WO2006010973A1

WO2006010973A1 - Hybrid static ram

Info

Publication number: WO2006010973A1
Application number: PCT/IB2004/002143
Authority: WO
Inventors: Bassem Mohamed Fouli
Original assignee: Bassem Mohamed Fouli
Priority date: 2004-06-25
Filing date: 2004-06-25
Publication date: 2006-02-02

Abstract

A static RAM is the fastest memory type, but due to the high power emission in the old designs ( High dynamic power emission in case of a CMOS SRAM, and high Static power emission in case of NMOS SRAM ), it wasn't used in a wide scale, and accordingly the paging system arouse to make use of it beside the other types of slower memory types. This new design is an introduction of a memory cell of more number of components, but with an extremely low static and dynamic power emission, which enables higher integration of the whole system, and thus obtaining a high dense system which will help using Static RAM in a wider scale, and it is expected to substitute the dynamic RAM completely, which means a very high efficiency in the overall speed of a digital system. Besides, due to the minimization of component size, the parasitic capacitances has lower values and accordingly the new design achieved a much higher speed than a normal NMOS static RAM. Now regarding the physical origin of the idea, it is simply introducing weak supply points to a normal CMOS inverter transistors which had a direct contact to supply and ground points, this is done by simply adding resistive loads to each transistor, and thus avoiding the usual short circuit which caused high dynamic current per cell in the NMOS SRAM before. It is logical that the addition of resistive loads caused a tradeoff in time response of the CMOS SRAM, but CMOS SRAM isn't our reference here, our reference is NMOS SRAM which is the working SRAM nowadays. So comparing to NMOS, here will be a little tradeoff assuming using components of the same dimensions, but remember that the low power emission in the new design will lead to a severe minimization per component, this will not only compensate the little tradeoff, but also the time response of the new design will be extremely much better.

Description

Hybrid static RAM Technical field:

This design is in the field of digital electronics, at the level of electronic implementation Background Art:

It is well known that a design of static RAM is based on: two unstable circuits each of them has its output introduces a strong point biasing to the other circuit input to provide mutual stability between the two circuits, in other words each circuit is characterized by only one operating point of stability which is the point that puts the whole system in its state of minimum energy (according to the physical rule that states that a system tends to reach the state of minimum energy) while any other operating point puts the system into a higher level of energy which means that it can't be a point of stable operation, but if another system is used to provide the input of the first system with a strong biasing, the circuit acquires another operating point of a stable nature, where this new point puts the whole system in a state of minimum energy.

The static memory can be described as if it were a ball representing the operating point, traveling between the two sides of a mountain, where the two sides of the mountain (on the ground) are two operating points of minimum state of potential energy while the top of the mountain is a point of a high state of energy, so the ball tend to fall into either sides of the mountain where there is no stable points on its narrow top of high potential energy. So, typically a static memory cell structure is usually built from two inverters put back to back in order to provide each others with biasing which causes stability. The most important designs introduced to implement an inverter which is the building block of a static memory cell were two; the l^sl was a simple MOSfet transistor with a simple resistive load (Typically a Polysilicon resistance to decrease its size) and practically this is the working model by manufacturers nowadays, the 2^nd was a CMOS inverter with an N-channel and another P-channel MOSfet transistors. The first design is characterized by its high static current which decreased its integrability and forced a manufacturer to spread it over a large area in order to provide a suitable heat dissipation area where the value of the resistive load was kept as low as possible in order not to affect the inverter speed during writing process. The second design is characterized by the instantaneous short circuit between input from the writing circuit and to either the power supply or the ground exclusively, this occurs each time the memory logic changes.

In the ideal case where the two access lines are fully synchronized this problem doesn't appear where the transistor whose state was ON changes into OFF state together with the introduction of the new logic to its drain, so no short circuit occurs between writing circuit and either the power supply or the ground, but practically a delay appears between the access signals of the two access lines which leads to the occurrence of the undesired short circuit and consequently the very high dynamic current, besides the life time of the memory cell components dramatically decreases.

So, considering a modification to the above CMOS technology, the question was how to avoid the undesired short circuit even in case of the asynchronized access signals. Disclosure of invention:

The design of the new static RAM being a modification to the CMOS technology, but instead of the strong supply and ground points, weak points are obtained and used instead, these points are obtained by adding resistive loads between each supply or ground point and the source of the adjacent transistor so as to turn the transistor source (which is the supply point for each transistor) into a weak point, now these weak points are immune against the affect of the asynchronized access signals. Remember that the introduced weak points feed the O/P point of each inverter which is in turn the supply point of the other inverter but remember also that we use MOSfet technology where the I/P of the inverter are MOSfet gates, which means that weakening the O/P point within a certain limit doesn't make it insufficient to supply the I/P point with an enough strong biasing because the I/P point is still much weaker, also note that introducing additional components is supposed to increase the final size of a memory cell, but don't forget that we are speaking in terms of integration, the new design contains more components but due to low amount of power emission ( from the simulation results static power is in the range of 50 milliWatt per milliard (1E9) cells), also dynamic current peak is in the range of a micro Ampere which means that the new design can be highly integrated inside an IC with the minimum dimensions provided by technology, which means a lot of diminishing in the final size of an integrated chip. For farther understanding of this point, read the following argument: To explain the concept of "minimum dimensions", you should know that dimension of a Chip depends on two parameters: Power emission per cell and no. of components per cell, to explain the effect of each parameter on dimension minimization here is a simple example:

Assume a design having an average current in the range of 1 μA per cell, this puts constraints on the technology used where you can't use minimum dimension technology because the area of the cell will not be enough to dissipate such large amount of heat emission, so a 10 μm technology ( λ =10 ) is used, now if this design consists of 6 components and the average dimensions of a component is 5λ x 5λ so the overall size of a cell equals 6 x (5x10) x (5x 10) = 15,000 μm², but assume another design of 10 components but with low power emission that allows us to use minimum dimensions technology let it be 0.1 μm technology ( λ = 0.1 ), so the overall size of a cell equals 10 x (5x0.1) x (5x0.1) = 2.5 μm².

So the second design is of much less size per cell than the first one although the first design consists of a less no. of components per cell, that's because power dissipation put constraints of technology usage.

Actually, the importance of dimensioning is to use the design in a wider scale, also dimensioning an electronic Chip leads to minimization of parasitic capacitances and consequently increasing the frequency (Speed) of operation.

But now the question is: Does the introduction of more components -especially resistors- cause any trade off of speed; the answer of these questions will need the following argument:

For the purpose of comparison, I'll compare my technology to the current technology used in static memory fabrication which is NMOS technology.

Firstly, it's not fair to just count the number of resistors existing in a design to determine the time response; however the right approach here is to use the concept of current path which is the effective measurement for time response, now look at the figure and read the design analysis from the point of view of "Current path". I'll take the case of static operation for the purpose of simplicity, and then generalize the argument to include the dynamic operation.

Let's take the case of 5V as the initial signal at the input of the first stage (stage of ( Ml & M2 )) inverter, and a OV as the initial signal at the input of the second stage inverter (stage of ( M3 & M4 )).

Now we have both Ml & M4 "On" and both M2 & M3 "Off so the current path between "Output of the first stage" and "ground" exists while the current path between the "Output of the first stage" and the "5V supply point" is almost an open circuit, similarly the Current path between "Output of the second stage" and "5V supply point" exists while the Current path between "Output of the second stage" and the "Ground" is almost an open circuit, so the resultant circuit can be approximated to FIG 2.1 Now, look well at the resultant circuit, the working structure is the only part of the circuit that affects time response in our case, because it's the only active part of the circuit, Note that this effective circuit is very close to the current Static memory used nowadays - NMOS technology- (^"We have two transistors and two resistors as inverter stages), which means that the time response of the circuit will be in the same range of that of the current Art (static RAM) until Ml & M4 change state (Switch off). , .

The same analysis is applicable for the case of OV signal introduced to the input of the first inverter stage and a 5V signal introduced to the input of the second inverter stage, where the resultant structure can be approximated to FIG 2.2

Similarly this is the only part of the circuit that affects time response in the second case, because it's the only active part of the circuit, and it is very close to the current Static memory used nowadays -NMOS technology- (Where we have two transistors and two resistors as inverter stages), which means that the time response of the circuit will be in the same range of that of the current Art (static RAM) until Ml & M4 change state (Switch off).

Now when talking about the dynamic state of operation, note that it is assumed that Vthl + IVth2| < 5 V. Where Vthl is the threshold voltage of the NMOS transistors while Vth2 is the threshold voltage of the PMOS transistors, so according to the last note, the PMOS & NMOS transistor will switch On & Off exclusively, and there will be no operating point where an PMOS & an NMOS transistor are On at the same time, this means that at any time however in static or dynamic state, the whole circuit can be approximated to either of the above approximations, and consequently the time response is just the typical range of the currently used NMOS technology.

Now get ready to the surprise, this new design will achieve a better transient response than the old NMOS design, simply because the integrability of the new design will lead to minimization of parasitic capacitances all over transistor terminals, and consequently the time constant will even be much smaller than that of the currently working NMOS technology.

Now, the last question is why didn't any one think about this design before, despite its obvious simplicity??! ! !

The answer is simple too, the old SRAM designs were introduced long before VLSI or

ULSI technologies were introduced, so during this period the only constraint put on cell size dimensions was the no. of components per cell, but no constraints were introduced due to power emission because the cell area was already big due to the available technologies these days, so there was no need to put another design for static RAM because the existing design was already of minimum no. of components and consequently the minimum dimensions, and even after when VLSI & ULSI technologies were introduced, no one tried to think about a new SRAM design but I did ,and I succeeded.

Brief description of the Drawings:

Notes:

The +5v signal represents a logic 1 while a Zero signal represents a logic 0.

The circuit structure used here is for the purpose of description and simulation. Referring to FIG.l, When an enough +ve Cont signal is introduced to the Gate of M5 it is driven into On state so an I/P signal can be introduced through its Source and delivered to the Drain, and when an enough -ve Cont signal is introduced to the Gate of M5 it is driven into off state and no signal is introduced from its Source to the Drain. When a +ve 5 V is introduced to the Gates of the first transistors (Ml & M2) M2 is off where the voltage difference between its Gate and its Source is 0 which is insufficient to drive it on, but Ml is derived On because the voltage difference between its Gate and Source is +ve 5 V which exceeds the threshold voltage, now Ml is On but no current passes through between Source and Drain because the node at its Drain is not in contact with any point through a finite resistance, where it faces almost infinite impedance from the Gates of M3 & M4 and the Drain of M2 which is off, so the voltage on the Drain of

Ml is the same as that on its source so it acquires 0 voltage.

Now consider the case of introducing a OV to the Gate of the same transistors (Ml &

M2), Ml is off where the voltage difference between its Gate and its Source is 0 and insufficient to drive it on, but M2 is driven On because the voltage between its Gate and

Source is -ve 5V which exceeds the threshold voltage, now M2 is On but no current passes through between Source and Drain because the node at its Drain is not in contact with any point through a finite resistance, where it faces almost infinite impedance from the Gates of M3 & M4 and the Drain of Ml which is off, so the voltage on the Drain of

M2 is the same as that on its source so it acquires a +ve 5V voltage.

So the signal introduced is now inverted on the O/P of the 1^st stage, then it's inverted back again on the O/P of the 2^nd stage to recover back its original value at the I/P of the

1^st stage and is introduced again to the I/P of the 1^st stage so as to keep its state when no signal is introduced through M5.

Now the final Figure for the Hybrid Static RAM, is shown in FIG.3

Best mode for carrying out the Invention:

This design being a modification of CMOS technology, Is supposed to be implemented through the same steps of a CMOS technology, with slight differences due to the introduction of resistive components.

Industrial Applicability:

This design is completely applicable because it is just a modification to an old design at the level of electronic implementation, it needs no new technology for implementation at the level of ULSI ( Chip ) implementation.

Claims

Claims:

The element to be protected is simply the introduction of resistive components or components that act as resistive components to the CMOS SRAM design for the purpose of avoiding the high dynamic current that used to accompany the process of changing state of a CMOS SRAM cell.