WO2006008721A3 - Emulation and debug interfaces for testing an integrated circuit with an asynchronous microcontroller - Google Patents

Emulation and debug interfaces for testing an integrated circuit with an asynchronous microcontroller Download PDF

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Publication number
WO2006008721A3
WO2006008721A3 PCT/IB2005/052372 IB2005052372W WO2006008721A3 WO 2006008721 A3 WO2006008721 A3 WO 2006008721A3 IB 2005052372 W IB2005052372 W IB 2005052372W WO 2006008721 A3 WO2006008721 A3 WO 2006008721A3
Authority
WO
WIPO (PCT)
Prior art keywords
emulation
testing
integrated circuit
asynchronous microcontroller
microcontroller
Prior art date
Application number
PCT/IB2005/052372
Other languages
French (fr)
Other versions
WO2006008721A2 (en
Inventor
Fabrizio Campanale
Jens Muttersbach
Andrea Foni
Original Assignee
Koninkl Philips Electronics Nv
Philips Corp
Fabrizio Campanale
Jens Muttersbach
Andrea Foni
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Philips Corp, Fabrizio Campanale, Jens Muttersbach, Andrea Foni filed Critical Koninkl Philips Electronics Nv
Priority to JP2007520966A priority Critical patent/JP2008507025A/en
Priority to EP05758728A priority patent/EP1782204A2/en
Publication of WO2006008721A2 publication Critical patent/WO2006008721A2/en
Publication of WO2006008721A3 publication Critical patent/WO2006008721A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3648—Software debugging using additional hardware
    • G06F11/3656—Software debugging using additional hardware using a specific debug interface

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Debugging And Monitoring (AREA)

Abstract

A target devi ce integrated circuit with an embedded asynchronous microcontroller is fitted with a standard JTAG-TAP interface. On board the IC a TAP port controller and emulation interface are able to intercept and substitute every instruction being fetched from a code memory. An external emulation PC has the ability to inspect on-board data and code memories by instruc Icing the embedded asynchronous microcontroller to read and write them to the JTAG-TAP interface. Single-stepping and breakpoint registers are provided for debugging and testing by the external emulation PC.
PCT/IB2005/052372 2004-07-16 2005-07-16 Emulation and debug interfaces for testing an integrated circuit with an asynchronous microcontroller WO2006008721A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007520966A JP2008507025A (en) 2004-07-16 2005-07-16 Emulation and debug interface for integrated circuit testing
EP05758728A EP1782204A2 (en) 2004-07-16 2005-07-16 Emulation and debug interfaces for testing an integrated circuit with an asynchronous microcontroller

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US58856204P 2004-07-16 2004-07-16
US60/588,562 2004-07-16
US63211204P 2004-11-30 2004-11-30
US60/632,112 2004-11-30

Publications (2)

Publication Number Publication Date
WO2006008721A2 WO2006008721A2 (en) 2006-01-26
WO2006008721A3 true WO2006008721A3 (en) 2006-12-21

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2005/052372 WO2006008721A2 (en) 2004-07-16 2005-07-16 Emulation and debug interfaces for testing an integrated circuit with an asynchronous microcontroller

Country Status (3)

Country Link
EP (1) EP1782204A2 (en)
JP (1) JP2008507025A (en)
WO (1) WO2006008721A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7263427B2 (en) 2020-08-31 2023-04-24 ベイジン バイドゥ ネットコム サイエンス テクノロジー カンパニー リミテッド Methods, apparatus, electronic devices, computer readable storage media and computer programs for validating chips

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070214389A1 (en) * 2006-03-08 2007-09-13 Severson Matthew L JTAG power collapse debug
DE102008019861A1 (en) * 2008-04-17 2009-10-29 Göpel electronic GmbH Method for controlling connection pins of an emulatable component and arrangement for carrying out the method
CN101814054B (en) * 2010-03-23 2012-05-02 苏州国芯科技有限公司 Instruction tracing controller for debugging microcontroller
CN104239176A (en) * 2014-10-16 2014-12-24 成都傅立叶电子科技有限公司 Multi-user multi-target remote JTAG debugging system based on Internet
CN105528270B (en) * 2015-12-30 2018-03-30 东风商用车有限公司 JTAG (Joint test action group) and BDM (brain-based data model) integrated debugging interface and using method thereof
CN111984521B (en) * 2019-05-23 2022-11-29 核工业理化工程研究院 Board-level debugging method without JTAG (Joint test action group) intervention
CN111753475B (en) * 2020-06-28 2022-06-28 福建工程学院 Method for simulating MSI digital logic chip based on Cortex-M0+ microcontroller
CN117251314A (en) * 2022-06-09 2023-12-19 象帝先计算技术(重庆)有限公司 Simulation debugging system and method
CN117632611B (en) * 2023-12-05 2024-05-14 北京中天星控科技开发有限公司 General testing device for microprocessor chip

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020065646A1 (en) * 2000-09-11 2002-05-30 Waldie Arthur H. Embedded debug system using an auxiliary instruction queue

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020065646A1 (en) * 2000-09-11 2002-05-30 Waldie Arthur H. Embedded debug system using an auxiliary instruction queue

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
BEEREL P A: "Asynchronous circuits: an increasingly practical design solution", QUALITY ELECTRONIC DESIGN, 2002. PROCEEDINGS. INTERNATIONAL SYMPOSIUM ON 18-21 MARCH 2002, PISCATAWAY, NJ, USA,IEEE, 18 March 2002 (2002-03-18), pages 367 - 372, XP010589388, ISBN: 0-7695-1561-4 *
GARSIDE J D ET AL: "AMULET3i-an asynchronous system-on-chip", ADVANCED RESEARCH IN ASYNCHRONOUS CIRCUITS AND SYSTEMS, 2000. (ASYNC 2000). PROCEEDINGS. SIXTH INTERNATIONAL SYMPOSIUM ON EILAT, ISRAEL 2-6 APRIL 2000, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 2 April 2000 (2000-04-02), pages 162 - 175, XP010377325, ISBN: 0-7695-0586-4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7263427B2 (en) 2020-08-31 2023-04-24 ベイジン バイドゥ ネットコム サイエンス テクノロジー カンパニー リミテッド Methods, apparatus, electronic devices, computer readable storage media and computer programs for validating chips

Also Published As

Publication number Publication date
EP1782204A2 (en) 2007-05-09
JP2008507025A (en) 2008-03-06
WO2006008721A2 (en) 2006-01-26

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