WO2006003368A2

WO2006003368A2 - Improved c-element and logic reduction and completion detection circuits

Info

Publication number: WO2006003368A2
Application number: PCT/GB2005/002412
Authority: WO
Inventors: Damon Thompson
Original assignee: The University Court Of The University Of Edinburgh
Priority date: 2004-07-01
Filing date: 2005-06-20
Publication date: 2006-01-12
Also published as: WO2006003368A3

Abstract

A configurable C-element logic cell and design method that can provide multiple variations of the C-element function from a one-off, custom cell implementation. Inputs of the C-element are tied off to supply voltages or other inputs. There are also provided circuits for logic reduction and completion detection having reduced circuit area and increased performance. The logic reduction circuits use wired logic in which a wired logic net has a load enabled from a high-impedance state. In a completion detection circuit, the enable signal of the load may be driven by the an exclusive OR of the completion outputs of both the an asynchronous module whose completion is being detected and an upstream module.

Description

Improved C-element and logic reduction and completion detection circuits

This invention relates to asynchronous digital VLSI (Very Large Scale Integration) circuits, in particular a configurable standard cell for implementing the C-element function and completion detection for self timed, asynchronous circuits.

In the field of asynchronous digital circuits, C-elements are commonly used in the control circuits of existing asynchronous logic designs. The function of the C- element is to merge its logical input values. When these are in agreement, the output of a C-element goes high when, and only when, all of its inputs are high. The output of the C-element goes low when, and only when, all of its inputs are low. The C-element does not have a conventional complementary Boolean function. The 'switch-on¹ and 'switch-off' functions of the C-element are not complementary as they are with standard Boolean functions and a unique logical expression is required for both. The C-element is therefore not offered as a standard cell by silicon library providers. In order to use C-elements in an asynchronous logic design it is currently necessary to perform a custom design of each required component and integrate these with existing cell libraries. It would be advantageous to provide multiple variations of the C-element function on a one-off, custom cell implementation.

In the field of asynchronous digital circuits, completion detection circuitry is required to decode the output state of a module. This circuit is generally realised as a logic reduction function, implemented as a MuIler C- element tree or parallel AND and OR trees.

The problem with this is that the logic reduction trees used incur an area overhead and a performance degradation that is proportional to the asynchronous module's output width.

Wired logic (also referred to as open-collector or open- drain) was originally used to connect multiple drivers to board level data buses in LSI digital systems. The application of wired logic circuits in modern ASIC (Application Specific Integrated Circuit) design has largely been superseded by tri-state logic. The main reason for this is that logic cells used to implement wired logic functions are not complementary in nature and there is a steady static power consumption when a wired logic net is being driven low.

It would be advantageous to provide a logic reduction function and completion detection functions which offer reduced area and increased performance characteristics for large output width asynchronous modules. It would be further advantageous to benefit from the simplicity and speed of wired logic in implementing reduction functions and completion detection functions.

It is an object of an aspect of the present invention to provide a C-element integrated circuit that is configurable with respect to its number of inputs.

It is a further object of an aspect of the present invention to provide an improved method of designing a C- element integrated circuit.

It is an object of an aspect of the present invention to provide logic reduction functionality with reduced circuit area and increased performance.

It is a further object of an aspect of the present invention to provide completion detection functionality with reduced circuit area and increased performance.

According to a first aspect of the present invention, there is provided a configurable C-element integrated circuit comprising: • a plurality of inputs ; • an output; • a C-element; and • a connecting means for electrically connecting a first input of said plurality of inputs to a node, so as to tie off said first input.

Preferably said C-element further comprises: • a state transition means for operating on state transitions of said plurality of inputs and changing the state of said output responsive to said state transitions; and • a state holding means for holding the state of said output.

Preferably said node is a supply voltage.

Preferably, said first input is a negative asymmetric input and said supply voltage is a lower supply voltage.

Preferably, said state transition means further comprises a pull-down stack comprising a plurality of pull-down transistors each having a pull-down gate and said negative asymmetric input is a pull-down gate.

Alternatively, said first input is a positive asymmetric input and said supply voltage is a higher supply voltage.

Alternatively, said state transition means further comprises a pull-up stack comprising a plurality of pull- up transistors, each having a pull-up gate and said positive asymmetric input is a pull-up gate.

Alternatively said node is a second input of said plurality of inputs.

Preferably, said first and second inputs are one each of a negative asymmetric input and a positive asymmetric input. Alternatively, said first and second inputs are both symmetric inputs.

Alternatively, said first and second inputs are one each. of an asymmetric input and a symmetric input.

Preferably said state holding means is optimised to hold the state of said output responsive to said state transitions of all of said plurality of inputs.

According to a second aspect of the present invention there is provided a method for designing a C-element integrated circuit comprising the steps: • providing a C-element with a plurality of inputs; and • selectively reducing the number of said plurality of inputs by electrically connecting a first input of said plurality of inputs to a node, so as to tie off said first input.

Preferably said node is a supply voltage.

Preferably, said first input is in a negative asymmetric input and said supply voltage is a lower supply voltage.

Alternatively, said first input is an asymmetric positive input and said supply voltage is a higher supply voltage.

Alternatively said node is a second input of said plurality of inputs. Preferably, said first and second inputs are one each of a negative asymmetric input and a positive asymmetric input.

Alternatively, said first and second inputs are both symmetric inputs.

Alternatively, said first and second inputs are one each of an asymmetric input and a symmetric input.

According to a third aspect of the present invention, there is provided a circuit for logic reduction in asynchronous circuits comprising: • a plurality of inputs; • an output; • a net means for providing a logic operation, said net means comprising wired logic; and • a switchable load means for providing a load for said net means, said switchable load comprising an enable input, said switchable load being switchable between a load state and a high-impedance state responsive to said enable input.

Preferably, said wired logic comprises open-drain logic comprising n-type transistors.

Alternatively, said wired logic comprises open-source logic comprising p-type transistors.

Preferably, said wired logic comprises transistors connected with their channels in series so as to provide AND functionality. Alternatively, said wired logic comprises transistors connected with their channels in parallel so as to provide NOR functionality.

Preferably, said switchable load means comprises a plurality of transistors connected with their channels in series and with a common gate.

According to a fourth aspect of the present invention, there is provided a circuit for completion detection in asynchronous circuits comprising: • first and second circuits for logic reduction in accordance with the third aspect of the present invention; and • an output latch means for combining and latching the output of said first and second circuits for logic reduction, said output latch means comprising a completion output.

Preferably, said first circuit for logic reduction comprises wired logic providing AND functionality and said second circuit for logic reduction comprises wired logic providing NOR functionality.

Preferably, said switchable load means is switchable responsive to the input and output states of the asynchronous module that said circuit for completion detection is detecting the completion of.

Preferably, said switchable load means is switchable responsive to said completion output. More preferably, said switchable load means is switchable responsive to said completion output and the completion output of an upstream asynchronous logic module.

Most preferably, said switchable load means is switchable responsive to an exclusive OR of said completion output and the completion output of an upstream asynchronous logic module.

Preferably, said output latch means comprises said configurable C-element integrated circuit according to the first aspect.

The present invention will now be described by way of example only and with reference to the accompanying figures, in which :

Figure 1 illustrates in schematic form a prior art completion detection circuit comprising Muller C- elements.

Figure 2 illustrates in schematic form a prior art completion detection circuit comprising parallel AND reduce and OR reduce trees merged with a final C-element function.

Figure 3 illustrates in schematic form a prior art completion detection circuit comprising a NAND-NOR tree structure with a combining Muller C-element.

Figure 4 illustrates in schematic form a logic reduction circuit comprising NOR gates in accordance with the present invention. Figure 5 illustrates in schematic form a logic reduction circuit comprising AND gates in accordance with the present invention.

Figure 6 illustrates in schematic form a completion detection circuit in accordance with a preferred embodiment of the present invention and comprising the logic reduction circuits of figures 4 and 5.

Figure 7 illustrates in schematic form a transistor level schematic of a four-input, open-drain CMOS NOR cell in accordance with the present invention.

Figure 8 illustrates in schematic form a transistor level schematic of a four-input, open-drain CMOS AND cell in accordance with the present invention.

Figure 9 illustrates in schematic form the transistor level schematic of a switchable load in accordance with the present invention.

Figure 10 illustrates in schematic form a 32-bit input wired logic completion detection circuit in accordance with the present invention.

Figure 11 illustrates the circuit diagram and schematic symbol for an unconfigured six input C-element with four asymmetric and two symmetric inputs.

Figures 12 to 14 illustrate the schematic symbol, the configuration connections and the silicon layout routing of a variety of different configurations of the configurable C-element (CCE) according to a preferred embodiment of the present invention.

Embodiments according to the first and second aspects of the present invention are a configurable C-element logic cell and design method, that can provide multiple variations of the C-element function from a one-off, custom cell implementation.

Embodiments according to the third and fourth aspects of the present invention are a set of circuits for logic reduction and completion detection using wired logic for use in asynchronous logic circuits. These embodiments will be described first.

Improved logic reduction and completion detection circuits:

There are generally two styles of determining circuit completion for asynchronous logic modules: completion prediction and completion detection. Completion prediction uses a local, matched delay, which (at least) equals the worst case performance of the associated asynchronous module. As an enhancement, this local delay element may be dynamically switchable, according to current module input values, to provide a more appropriate delay for the current operation. Completion detection techniques use dedicated circuitry to deduce the state of an asynchronous module. Completion detection techniques include: current sensing, activity monitoring and output decoding, amongst others. Output decoding, using a delay-insensitive M-of-N data encoding, is the most popular approach. Where delay insensitive, M-of-N data encoding is employed, more than one wire (or net) is used to represent each logical data bit. For example, in the popular dual-rail (l-of-2) data encoding, two wires are used for every logical data bit in a binary word. The following table illustrates the normal encoding scheme used here:

00 - no data 01 - logical 0 (zero) 10 - logical 1 (one) 11 - erroneous state

There are other M-of-N encoding schemes which are in use: l-of-4 encoding has been shown to have beneficial switching and power characteristics; 3-of-7 encoding has been successfully used as an efficient, delay-insensitive scheme for on-chip data busses.

Delay-insensitive, M-of-N encoded data in asynchronous circuits requires a return-to-zero phase between each consecutive valid data value. In the dual-rail case, between each valid logic value for a given data bit (either "01" or "10"), both wires in the signal pair are returned to zero - the "no data" state. This is the basis for delay-insensitivity: a new data value can be identified on a dual-rail signal, regardless of the transmission delay on either wire in the signal pair, or the relative delay between them.

Used in an asynchronous digital system, as a dual-rail bit transition from "no data" to either of the valid data states represents a new data value, there is no need for an explicit accompanying request signal: the asynchronous request is effectively embedded in the dual-rail data bit transition.

The error state ("11" in dual-rail) is generally not used in normal circuit operation. It can, however, be used in error detection and self-testing circuitry.

The state (completion) detection function for a dual-rail signal-pair, or bit, is therefor a simple boolean OR operation. For a dual-rail signal pair X, consisting of wires Xl and XO, the corresponding detection signal, Xd, is calculated as:

Xd = Xl + XO

where '+' represents a boolean/logical OR operation.

Note: the above expression assumes that the error state, "11" in dual-rail, is not used and will not occur. This is generally the case. If the error state is to be considered, the bit state detection function, in the dual-rail case, will become a logical XOR (exclusive OR) .

There is a corresponding bit state detection function for each M-of-N data encoding variant. The rest of this specification will consider completion detection circuitry with bit state signals, regardless of the data encoding scheme used, as circuit inputs.

In a practical asynchronous circuit case, a logic block will have multiple output bits, which combined represent the module's complete output word. A state detection function can be applied to each of these output bits, as discussed above. A completion detection circuit is then applied to merge and reduce each of the bit state detection signals down to a single module output state detection signal - the completion signal.

The completion signal follows the value of the bit state detection signals when, and only when, all bit state detection signals are the same.

This operation effectively has the same function as a large Muller C-Element. This can be realised as a tree of Muller C-Elements to perform the reduction operation required. Alternatively, the logic reduction operation can be realised as parallel AND reduce and OR reduce trees, merged with a final C-Element function.

The C-Element tree has a smaller circuit structure, in terms of cell count and internal nets, than the parallel AND and OR trees. The parallel AND and OR trees structure, however, is generally faster (due to the state-holding nature of the C-Element) but potentially hazardous.

A simple application of DeMorgan's theorem can be used to significantly improve the parallel AND and OR tree case: the AND reduce tree structure can be simplified to a NAND/NOR tree structure; the OR reduce tree can be simplified to a NOR/NAND tree. These simplified prior art versions are smaller and faster than their native AND and OR prior art counterparts. However they still use larger circuit area than is desirable. Gate-level schematics, illustrating the alternative completion detection circuits described, are illustrated in figures 1 to 3.

With reference to figure 1, a prior art completion detection circuit is shown that combines the sixteen inputs XdO to Xdl5 through the reduction tree of Muller C-elements 100 to provide a completion detection output 110.

With reference to figure 2, another completion detection circuit is shown. The sixteen inputs XdO to Xdl5 are fed into a reduction tree of AND gates 200 and the same inputs are also fed into a reduction tree of OR gates 210 and the outputs of the two trees is combined by the Muller C-element 220 to provide a completion detection output 230.

With reference to figure 3, the sixteen inputs XdO to Xdl5 are fed into four NAND gates 300, the outputs of which are combined by a NOR gate 310. The same sixteen inputs are fed into four NOR gates 320, the outputs of which are combined by a NAND gate 330. The two subsequent outputs are combined by a Muller C-element 340 to provide a completion detection output 350.

Wired logic (also referred to as open-collector or open- drain) was originally used to connect multiple drivers to board-level data buses in LSI digital systems.

An open-drain wired logic net can have multiple drivers which can only pull the net low; pull-up transistors are omitted from open-drain logic cell designs. A resistive pull-up load device is connected to the net to return and maintain it at a high voltage level, when it is not being pulled low by any of it's driving cells.

The logical function of the wired logic net can be effectively a boolean AND: when one or more of it's drivers are pulling it low, the net becomes low; when there are no drivers pulling the net low, it will become high. The term wired-AND is often used to describe this circuit configuration.

The application of wired logic circuits in modern ASIC design has largely been superseded by tri-state logic. The main reason for this is that logic cells used to implement wired logic functions are not complementary in nature, and there is steady static power consumption when a wired logic net is being driven low. However, wired logic is still employed for some applications such as serial peripheral busses and asynchronous interrupt interfaces.

The present invention is a wired logic implementation of the completion detection reduction functions, which offer reduced area and increased performance characteristics for large output width asynchronous modules.

The required AND and OR reduction functions are implemented as individual wired logic circuits. These two circuits are then merged, as they are in the tree AND/OR reduction circuits described above, with reference to figure 2, with a final Muller C-Element cell. Considering that a wired logic net with a default value of high (when un-driven, the net is pulled high) has an equivalent boolean AND function, the wired logic circuits for the reduction functions can be derived.

i. Considering the OR reduction of eight signals (bit state detection signals in this case) , A to H, the required function is:

D0 = A + B + C + D + E + F + G + H

The label ¹DO¹ is used here as the OR reduction tree effectively detects when all the bit state signals are low.

ii. Assuming four-input open-drain logic cells are available (the design of these cells will be discussed shortly), the function becomes:

DO = ( A + B + C + D ) + ( E + F + G + H )

iii . The resolution function for the wired logic net is, however, an AND, which would make the actual function:

DO = ( A + B + C + D ) . ( E + F + G + H )

iv. Following DeMorgan's theorem, it is possible to turn an AND function into an OR by inverting it's inputs and output, so the function becomes:

DO = ! ( ! ( A + B + C + D ) . ! ( E + F + G + H ) ) This function is logically equivalent to the required function. It can be realised as two four- input, open-drain NOR cells driving the wired-AND net, where the output of the wired-AND net is inverted.

With reference to figure 4 a circuit for logic reduction is shown according to the present invention. The circuit for this wired-AND OR reduction function 400 is shown for a 16 bit, rather than 8 bit, input case. The inputs XdO to Xdl5 are fed into four four-input open-drain (od) NOR gates 410, the output of which are all connected to a NOT gate 420 to provide an output Z. The outputs of the NOR gates are connected to a pull-up device 430 (or cell) that functions to return and maintain the wired logic net of gates 410 in a high state when not driven by an associated open-drain cell. Normally a pull-up device is responsible for the undesirable static power consumption characteristics of wired logic circuits. However, according to the present invention, the pull-up device or load is switchable using the enable (EN) input 440 to switch it to a high impedance state, thereby disabling the wired logic net of gates 410.

The derivation of the AND reduction function, given that the resolution function of the wired logic net is itself a boolean AND, is straight forward. Open-drain AND cells, providing the first level of reduction, can be used to drive the wired-AND net. The output of the wired- AND net is the required AND reduce function, and does not need any further modification. With reference to figure 5, a circuit for logic reduction is shown according to the present invention. The circuit for this wired-AND AND reduction function 500 is shown for a 16 bit input case. The inputs XdO to Xdl5 are fed into four four-input open-drain (od) AND gates 510, the output of which are all connected together to provide an output Z. The outputs of the AND gates are connected to a pull-up device 520 (or cell) that functions to return and maintain the wired logic net of gates 510 in a high state when not driven by an associated open-drain cell. The pull-up device or load is switchable using the enable input 530 to switch it to a high impedance state, thereby disabling the wired logic net of gates 510.

With reference to figure 6 that shows a completion detection circuit in accordance with a preferred embodiment of the present invention, the combination of the two wired logic reduction functions, complete with the final Muller C-Element to merge the results, is illustrated for a 16 bit input case. A wired logic reduction circuit of figure 4, 400 is combined with a wired logic reduction circuit of figure 5, 500 and the outputs combined by a Muller C-element 610 to provide a completion detection output 620. The NOT function provided by the NOT gate 420 of figure 4 may be integrated into the C-element 610 as a NOT input, as illustrated.

With reference to figure 7 a transistor level schematic of a four-input open-drain CMOS NOR cell is illustrated. The four n-channel transistors MNO to MN3 are connected with their channels in parallel so that their respective inputs A to D are combined into an output Z. With reference to Figure 8 a transistor level schematic of a four-input open-drain CMOS NAND cell is illustrated. The four n-channel transistors MNO to MN3 are connected with their channels in series so that their respective inputs A to D are combined into an output Z.

To complete the wired logic circuit functions, a pull-up device (or cell) is required to return and maintain the wired logic net in a high state when not driven by an associated open-drain cell. The pull-up device is responsible for the undesirable static power consumption characteristics of wired logic circuits.

In a self-timed asynchronous design, the completion detection circuitry is not required to be active all of the -time. Between each operation phase of an asynchronous module, there will generally be some redundant, idle time (due to the relative performance and behaviour of interconnecting modules) before the next phase of activity is required.

It is therefor possible to enable and disable the completion detection circuitry at appropriate times, and therefor remove any unnecessary static power consumption by the wired logic circuits.

By making the pull-up device switchable - in that it can be turned on and off - this provides a suitable mechanism for controlling the wired logic reduction functions. The design of the switchable CMOS pull-up device is shown in figure 9. With reference to figure 9, the enable input EN is connected to the gates of the two P-channel transistors MPO and MPl that have their channels connected in series to provide an output Z.

The Muller C-Element (610 in figure 6) merges the two logic reduction signals and also latches the result. At this point, the value of the logic reduction signals no longer needs to be maintained and the wired logic reduction circuits can be disabled.

The two wired logic reduction functions will have complementary values for the Muller C-Element to switch - one of which will be held low, regardless of the pull-up cell being disabled. It is therefor safe to disable the wired logic reduction functions without the C-Element switching again erroneously.

The wired logic reduction functions, and hence the completion detection circuit, can be enabled again when a new word (either valid data or a on-data token) is present at the asynchronous module's inputs.

The correct enabling of the completion detection circuits can be precisely determined from a module's own completion detection signal (asynchronous acknowledge signals) and that of its upstream driving/input module. These signals effectively indicate the input and output states of the asynchronous module - these can be either data or non-data (null) . The following table summarises the completion detection enable function, depending on the module's input and output state:

input output enable null null no data. null yes data data no null data yes

This function maps directly to an exclusive OR (XOR) function, and can be implemented immediately as a standard logic cell.

It is possible to use multiple (more than two) wired logic reduction circuits within a completion detection circuit. The example presented so far has two 16 bit input wired logic nets (one AMD reduce, one OR reduce) into a two input Muller C-Element; it is possible to implement the same function with four 8 bit input wired logic nets (two AND reduce and two OR reduce) into a four input Muller C-Element. This alternative implementation incurs a small area penalty, but offers a significant performance increase.

This implementation of a 32 bit input wired logic completion detection circuit is illustrated in figure 10. This approach scales well to larger output width asynchronous modules. With reference to figure 10, the inputs XdO and Xdl5 1010 are fed into logic reduction circuits 400 and 500 as are input XdI6 to Xd31 1020 and the outputs of the logic reduction circuits are combined by a Muller C-element 1030 to provide a completion detection output 1040.

When implementing wired logic functions on silicon, careful consideration of cell placement and net routing is required. Generally, open-drain cells, and associated pull-up cells, for a given wired logic net need to be located, or clustered, as locally as possible. The routing of wired logic nets needs to be as short and as direct as possible.

Logic cell designs, from an existing standard cell library, can be modified to provide the wired logic functions required. Alternatively, open-drain cell drivers and switchable pull-up cells can be designed, as described previously, and implemented for a chosen CMOS technology.

Simple standard logic cells, that provide a single level of logic, can be modified for open-drain operation. These typically include NAND, NOR and INV cells.

By connecting the output pin of an existing cell to it's VDD pin, this effectively disables any PMOS pull-up devices, leaving only the pull-down devices as active. This effectively makes the large VDD pin of the original cell now an output pin - this helps considerably with the placement and routing considerations for wired logic nets. Special care needs to be taken to isolate the output (VDD) pins of the modified open-drain cells from the normal VDD connection of other surrounding standard cells.

An open-drain AND cell, as required in the wired logic completion detection circuits presented, can be created from an existing AND cell and a modified INV cell to operate in an open-drain mode. Switchable pull-up cells can be implemented by using strong INV standard logic cells. Here, the output pin is connected to the GND pin of the standard cell. The pull- down device is bypassed and permanently disabled. The large GND pin can now be used for connection to the wired logic net.

It will be clear to one skilled in the art of VLSI design how to implement the present invention in silicon. Similarly, one skilled in the art will appreciate that the present invention is applicable to all M-of-N encoding schemes, not just l-of-2.

Improved C-Element:

The logic equations for a two-input, C-Element function are:

Z1 = A * B + Z * ( A + B ) ZO = !A * !B + !Z * ( !A + !B )

and in the general, more than two input, case:

Zl = A * B * C * ... + Z * ( A + B + C + ... ) ZO = !A * IB * !C * ... + !Z * ( !A + IB + !C + ... )

where A, B, ... are the input values Z is the current output value Zl represents the output rising ZO represents the output falling * represents the logical AND operation + represents the logical OR operation The first term in the equation, A * B * C * describes the output state transition behaviour; the second term in the equation, Z * ( A + B + C + ... ), describes the output state holding behaviour.

In the description of the traditional C-Element operation given, all inputs are considered in both of the output switching functions (rising and falling) . This is known as a symmetric C-Element.

It is possible to have C-Element inputs that contribute to only one of the output switching functions. A simple example is:

Z1 = A * B + Z * ( A + B ) ZO = !B + IZ * ( !A + !B )

where input A is only considered in the output rising function. This is known as an asymmetric C-Element.

For a given number of inputs, there are multiple asymmetric C-Element functions, but only one symmetric function.

As with conventional logic cell realisations, it is possible to invert the inputs and outputs of a C-Element design to produce further variations of the component as required.

In the Weak Feedback implementation of C-Element logic cells only the transition terms of the output switching functions are implemented here. This leads to a stack of pmos pull-up devices, and a stack of nmos pull-down devices. The state holding behaviour of the C-Element's operation is realised by a weak feedback inverter which essentially forms an output latch. This feedback inverter drives, and maintains, the internal node of the cell, when it is not driven by either the pull-up or pull-down circuits. For an output transition, the pull- up/down circuits must over-drive the weak feedback inverter.

It can be shown that for input combinations beyond the symmetric, two-input case, the Weak-feedback implementation style becomes preferable over alternative C-element implementations in terms of design, performance and area.

It is also worth noting that C-Element functions can be realised as standard logic cell networks. Combinatorial logic networks with an output feedback path, or an SR latch with separate set and reset circuits, can be used. However, these implementation styles lead to very large, and very slow, C-Element functions when compared to a dedicated logic cell design. There are also timing hazards to deal with.

An asynchronous circuit design will typically require a range of C-Element logic cells, with different input combinations and polarities. Each C-Element design, implemented in any of the styles discussed, has a fixed, non-variable functionality. Therefore, each C-Element logic cell variation required will have to be custom designed, implemented and integrated with a target silicon cell library. This process requires a significant amount of designer effort for each cell. This process will involve the following tasks:

1. Design 2. Optimisation 3. Layout 4. Verification 5. Extraction 6. Characterisation 7. Library integration

There will be at least three simulation tasks - at steps 1/ 2 and 5 - which may result in the design returning to previous steps. The library integration task involves the generation of multiple views of the cell design for various EDA purposes such as simulation, synthesis, timing analysis, placement, routing, ...

One significant advantage of using standard logic cells from a library, is that these have been fully verified by the library provider and generally certified by the target silicon fabrication foundry. Each custom cell added to a logic library, and used in a silicon design, increases the amount uncertified layout.

The present invention is a new configurable C-Element logic cell design, that can provide multiple variations of the C-Element function from a one-off, custom cell implementation. The main advantage is that a single custom cell design task, as described above, is required, to produced a generic cell that can be configured to perform several C-Element functions, and significantly reduce the custom cell design effort, and associated hazards, described above.

The configurable C-Eleinent cell design uses serial pull- up and pull-down transistor stacks to implement state transition functions only. The state holding function of the cell is realised with an inverter latch, as it is in the Weak-feedback C-Element design style.

When designing the configurable C-Element, each device in a transition function stack can be setup as a single, asymmetric input. Alternatively, complementary devices (one from the pull-up stack, and one from the pull-down stack) can be tied together to provide a conventional, symmetric input. The choice of the number of inputs, and whether these are setup to have symmetric or asymmetric function behaviours, is a decision based on the variety of C-Element cells required and the intended CMOS technology properties.

Note that the above paragraph applies to the design and implementation of the configurable C-Element, not to its later use as a multi-purpose cell.

The resulting cell design has a generic C-Element function, which can be configured to have a more specific behaviour by connecting the existing, hard-wired inputs in different ways. In summary:

i. asymmetric, single transistor inputs can be

a. left as asymmetric inputs b. tied to the relevant supply voltage, and disabled, i.e. pull-up (p-type) devices are tied to Ov, pull-down (n-type) devices are tied to the supply voltage

c. coupled to an asymmetric input in the opposite stack to form a conventional, symmetric input

ii. symmetric, coupled transistor inputs can be

a. left as symmetric inputs

b. tied to either another symmetric input or an asymmetric input, and disabled

It is worth noting that an asymmetric C-Element input can be expanded by using a simple logic cell to increase it's - fan-in: a simple OR gate can be used to reduce multiple inputs to a single negative asymmetric input; a simple AND gate can be used to reduce multiple inputs to a single positive asymmetric input.

With reference to Figure 11a, a configurable C-element is illustrated, with six inputs 1100. A state transition subcircuit 1102 with a pull-down stack MPO to MP3 connected to Vss and a pull-up stack MNO to MN3 connected to Vdd. The state holding subcircuit 1104 consists of an output inverter 1106 comprising transistors MP4 and MN4, and a weak feed-back inverter 1108 comprising resized transistors MP5 and MN5. Finally, an output is shown 1110. Of the inputs two are positive asymmetric inputs labelled a and b, two are symmetric inputs labelled c and d, and two are negative asymmetric labelled e and f. The output is labelled z. The upper case labels A to F represent the logic inputs that in this case correspond to the input nodes a to f. The labelling of the inputs and outputs with lower case letters is used in the subsequent figures to identify the nodes on the schematic symbols and the silicon layout routing diagrams.

Figure lib shows the schematic symbol corresponding to the circuit of figure 11a with logic inputs A to F and output Z. The positive asymmetric logic inputs A and B are labelled with a '+' and the negative asymmetric logic inputs E and F are labelled with a ' - ' .

The inputs, and transition function transistor stacks, are summarised as follows:

i. transistor gates MPO and MPl are connected directly to inputs f and e respectively - these are set up as negative asymmetric inputs,

ii. transistor gates MP2 and MNl are coupled together and connected to input d: this is set up as a symmetric input,

iii. transistor gates MP3 and MNO are coupled together and connected to input c: this is set up as a symmetric input,

iv. transistor gates MN2 and MN3 are connected directly to inputs b and a respectively - these are set up as negative asymmetric inputs. Without any extra configuration, this cell can be used directly as a 2-2-2 (2 negative inputs, 2 positive inputs, 2 symmetric inputs) C-Element. The schematic symbol for the native/direct use of this cell is shown in figure lib.

This particular cell has 27 different functional variations, depending on how it is configured, at the cell routing stage of the standard cell design flow (discussed in more detail below) .

Unless used in it's native/direct mode, a configurable C- Element generally has slightly decreased performance, and increased silicon cell area, when compared with the a functionally equivalent Weak-Feedback C-Element implementation. The native/direct mode is identical to the Weak-Feedback implementation of the same cell.

Disabled Configurable C-Element inputs - either tied to a supply rail or another input - effectively increase the pull-up or pull-down resistance (decrease the pull- up/down strength) of the function transition stacks, and therefor slows down input-output propagation time.

Tied inputs also incur redundant devices, which increase the effective silicon area of the resulting C-Element cell. These two factors, although small in practice, represent the design trade-off in using a single configurable C-Element logic cell versus several custom cell implementations.

The 2-2-2 cell design shown is only one example of a Configurable C-Element implementation. Within the technology parameters, and standard cell dimension, of the target silicon fabrication process, there are a number of possible CCE implementations. Each implementation has a unique native/direct mode of operation and a range of configurations. Various CCE implementations can be realised by changing the transition function stack parameters, summarised as follows:

i. The number of devices in the pull-up and pull-down stacks can be varied. The amount of devices that can be used in series will be limited by the silicon technology. The number of pull-up and pull-down devices does not need to be equal. The choice of pull-up and pull-down devices depends on the range, and type, of CCE configurations required.

ii. The number of pull-up and pull-down devices that are coupled to produce symmetric inputs can be varied. The choice of coupled devices, or symmetric inputs, again depends on the range, and type, of CCE configurations required.

Once a single CCE standard cell has been implemented and integrated into the required library formats, it can be employed and referenced as any of it's alternative configurations, within a conventional standard cell based design flow.

For the one layout view, multiple simulation and synthesis views can exist, each describing a different configuration of the CCE cell. This is achieved by using hierarchical abstracts, or input-output wrappers, which instantiate the same CCE cell, but with different input configurations (normal, tied or coupled) to provide virtual cells with alternative C-Element functionalities.

Each virtual C-Element (configured CCE cell) has a unique view, and is considered as a unique cell, during the HDL (Hardware Description Language) specification, simulation and synthesis stages.

When it comes to placing and routing the cells as part of the silicon layout, the virtual C-Element (hierarchical abstract) is flattened. This produces a CCE cell instance with the required local net connectivity to configure the inputs and setup the CCE with the required functionality.

There are two approaches to implementing the programmed CCE cells in the final silicon layout. These are summarised as follows:

i. The local nets, to program the CCE functionality, can be connected at the routing stage of silicon layout. Using the lowest level of metal routing available, connections between CCE cell input pins and power strips can be prioritised and automatically routed.

ii. For CCE programs in common use, a view of the CCE cell layout can be produced, which has all of the local configuration nets already in place.

The process of programming a CCE cell, from the abstract view down to silicon layout routing, is illustrated in figures 12 to 14. With reference to figure 12, an example of configuration of a configurable C-element is depicted. Figure 12a shows the schematic symbol for a C-element with two positive asymmetric logic inputs A and B and one symmetric logic input C. In all of the following diagrams Z is the output. Figure 12b shows the connections that are made to configure the C-element of figure lib to provide the functionality shown in figure 12a. Figure 12c shows the silicon layout routing where the narrower connecting lines represent connections using the lowest level of metal routing available, corresponding to the connections depicted in figure 12b; the input nodes c and d are connected together and the input nodes e and f are connected to Vss.

With reference to figure 13, an example of configuration of a configurable C-element is depicted. Figure 13a shows the schematic symbol for a C-element with three symmetric logic inputs A, B and C and one negative asymmetric logic input D. Figure 13b shows the connections that are made to configure the C-element of figure lib to provide the functionality shown in figure 13a. Figure 13c shows the silicon layout routing where the narrower connecting lines represent connections using the lowest level of metal routing available, corresponding to the connections depicted in figure 13b; the input node a is connected to Vdd and the input nodes b and e are connected together.

With reference to figure 14, an example of configuration of a configurable C-element is depicted. Figure 14a shows the schematic symbol for a C-element with two symmetric logic inputs A and B and one negative asymmetric logic input C. Figure 14b shows the connections that are made to configure the C-element of figure lib to provide the functionality shown in figure 14a. Figure 14c shows the silicon layout routing where the narrower connecting lines represent connections using the lowest level of metal routing available, corresponding to the connections depicted in figure 14b; the input nodes a and b are connected to Vdd and the input node f is connected to Vss.

Further modifications and improvements may be added without departing from the scope of the invention herein described.

Claims

1. A configurable C-element integrated circuit comprising: • a plurality of inputs; • an output; • a C-element; and • a connecting means for electrically connecting a first input of said plurality of inputs to a node, so as to tie off said first input.

2. The configurable C-element integrated circuit of Claim 1 wherein said C-element further comprises: • a state transition means for operating on state transitions of said plurality of inputs and changing the state of said output responsive to said state transitions; and • a state holding means for holding the state of said output.

3. The configurable C-element integrated circuit of any previous claim wherein said node is a supply voltage.

4. The configurable C-element integrated circuit of Claim 3 wherein said first input is a negative asymmetric input and said supply voltage is a lower supply voltage.

5. The configurable C-element integrated circuit of Claim 4 wherein said state transition means further comprises a pull-down stack comprising a plurality of pull-down transistors each having a pull-down gate and said negative asymmetric input is a pull-down gate.

6. The configurable C-element integrated circuit of Claim 3 wherein said first input is a positive asymmetric input and said supply voltage is a higher supply voltage.

7. The configurable C-element integrated circuit of Claim 6 wherein said state transition- means further comprises a pull-up stack comprising a plurality of pull-up transistors, each having a pull-up gate and said positive asymmetric input is a pull-up gate.

8. The configurable C-element integrated circuit of Claims 1 to 2 wherein said node is a second input of said plurality of inputs.

9. The configurable C-element integrated circuit of Claim 8 wherein said first and second inputs are one each of a negative asymmetric input and a positive asymmetric input.

10. The configurable C-element integrated circuit of Claim 8 wherein said first and second inputs are both symmetric inputs.

11. The configurable C-element integrated circuit of Claim 8 wherein said first and second inputs are one each of an asymmetric input and a symmetric input.

12. The configurable C-element integrated circuit of any previous claim wherein said state holding means is optimised to hold the state of said output responsive to said state transitions of all of said plurality of inputs.

13. A method for designing a C-element integrated circuit comprising the steps: • providing a C-element with a plurality of inputs; and • selectively reducing the number of said plurality of inputs by electrically connecting a first input of said plurality of inputs to a node, so as to tie off said first input.

14. The method of Claim 13 wherein said node is a supply voltage.

15. The method of Claim 14 wherein said first input is in a negative asymmetric input and said supply voltage is a lower supply voltage.

16. The method of Claim 14 wherein said first input is an asymmetric positive input and said supply voltage is a higher supply voltage.

17. The method of Claim 13 wherein said node is a second input of said plurality of inputs.

18. The method of Claim 17 wherein said first and second inputs are one each of a negative asymmetric input and a positive asymmetric input.

19. The method of Claim 17 wherein said first and second inputs are both symmetric inputs.

20. The method of Claim 17 wherein said first and second inputs are one each of an asymmetric input and a symmetric input.

21. A circuit for logic reduction in asynchronous circuits comprising: • a plurality of inputs; • an output; • a net means for providing a logic operation, said net means comprising wired logic; and • a switchable load means for providing a load for said net means, said switchable load comprising an enable input, said switchable load being switchable between a load state and a high-impedance state responsive to said enable input.

22. The circuit of Claim 21 wherein said wired logic comprises open-drain logic comprising n-type transistors.

23. The circuit of Claim 21 wherein said wired logic comprises open-source logic comprising p-type transistors.

24. The circuit of any of Claims 21 to 23 wherein said wired logic comprises transistors connected with their channels in series so as to provide AND functionality.

25. The circuit of any of Claims 21 to 23 wherein said wired logic comprises transistors connected with their channels in parallel so as to provide NOR functionality.

26. The circuit of any of Claims 21 to 25 wherein said switchable load means comprises a plurality of transistors connected with their channels in series and with a common gate.

27. A circuit for completion detection in asynchronous circuits comprising: • first and second circuits for logic reduction in accordance with Claims 21 to 26; and • an output latch means for combining and latching the output of said first and second circuits for logic reduction, said output latch means comprising a completion output.

28. The circuit of Claim 27 wherein said first circuit for logic reduction comprises wired logic providing AND functionality and said second circuit for logic reduction comprises wired logic providing NOR functionality.

29. The circuit of any of Claims 27 to 28 wherein said switchable load means is switchable responsive to the input and output states of the asynchronous module that said circuit for completion detection is detecting the completion of.

30. The circuit of any of Claims 27 to 29 wherein said switchable load means is switchable responsive to said completion output.

31. The circuit of any of Claims 27 to 30 wherein said switchable load means is switchable responsive to said completion output and the completion output of an upstream asynchronous logic module.

32. The circuit of any of Claims 27 to 31 wherein said switchable load means is switchable responsive to an exclusive OR of said completion output and the completion output of an upstream asynchronous logic module.

33. The circuit of any of Claims 27 to 32 wherein said output latch means comprises said configurable C- element integrated circuit according to any of Claims 1 to 12.