WO2006003288A1 - Procede de decodage iteratif de codes blocs et dispositif decodeur correspondant - Google Patents
Procede de decodage iteratif de codes blocs et dispositif decodeur correspondant Download PDFInfo
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- WO2006003288A1 WO2006003288A1 PCT/FR2005/001377 FR2005001377W WO2006003288A1 WO 2006003288 A1 WO2006003288 A1 WO 2006003288A1 FR 2005001377 W FR2005001377 W FR 2005001377W WO 2006003288 A1 WO2006003288 A1 WO 2006003288A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
- H03M13/2909—Product codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/3784—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 for soft-output decoding of block codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/45—Soft decoding, i.e. using symbol reliability information
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/45—Soft decoding, i.e. using symbol reliability information
- H03M13/451—Soft decoding, i.e. using symbol reliability information using a set of candidate code words, e.g. ordered statistics decoding [OSD]
- H03M13/453—Soft decoding, i.e. using symbol reliability information using a set of candidate code words, e.g. ordered statistics decoding [OSD] wherein the candidate code words are obtained by an algebraic decoder, e.g. Chase decoding
Definitions
- Iterative decoding method of block codes and corresponding decoder device The coding-decoding methods of the digital signals have been introduced in order to ensure an efficient transmission of the digital data conveyed by the latter. In principle, they consist in adding to a significant bit, the medium of the information conveyed by the aforementioned digital signals, a redundancy of known bits, in order to allow after transmission of the set, and introduction of errors inherent in the transmission process. , decoding and reconstruction of the signifying bits with a good probability of likelihood.
- block codes including product codes
- T q T q representing all combinations of binary values in the least reliable p positions and zero value for the other positions;
- Z q Y ⁇ T q where the sign ⁇ designates the exclusive OR operation on the components of the vectors;
- C po - Cn J ⁇ t
- the above-mentioned competing words are found through Chase's algorithm. In the case where one of the words does not exist, the reliability is fixed by a constant predetermined value ⁇ , whose sign is given by Chase's decision. The fact of increasing p increases the probability of finding, for a bit of rank j, the competing word at D.
- the processing of the information to execute the turbo decoding from a SISO decoder is then the following: for a received product code word [R], the decoded product code word generated by the previous iteration [R (m)] and the decoded product code word [R (m)] generated by the iteration current output from the SISO decoder, the input word [W (m + 1)] of the decoding turbo T for the next iteration satisfies the relation:
- W (m) designates the extrinsic information, normalized to 1 at each iteration and ⁇ (m) denotes a coefficient which depends on the current iteration, of rank m.
- This decoding process is close to the optimal in that the information that flows from one decoding iteration to the next contains only the information provided by this iteration, because of the subtraction operation carried out. extrinsic information being transmitted alone.
- step a) The implementation mode according to the process described by R. Pyndiah requires the effective storage of 2 P n-bit words in step a) for each decoded row or column.
- steps c) and d) each requires the conduct of a loop calculation to discriminate the decision code word, which lasts respectively for the competitor word at a minimum distance, against the received product code word R.
- the present invention aims to overcome the disadvantages of the method of the prior art described above.
- an object of the present invention is to substantially eliminate the operation of storing the code words produced by the implementation of the iterative process, according to the Fast Chase algorithm for example, in particular to enable the implementation of decoding devices in devices of much reduced computing capacity, not exceeding, for example, that of mobile computers, mobile telephony terminals or PDA-type PDAs, or in systems digital data storage.
- Another object of the present invention is, finally, because of the introduction of the aforementioned simplification, the implementation of a method and a device for iterative decoding of block codes in which the iterative process is reduced to a single loop, the loop processes of steps c) and d) of the method of the prior art being substantially eliminated, which allows to obtain a significant reduction in the calculation time to perform the decoding, to increase the number of words of test code for decoding, or to increase the length of the processed code.
- the method of iterative decoding of block codes by SISO decoding of a product code word received from decoded test words, object of the present invention, is remarkable in that it consists at least in generating by means of a iterative process a plurality of decoded test words, calculating for each decoded test word the analog weight expressed as the half sum of the products of the value of each bit mapped to the value + or -1 of this decoded test word and of the probability of this value, in terms of log-likelihood, classifying and storing said analog weight values, to constitute a first analog weight vector formed by the analog weight components of the decoded test words whose bit of rank j is at a first value and a second analog weight vector formed by the analog weight components of the decoded test words whose bit of rank j is at a second value, calculating the value of sort ie soft decision of the SISO decoding, expressed as the difference of the analog weight components of the first and second analog weight vectors.
- the iterative decoding device of block codes by SISO decoding of a received product code word, from decoded test words, object of the present invention is remarkable in that it comprises at least for the treatment of each word.
- received product code a generator module, from an iterative algorithm, a plurality of decoded test words, a calculation module, for each decoded test word, the analog weight expressed as the half-sum of the products.
- a sorting module by classification, of the analog weight values for the test words decoded to constitute a first vector of analog weight formed by the analog weight components of the words of decoded test whose bit of rank j is at a first value and a second vector of analog weight formed by the analog weight components of the decoded test words whose bit of rank j is at a second value, a first and a second register for storing said analog weight values classified according to this first respectively this second analog weight vector and a module for calculating the soft decision output value of the SISO decoding, comprising at least one subtractor module of the analog weight components of the first and of the second analog weight vector.
- FIG. 2 represents, by way of illustration, a flowchart of the essential steps for implementing the iterative decoding method that is the subject of the present invention
- FIG. 3a represents, by way of illustration, a detailed flowchart of the step of classifying the analog weight values of the decoded test words represented in FIG. 2;
- FIG. 3b represents, by way of illustration, a detailed flowchart of the step of calculating the soft decision value represented in FIG. 2.
- the aforementioned fast chase iterative process or algorithm simplifies the operations of the Chase process, previously mentioned in the description, by traversing the test vectors or means of a Gray count type.
- This procedure makes it possible to simplify the expression of the syndrome calculated for each iteration, the notion of syndrome corresponding to the notion of error location after coding, taking advantage of the properties of the linear block codes.
- the calculation of the weight for each test vector is also simplified because of the simplification of the update when considering the change of a single bit.
- H denotes the i- th line of the matrix H.
- the code is a Hamming code extended by a parity bit, denoted yo. The parity bit is not taken into account in the calculation of the syndrome but checked afterwards.
- Y ⁇ y 0 y n ⁇ denotes the hard decision of the word R soft input of the SISO decoder with y, € ⁇ 0, 1 ⁇ .
- Weight hm and Weight are the analog weights of Y bm and Y 1 respectively, vector tested at each iteration and word obtained by hard decoding.
- the weight of the tested vector is updated:
- the decoded test words Y 1 are obtained from a row or a column of the received product codeword R. These operations are then applied sequentially to all the rows or all the columns following the iteration considered.
- a hard decision Y is made on the received product code word R, and the values of the bits of Y, 0 or 1 (or -1 or +1 according to the convention adopted) are therefore decided from the soft values, without decoding.
- test vectors are generated, by modifying the p bits selected as being the least reliable, on the hard decision Y mentioned above, not decoded, according to all the possible bit combinations.
- the decoded test words Y 1 are then obtained by decoding the above test vectors by hard decoding.
- the one where the least reliable p bits are not changed corresponds to the decoded test word Y 1 obtained by direct decoding of the hard decision Y.
- the following decoded test words are obtained from the hard decision Y in which the least reliable bits are modified to obtain a test vector, which is hard decoded.
- the method which is the subject of the invention consists, in particular, in generating 2 P decoded test words for the 2 P bits of the decoded received word Y resulting from hard decoding, the value of which is the least reliable.
- Step A is then followed by a step B, represented in FIG. 2, consisting in calculating for each decoded test word Y 1 the analog weight expressed as the half-sum of the products of the value of each bit mapped to the ⁇ 1 value of this decoded test word and the probability of this value in terms of log-likelihood.
- r denotes the log-likelihood value of the corresponding bit of rank i, i being a computation index corresponding in fact to the index of the bit mapped to the value +1 respectively -1 and c, denotes this value mapped for each decoded test word Y *.
- log-likelihood value can be expressed as the relation (16)
- all possible combinations of the test vectors are obtained by modifying a single bit of the test vector of the previous iteration t to obtain the vector of next test of the current iteration t + 1 to obtain the next test vector of the current iteration t + 1, and so on, from the first test vector, to obtain all the possible combinations of these bits on the selected positions.
- the bits of the test vector of the previous iteration are modified, at the rate of only one of these, according to a specific sequence starting from a Gray count, to review all possible combinations of bits.
- the order of change of the bits is contained in a vector respecting this counting mode.
- P ' P - r k c' k (17)
- P is the weight of the previous iteration test vector
- r k denotes the reliability in terms of log-likelihood of the bit of rank k modified
- c 'k the new value mapped to ⁇ 1 of the bit of rank k modified.
- the decoded test word of the current iteration is obtained by decoding by hard decoding the test vector considered of this same iteration.
- the iterative decoding method, object of the present invention consists in classifying and, of course, storing the analog weight values for the decoded test words, so as to constitute a first vector Vi of analog weight formed by the analog weight components p ⁇ ; decoded test words whose bit of rank j is mapped to a first value +1 and a second vector V2 of analog weight formed by the analog weight components p
- the ranking operation is represented symbolically in step C of FIG. 2 by the relation: Weight -W 1 (PMJ " ) or V 2 ( PM j)
- steps A, B, C represented in FIG. 2 and, in particular, the steps B and C can be integrated into the iterative process of the fast chase algorithm, this iterative process being represented by the return step.
- the index t denotes the passage of the decoded test word generated at the current iteration to the decoded test word of the next iteration for the exploitation of the 2 decoded test words.
- step D of soft decision-making that is to say of the SISO decoding, expressed as the difference of the analog weight components of the first and of the second vectors ⁇ ⁇ and V 2 of analog weight.
- step C of Fig. 2 A more detailed description of the process of ordering the analog weight values for the decoded test words, step C of Fig. 2 will now be given in connection with Fig. 3a.
- the classification process of the method that is the subject of the present invention comprises a step of initializing the first Vi and the second V 2 analog weight vector in which each analog weight component p ⁇ for the first vector Vi relating to the analog weight components of the decoded test words whose bit of rank j is at a first value and respectively p ⁇ " for the second vector V 2 of analog weight relative to the components of analog weight of the decoded test words whose bit of rank j is the second value are initialized to the value p
- the list containing the minimum weights must be understood as such because of the process implemented by the steps Ci and C 2 hereinafter called after the initialization step Co and the first iteration of the fast chase algorithm. noted C 1 in Figure 3a.
- the operation of classifying and storing the analog weight values then consists in classifying the analog weight values of the first test word obtained in the weights vectors of the minimum weights as a function of the value of the bits of the latter, the first First tested test word having the minimum weight relative to the arbitrary initialization weight values.
- the decoded test word considered is the test word Y 1 .
- step Ci The so-called launch operation performed at the end of the first iteration in step Ci is written:
- the classification process consists in classifying the current weight obtained during the current iteration of the fast Chase algorithm in the first Vi and the second V 2 vector, respectively. of minimum analog weight, if and only if the current weight Weight is less than the weight value present for the component of the same rank stored at the previous iteration or at a previous iteration.
- step D of FIG. 2 for calculating the SISO decoding output value
- step c 2 available vectors ⁇ ⁇ and V 2, lists the analog weight values of the test words decoded with the j -th bit to 1 first value and 0 second value.
- step D of FIG. 2 then consists, starting from the values P ⁇ + and p ⁇ " , for any bit of rank j belonging to 0, n, of each decoded test word if the value of the analog weight components is different from the initialization value, ie + ⁇ , the probability of the value of the corresponding rank bit j is calculated as the difference of the actual analog weight values p ⁇ ⁇ and p ⁇ +.
- the above condition can be realized by the tests D 1 and D 2 shown in FIG 3b, the difference values p ⁇ and
- the value + ⁇ can be represented by any arbitrarily large value that is not compatible with an actual value of probable analog weight.
- the difference test can then consist of an inferiority test for example.
- step D 4 The calculation of the difference of the analog weight values is represented in step D 4 .
- the value of the analog weight component p ⁇ T of the decoded test word whose bit of rank j is at a value is only different from the initialization value + ⁇ , it is assigned to the probability of the bit value of rank j a first negative determined value.
- This operation can be performed, as shown in FIG. 3b, on a negative response to the test D 1 in a step D 3 .
- the value of the analog weight component py ⁇ of the decoded test word, whose bit of rank j is at the other value the value 1 for example, is different from the initialization value, it is assigned to the probability of the value of the rank bit j a determined value opposite to the first determined value. This operation is performed on a negative response to the test D 2 in step D 5 .
- the first and second positive negative values respectively positive are the values ⁇ , weighting coefficient of turbo-decoding.
- An additional memory saving can be obtained for the purpose of implementing the product code decoding method by eliminating Y, i.e., the decoded test word after hard decoding forming the decoded test word of the setting. implementation of the algorithm. In this situation, only the test vector Y bm constituting the test word is used. This test word can be reassigned to its true value from the beginning of the iteration after having been subjected to a hard decoding to form the corresponding test word, so as not to change the list of test words, if one has kept the value of the erroneous bit and a variable indicating a possible parity error. This operating process also makes it possible to avoid reassigning each time the value Y 1 of the test word after hard decoding, that is to say from the decoded test word to the value of Y bm .
- parity bit of each test word can be updated each time a bit of rank j is modified, which avoids the need to sum all the bits each time to recalculate the value of parity.
- the method which is the subject of the present invention is remarkable vis-à-vis the methods of the prior art, in that it allows a considerable gain in the number of logic gates used and the actual calculation time required while retaining the same calculation result.
- First, exploiting the properties of block code syndromes as part of the Fast Chase algorithm divides the computation time of the syndrome by n. In fact, we divide by the same factor the amount of operations required to calculate the analog weight and therefore, Overall, the calculation time of the process of scanning all the test vectors by the Fast Chase algorithm is itself divided by n.
- the new method of calculating the reliability used in accordance with the subject of the present invention makes it possible to completely get rid of the storage of the decoded test words examined by the fast Chase algorithm process. iterative.
- This procedure thus eliminates the need to implement a quantity of memory corresponding to n ⁇ 2 p bits and this, for each line or column of the product code, which gives a total saving of n 2 ⁇ 2 P bits for decoding. full product code on a half-iteration.
- the amount of memory then needed to store the analog weights depends only on the length of the code and the number of bits of the quantization, and therefore does not depend in any way on the number of competing words or test words chosen.
- An iterative decoding device of block codes by decoding SISO of a received code word R consisting of n bits, from decoded test words, according to the method of the present invention, described above, will now be described in connection with FIG. 4.
- the device that is the subject of the invention is deemed, in a nonlimiting manner, integrated in a mobile telephone terminal, a digital assistant of the type
- This type of apparatus comprises, in a conventional manner, a central processing unit, CPU, formed by a microprocessor, a random access memory, RAM memory, acting as a working memory, and a permanent memory, such as a ROM memory. , non-volatile memory for example.
- the device according to the invention shown in FIG. 4 furthermore comprises a generator module based on an iterative algorithm such as the
- the aforementioned generator module may consist of a program module stored in ROM memory and called in working memory RAM for execution of the fast chase algorithm described above in connection with the table of the present description in accordance with FIG. step A) of FIG.
- the above-mentioned calculation module may consist of a program module stored in a ROM 2 memory and called in working memory for execution according to the relation indicated in step B) of FIG. 2.
- This sorting module also comprises a sorting module by classification of the analog weight values for the decoded test words Y 1 above.
- This sorting module may be constituted by a ROM 3 program module, called RAM working memory for execution in accordance with the method of the invention shown in Figures 2 and C stages 3a.
- a first Ri and a second register R 2 for storing the analog weight values classified according to the first and second vector Vi, V 2 of analog weight, relative each the analog weight components of the decoded test words.
- the aforementioned registers can be configured as a memory area protected from the RAM working memory or by an electrically reprogrammable non-volatile memory, so as to allow a reconfiguration of each register Ri, R 2 , depending on the number of decoded test words finally retained for the implementation of the decoding.
- the device comprises, as illustrated in FIG. 4, a module for calculating the SISO decoding soft decision output value comprising at least one subtractor module of the analog weight components of the first and the second second analog vector stored in the registers Ri respectively R 2 .
- This calculation module may consist of a ROM4 program module called in working memory for execution in accordance with the method that is the subject of the invention represented in FIG. 2, step D and 3b.
- the embodiment of the decoding device that is the subject of the present invention can advantageously be executed in the form of a chip, a dedicated integrated circuit.
- the method and the decoding device according to the invention find application in the implementation of systems or apparatus for storing coded data and reproducing these coded data in decoded form.
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Abstract
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2007526489A JP2008502247A (ja) | 2004-06-10 | 2005-06-06 | ブロック符号の反復復号方法及び復号デバイス |
US11/628,851 US20080046799A1 (en) | 2004-06-10 | 2005-06-06 | Method for Iteratively Decoding Block Codes and Decoding Device Therefor |
EP05775373A EP1766785A1 (fr) | 2004-06-10 | 2005-06-06 | Procede de decodage iteratif de codes blocs et dispositif decodeur correspondant |
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FR0406291 | 2004-06-10 | ||
FR0406291A FR2871631B1 (fr) | 2004-06-10 | 2004-06-10 | Procede de decodage iteractif de codes blocs et dispositif decodeur correspondant |
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US (1) | US20080046799A1 (fr) |
EP (1) | EP1766785A1 (fr) |
JP (1) | JP2008502247A (fr) |
KR (1) | KR20070058430A (fr) |
FR (1) | FR2871631B1 (fr) |
WO (1) | WO2006003288A1 (fr) |
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US7752523B1 (en) * | 2006-02-13 | 2010-07-06 | Marvell International Ltd. | Reduced-complexity decoding of parity check codes |
DE102008040797B4 (de) * | 2008-07-28 | 2010-07-08 | Secutanta Gmbh | Verfahren zum Empfangen eines Datenblocks |
US8332810B2 (en) * | 2008-11-24 | 2012-12-11 | Sap Aktiengeselleschaft | Optimal code generation for derivation tables |
DE102008055139B4 (de) | 2008-12-23 | 2010-12-09 | Secutanta Gmbh | Verfahren zum Empfangen eines Datenblocks |
KR101923701B1 (ko) * | 2011-12-14 | 2018-11-30 | 한국전자통신연구원 | 무선 통신 시스템에서의 반복적 검출 및 복호 방법 및 이의 장치 |
EP2916460B1 (fr) * | 2014-03-06 | 2017-08-23 | Samsung Electronics Co., Ltd | Décodeur à consommation de puissance ultra faible |
US9641285B2 (en) | 2014-03-06 | 2017-05-02 | Samsung Electronics Co., Ltd. | Ultra low power (ULP) decoder and decoding processing |
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JP3876662B2 (ja) * | 2001-08-03 | 2007-02-07 | 三菱電機株式会社 | 積符号の復号方法および積符号の復号装置 |
JP2003283341A (ja) * | 2002-03-22 | 2003-10-03 | Sony Corp | 線形ブロック符号に従って符号化されたデータを訂正するための装置 |
US7058873B2 (en) * | 2002-11-07 | 2006-06-06 | Carnegie Mellon University | Encoding method using a low density parity check code with a column weight of two |
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2004
- 2004-06-10 FR FR0406291A patent/FR2871631B1/fr not_active Expired - Fee Related
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2005
- 2005-06-06 KR KR1020077000620A patent/KR20070058430A/ko not_active Application Discontinuation
- 2005-06-06 WO PCT/FR2005/001377 patent/WO2006003288A1/fr active Application Filing
- 2005-06-06 EP EP05775373A patent/EP1766785A1/fr not_active Withdrawn
- 2005-06-06 US US11/628,851 patent/US20080046799A1/en not_active Abandoned
- 2005-06-06 JP JP2007526489A patent/JP2008502247A/ja active Pending
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EP0654910A1 (fr) * | 1993-11-19 | 1995-05-24 | France Telecom | Procédé pour détecter des bits d'information traités par des codes en blocs concaténés |
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Also Published As
Publication number | Publication date |
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FR2871631B1 (fr) | 2006-09-22 |
JP2008502247A (ja) | 2008-01-24 |
US20080046799A1 (en) | 2008-02-21 |
KR20070058430A (ko) | 2007-06-08 |
FR2871631A1 (fr) | 2005-12-16 |
EP1766785A1 (fr) | 2007-03-28 |
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