WO2005124872A1 - Nanowire semiconductor device - Google Patents
Nanowire semiconductor device Download PDFInfo
- Publication number
- WO2005124872A1 WO2005124872A1 PCT/IB2005/051843 IB2005051843W WO2005124872A1 WO 2005124872 A1 WO2005124872 A1 WO 2005124872A1 IB 2005051843 W IB2005051843 W IB 2005051843W WO 2005124872 A1 WO2005124872 A1 WO 2005124872A1
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- WIPO (PCT)
- Prior art keywords
- nanowires
- trench
- gate
- substrate
- semiconductor device
- Prior art date
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- 239000002070 nanowire Substances 0.000 title claims abstract description 145
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 239000000463 material Substances 0.000 claims abstract description 41
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 26
- 238000000151 deposition Methods 0.000 claims description 19
- 239000003054 catalyst Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 210000000746 body region Anatomy 0.000 claims description 15
- 239000002243 precursor Substances 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000012212 insulator Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 230000015556 catabolic process Effects 0.000 claims description 7
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 5
- 239000007787 solid Substances 0.000 claims description 4
- 230000005684 electric field Effects 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 239000004411 aluminium Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 5
- 229910002601 GaN Inorganic materials 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000013459 approach Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 239000002071 nanotube Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000012552 review Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000002041 carbon nanotube Substances 0.000 description 1
- 229910021393 carbon nanotube Inorganic materials 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000001962 electrophoresis Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 229910001338 liquidmetal Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H01L29/66666—Vertical transistors
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- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
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- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
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- Y10S977/70—Nanostructure
- Y10S977/701—Integrated with dissimilar structures on a common substrate
- Y10S977/72—On an electrically conducting, semi-conducting, or semi-insulating substrate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/701—Integrated with dissimilar structures on a common substrate
- Y10S977/72—On an electrically conducting, semi-conducting, or semi-insulating substrate
- Y10S977/721—On a silicon substrate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/701—Integrated with dissimilar structures on a common substrate
- Y10S977/72—On an electrically conducting, semi-conducting, or semi-insulating substrate
- Y10S977/722—On a metal substrate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/701—Integrated with dissimilar structures on a common substrate
- Y10S977/723—On an electrically insulating substrate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/734—Fullerenes, i.e. graphene-based structures, such as nanohorns, nanococoons, nanoscrolls or fullerene-like structures, e.g. WS2 or MoS2 chalcogenide nanotubes, planar C3N4, etc.
- Y10S977/742—Carbon nanotubes, CNTs
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/762—Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/902—Specified use of nanostructure
- Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
- Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
- Y10S977/938—Field effect transistors, FETS, with nanowire- or nanotube-channel region
Definitions
- NANOW1RE SEMICONDUCTOR DEVICE The invention relates to a semiconductor device and method of manufacture, the semiconductor device including in particular at least one nanowire.
- Nanowires also known as whiskers, are very narrow wires. They may be formed in a variety of materials, including a variety of different semiconductors. An early review of methods of growing these wires and their use is provided by the applied physics review of Hiruma et al, "Growth and optical properties of nanometer-scale GaAs and InAs whiskers", in J. Appl. Phys, volume 77, number 2 (1995), pages 447 to 461. Further details of their growth are provided in Morales and Lieber, “A laser ablation method for the synthesis of crystalline semiconductor nanowires", Science, Volume 279, pages 208 to 210, (1998). Details of growing nanowire superlattices, i.e.
- VLS vapour-liquid-solid
- the metal atoms may be for example of gold.
- the paper by Gudiksen et al describes how nanowire composition may be varied during growth to provide high-quality heterostructures. It has been proposed to incorporate nanowires in a number of different types of semiconductor device.
- US2003/0132461 (Roesner et al) describes a field effect transistor using nanowires.
- This patent application proposes a method in which a nickel source layer is deposited on a substrate, followed by an aluminium oxide layer. A gate layer is deposited on the aluminium oxide, and through holes etched in the gate layer and aluminium oxide layer. Carbon nanotubes are then grown in the through holes. The gate layer is then oxidised so that the sidewalls of the through holes are insulating.
- a semiconductor device comprising: a substrate defining opposed first and second major surfaces; at least one conductive nanowire extending substantially perpendicularly to the major surfaces defining a body region and a drift region along the length of the nanowire; a gate region of conductive material insulated from the nanowires and arranged adjacent to the body region of the nanowires and spaced from the drift region end of the nanowires to control conduction in the nanowires in the body region of the nanowires.
- the invention is of use in power applications and can result in a better tradeoff between breakdown voltage and on-state resistance than can be obtained through more conventional methods.
- a gated nanowire device By forming a gated nanowire device in this way a higher breakdown voltage can be achieved.
- the region of the nanowire not adjacent to the gate acts in effect as a drift region thereby increasing the breakdown voltage of the device.
- the maximum electric field strength that can be supported by bulk silicon is not particularly high, and gallium nitride (GaN) has for example a maximum electric field strength around one order of magnitude higher than for silicon.
- GaN gallium nitride
- the use of a nanowire in the arrangement of the invention allows high breakdown strengths to be achieved.
- the nanowire may be formed of a first material in the body region adjacent to the gate and a different second material in the drift region not adjacent to the gate. In this way each region of the device can be optimised independently.
- the first material is silicon and the second material is gallium nitride.
- Other materials for the nanowire may also be used, for example carbon.
- the doping profile can be optimised independently. For instance, a doping gradient in the drift region can be realised by choosing the growth conditions accordingly.
- Any suitable conductive material may be used for the gate, for example metal such as aluminium.
- Alternative materials such as highly doped polysilicon may also be used, and indeed may be preferred.
- the invention in another aspect, relates to a substrate defining opposed first and second major surfaces; at least one conductive nanowire extending substantially perpendicularly to the major surfaces defining a first region and a second region along the length of the nanowire; wherein the nanowires are formed of a first material in the first region and a different second material in the second region not adjacent to the gate.
- the nanowires may be embedded in dielectric material, which may for example be deposited after forming the nanowires.
- the nanowires may be in at least one trench.
- a dielectric layer may be provided on the sidewalls of the at least one trench, a dielectric layer on the surface of the substrate, and a conductive gate region formed on the dielectric layer on the surface of the substrate.
- a plurality of nanowires may be provided in the or each trench.
- a single nanowire may be provided in the or each trench, and may indeed fill the trench.
- Suitable materials for the substrate include silicon and aluminium oxide.
- the latter is a known substrate for growing nanowires.
- the aluminium oxide may be a layer formed on aluminium, the underlying aluminium forming the second contact.
- the substrate can be doped silicon, especially where the substrate acts as a gate and so needs to conduct, but may also be of undoped silicon, especially where a separate gate contact is provided or the semiconductor device does not have a gate.
- the substrate is highly doped with a lower doped epilayer of the same conductivity type as the substrate formed on the substrate.
- the invention also relates to a method of manufacturing a semiconductor device according to the first aspect.
- the invention also relates to: providing a substrate defining opposed first and second major surfaces; growing at least one conductive nanowire substantially perpendicularly to the major surfaces; a gate region of conductive material insulated from the nanowires and arranged adjacent to a body region of the nanowires and spaced from a drift region end of the nanowires to control conduction in the nanowires in the body region of the nanowires.
- a semiconductor device comprising: a semiconductor substrate having opposed first and second major surfaces; at least one trench extending from the first major surface of the substrate towards the second major surface through the semiconductor substrate; a first contact at the first major surface of the substrate; and a plurality of conductive nanowires extending from the first contact to the base of the trench through the trench.
- the term "trench” is not intended to be limited to elongate forms and is specifically intended to include a contact hole in a dielectric.
- a semiconductor device comprising: a metal plate; an insulating layer on the metal plate; at least one trench extending through the insulating layer; a first contact at the top of the trench; a second contact at the base of the trench; and conductive nanowires extending from the first contact to the second contact through the trench.
- the metal plate may be aluminium and the insulating layer aluminium oxide.
- the invention in another aspect, relates to a method of manufacturing a semiconductor device having first and second contacts, comprising: providing a substrate having opposed first and second major surfaces; forming a trench extending from the first major surface towards the second major surface; forming a second contact at the base of the trench; forming insulator on the sidewalls of the trench; depositing catalyst in the base of the trench on the second contact; growing nanowires from the catalyst extending from the base of the trench to the top of the trench; and forming a first contact in contact with the nanowires at the top of the trench.
- the method may further comprise depositing insulator on top of the first major surface of the substrate; and depositing a gate layer on the insulator.
- the method may readily provide nanowires with a first material adjacent to the gate layer and a second material not adjacent to the gate layer by: supplying a precursor of the second material layer when initially growing the nanowire from the catalyst; and subsequently supplying a precursor of the first material layer. It is convenient to grow the nanowires using a VLS process.
- a method of manufacturing a semiconductor device comprising: • depositing catalyst on a substrate having a first major surface in electrical connection with a second contact; growing a plurality of nanowires; depositing dielectric around the nanowires leaving the tops of the nanowires exposed; and forming a first contact in contact with the tops of the nanowires.
- the method may include: depositing gate insulator on at least part of the exposed tops of the nanowires; depositing a gate layer on the dielectric; depositing an upper insulating layer on the gate layer, and forming the first contact to the nanowires on the upper insulating layer.
- the dielectric deposited around the nanowires may be formed from a tetraethylorthosilicate (TEOS) precursor.
- Figure 1 illustrates growth of nanowires.
- Figure 2 shows a first embodiment of the invention
- Figure 3 shows a second embodiment of the invention
- Figure 4 shows a third embodiment of the invention
- Figure 5 shows a fourth embodiment of the invention
- Figure 6 shows a fifth embodiment of the invention
- Figure 7 shows a sixth embodiment of the invention.
- Like components are given like reference numerals in the different embodiments and the description relating to each reference numeral is not always repeated with reference to each figure.
- the figures are not to scale and in particular the full substrate thickness is generally not shown.
- Figure 1 illustrates nanowire growth on a metal electrode 12.
- a metal film of catalyst is deposited by a technique such as evaporation.
- the metal may be for example nickel, cobalt, iron or gold.
- the film thickness may be in the range 0.2nm to 5nm. This deposition will deposit film both on the top surface of the device and on the base of the trench. The film at the top surface can be removed at this stage, e.g. using lift-off or Chemical- Mechanical Polishing
- An alternative approach to depositing the metal is by electrodeposition applying a cathodic potential to the electrode 12. In alternate arrangements small colloidal particles may be deposited, directly or by electrophoresis.
- the substrate is heated in a reaction chamber (not shown) which forms small metal droplets 14 of the metal catalyst on drain contact 12.
- the material of the nanowire grown depends on the precursor, and the skilled person will be familiar with suitable precursors for growing a number of types of nanowires, for example from the articles and patents referred to above.
- a suitable precursor is introduced into the reaction chamber and the precursor forms the chosen semiconductor preferentially under the catalyst 14.
- the semiconductor forms thin nanowires 16.
- the nanowires may in alternative embodiments and under suitable conditions be nanotubes. Further details of nanowire growth can be found in the articles and patents referred to above.
- a first embodiment will now be described referring to Figure 2.
- a silicon substrate 2 doped to be conductive has opposed first and second major surfaces 4, 6.
- a through trench 8 is etched to extend between the surfaces.
- Dielectric 10 is coated on the sidewalls of the trench 8 as well as on the first major surface 4. Any dielectric is then removed from the base of the trench.
- VLS vapour liquid solid
- the catalyst is heated until it form small droplets, also known as clusters, and then precursor is provided in vapour form which grows preferentially at the clusters to provide nanowires 16. Note that in this example a single nanowire is formed in each trench. Any nanowires deposited on the top surface can easily be wiped/polished off.
- a source contact 18 is provided on the first major surface to connect to the top of the nanowires and a gate contact 20 is provided to connect to the substrate.
- a drain contact 12 is deposited on the second major surface and a catalyst deposited on the drain contact in the trench to provide the device illustrated in Figure 2.
- the drain contact 12 may be deposited at this late stage because the drain metal's presence can be incompatible with the wire growth and much of the subsequent processing.
- voltage can be applied to the gate contact to control conduction between source and drain contacts.
- the gate is omitted and the nanowire is formed to be a diode. This is achieved in a like manner to that described below.
- the nanowire is formed in a trench through an epilayer, as in the subsequent embodiments.
- Figure 3 shows an alternative arrangement.
- a highly doped semiconductor substrate 2 is provided having a lower doped epilayer 3 on top.
- a trench 8 is formed in epilayer 3, dielectric 10 deposited on the sidewalls of the trench 8, catalyst is deposited at the base of the trench and a number of nanowires 16 are formed in each trench by growing them from the catalyst.
- the depth of the trench 8 is the same as the thickness of the epilayer 3, though this is not essential as long as connection can be made to both ends of the nanowire.
- substrate is often used in this specification to refer to the substrate and the epilayer.
- the nanowires 16 are diodes having one end doped n- type and one end doped p-type.
- a region 28 of the nanowire adjacent to the substrate 2 is grown using a p-type dopant in the gas mixture used to grow a p-type length 28 of nanowire. After a length of nanowire is grown, the dopant is changed to an n-type dopant and growth continued of an n-type length of nanowire 29.
- a p-n junction formed at the boundary between the lengths 28,29 of nanowire forms a diode. Therefore, the upper contact 18 is in this instance an anode contact, not a source contact, and lower contact 12 is in this instance a cathode contact, not a drain contact.
- the processing can also start with n-type and then p-type.
- the invention can also provide a Schottky diode by using a nanowire 29 of a single conductivity type and using the Schottky barrier with upper contact 18 to act as the rectifier.
- Figure 4 shows an alternative arrangement, again using a substrate 2 and epilayer 3 combination, wherein a transistor is formed not a diode.
- conductive gate 22 is deposited on the dielectric 10 on the first major surface, followed by the deposition of a layer that forms gate insulator 24 between the gate 22 and the trench 8 as well as an insulating layer 26 above the gate 22.
- the gate contact 20 is connected to gate through a via 27 in the insulating layer 26.
- Source contact 18 is formed over insulating layer 26.
- the material of the nanowire is not the same along the whole length of the nanowire.
- a drift region 28 of the nanowire adjacent to the substrate 2 is grown using GaN precursor.
- the precursor used in the VLS growth process is changed to a precursor for growing silicon and body region 29 is grown. Therefore, the body region 29 of the nanowire adjacent to the gate 22 is of silicon.
- GaN is used in the region of the nanowire that acts as a drift region to support voltage when the device is off, and silicon is used in the region controlled by the gate. In this way, the improved breakdown performance of the GaN can be used to enhance the breakdown voltage for a given specific on-resistance This is just one example.
- the nanowire is attached to the sidewalls. This may be done, for example, by applying a voltage between nanowire and substrate to electrostatically attract the nanowire to the sidewalls.
- a conductive substrate 30 is used as drain contact. Nanowires 16 are grown on the conductive substrate using the VLS process. Then, a dielectric 32 is deposited around the nanowires leaving their tops exposed. In the embodiment described a spin-on process is used. The deposited dielectric may be, for example tetraethylorthosilicate (TEOS), though other materials can be used instead if required.
- TEOS tetraethylorthosilicate
- a gate dielectric 34 is deposited around the exposed tops of the nanowires 16 and a conductive gate 22 deposited.
- Figure 6 shows a further development which essentially forms the structure of Figure 5 inside a trench as shown in Figures 1 to 4.
- the method used to manufacture the device of Figure 5 is used after forming a trench or trenches in a substrate as used to make the device of Figure 1.
- gate electrode 22 is inside the trench 8 and may be contacted for example at one or both ends of the trench.
- an aluminium plate 12 is used and an insulating aluminium oxide (Al 2 0 3 ) layer 36 grown on top of the aluminium.
- Al 2 0 3 aluminium oxide
- This combination is suitable for growing nanowires.
- the aluminium plate 12 can be used as the drain contact 12.
- a trench is formed through the aluminium oxide layer 2 and insulated. Nanowires are then grown by the VLS process followed by the formation of the gate 22 and source contact 18 as above. Other materials can be used for substrate 2 and drain contact 12 if convenient.
- the feature of a nanowire filling a narrow trench described above in the embodiment of Figure 2 in which the trench passes through the full thickness of the substrate, can just as well be implemented in an embodiment in which the trench is formed only at the top of the substrate as in the embodiments of Figures 3 and 4.
- Other combinations of features will be apparent to those skilled in the art. From reading the present disclosure, other variations and modifications will be apparent to persons skilled in the art. Such variations and modifications may involve equivalent and other features which are already known in the design, manufacture and use of semiconductor devices and nanowires and which may be used in addition to or instead of features described herein.
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Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05743256A EP1759417A1 (en) | 2004-06-15 | 2005-06-07 | Nanowire semiconductor device |
JP2007516090A JP2008503081A (en) | 2004-06-15 | 2005-06-07 | Nanowire semiconductor device |
US11/629,657 US7538337B2 (en) | 2004-06-15 | 2005-06-07 | Nanowire semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GBGB0413310.4A GB0413310D0 (en) | 2004-06-15 | 2004-06-15 | Nanowire semiconductor device |
GB0413310.4 | 2004-06-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005124872A1 true WO2005124872A1 (en) | 2005-12-29 |
Family
ID=32732518
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2005/051843 WO2005124872A1 (en) | 2004-06-15 | 2005-06-07 | Nanowire semiconductor device |
Country Status (6)
Country | Link |
---|---|
US (1) | US7538337B2 (en) |
EP (1) | EP1759417A1 (en) |
JP (1) | JP2008503081A (en) |
CN (1) | CN100557814C (en) |
GB (1) | GB0413310D0 (en) |
WO (1) | WO2005124872A1 (en) |
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WO2007086009A1 (en) * | 2006-01-25 | 2007-08-02 | Nxp B.V. | Nanowire tunneling transistor |
WO2007086008A1 (en) * | 2006-01-25 | 2007-08-02 | Nxp B.V. | Tunneling transistor with barrier |
WO2008129478A1 (en) * | 2007-04-19 | 2008-10-30 | Nxp B.V. | Nonvolatile memory cell comprising a nanowire and manufacturing method thereof |
WO2010110733A1 (en) * | 2009-03-25 | 2010-09-30 | Glo Ab | A schottky device |
EP2591506B1 (en) * | 2010-07-06 | 2018-05-30 | Commissariat à l'Énergie Atomique et aux Énergies Alternatives | Method of forming a microelectronic device having metal interconnection levels connected by programmable vias |
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US7838809B2 (en) * | 2007-02-17 | 2010-11-23 | Ludwig Lester F | Nanoelectronic differential amplifiers and related circuits having carbon nanotubes, graphene nanoribbons, or other related materials |
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JP6426102B2 (en) | 2012-11-05 | 2018-11-21 | ユニバーシティー オブ フロリダ リサーチ ファウンデーション,インコーポレイテッドUniversity Of Florida Research Foundation,Inc. | Brightness compensation in a display |
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- 2004-06-15 GB GBGB0413310.4A patent/GB0413310D0/en not_active Ceased
-
2005
- 2005-06-07 WO PCT/IB2005/051843 patent/WO2005124872A1/en not_active Application Discontinuation
- 2005-06-07 CN CN200580019435.XA patent/CN100557814C/en not_active Expired - Fee Related
- 2005-06-07 US US11/629,657 patent/US7538337B2/en active Active
- 2005-06-07 EP EP05743256A patent/EP1759417A1/en not_active Withdrawn
- 2005-06-07 JP JP2007516090A patent/JP2008503081A/en not_active Withdrawn
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WO2007086009A1 (en) * | 2006-01-25 | 2007-08-02 | Nxp B.V. | Nanowire tunneling transistor |
WO2007086008A1 (en) * | 2006-01-25 | 2007-08-02 | Nxp B.V. | Tunneling transistor with barrier |
US7791108B2 (en) | 2006-01-25 | 2010-09-07 | Nxp B.V. | Nanowire tunneling transistor |
US8134142B2 (en) | 2006-01-25 | 2012-03-13 | Nxp B.V. | Tunneling transistor with barrier |
WO2008129478A1 (en) * | 2007-04-19 | 2008-10-30 | Nxp B.V. | Nonvolatile memory cell comprising a nanowire and manufacturing method thereof |
US8546863B2 (en) | 2007-04-19 | 2013-10-01 | Nxp B.V. | Nonvolatile memory cell comprising a nanowire and manufacturing method thereof |
WO2010110733A1 (en) * | 2009-03-25 | 2010-09-30 | Glo Ab | A schottky device |
US8766395B2 (en) | 2009-03-25 | 2014-07-01 | Qunano Ab | Schottky device |
EP2591506B1 (en) * | 2010-07-06 | 2018-05-30 | Commissariat à l'Énergie Atomique et aux Énergies Alternatives | Method of forming a microelectronic device having metal interconnection levels connected by programmable vias |
Also Published As
Publication number | Publication date |
---|---|
JP2008503081A (en) | 2008-01-31 |
US7538337B2 (en) | 2009-05-26 |
EP1759417A1 (en) | 2007-03-07 |
CN1977385A (en) | 2007-06-06 |
CN100557814C (en) | 2009-11-04 |
US20080029909A1 (en) | 2008-02-07 |
GB0413310D0 (en) | 2004-07-14 |
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