WO2005104233A1

WO2005104233A1 - Integrated circuit layout for virtual power supply

Info

Publication number: WO2005104233A1
Application number: PCT/IB2005/051268
Authority: WO
Inventors: Jose D. J. Pineda De Gyvez; Francesco Pessolano; Kiran B. R. Rao; Rinze I. M. P. Meijer; Josep Rius Vazquez
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2004-04-27
Filing date: 2005-04-19
Publication date: 2005-11-03
Also published as: JP2007535161A; TW200605308A; EP1743374A1; CN1950941A

Abstract

A header transistor (3) and footer transistor (5) provide a virtual power supply for a core (1) on an integrated circuit. The header transistor (3) and/or footer transistor (5) are partitioned into a number of smaller transistors. For example, the header transistor (3) is partitioned into a first segment 3a and a second segment 3b, while the footer transistor (5) is partitioned into a first segment 5a and a second segment 5b. The combined width of each segment 3a/3b and 5a/5b will be the same as a single header/footer transistor (3, 5) of the prior art. However, the individual widths of each segment 3a, 3b, 5a and 5b will be smaller, thereby improving the layout of the header/footer transistors (3, 5) in the integrated circuit design. The header transistor( 3) and the footer transistor (5) are uniformly arranged around the core (1). This has the advantage of enabling the power to be uniformly distributed to the core, thereby avoiding localized temperature rises.

Description

INTEGRATED CIRCUIT LAYOUT FOR VIRTUAL POWER SUPPLY

The invention relates to the layout of a transistor circuit for an integrated circuit, and in particular, to the layout of header and/or footer transistors in an integrated circuit.

Header and footer transistors are commonly used in integrated circuits. For example, header and footer transistors are used on an integrated circuit for reducing leakage, power supply adjustment and active power supply noise suppression. Header and footer transistors are also used to partition an integrated circuit into a number of separate regions, each region having a power supply that is individually controlled by its respective header and footer transistors, i.e. islands of voltage. Fig. 1 shows a conventional circuit schematic for header and footer transistors in a core of an integrated circuit. The power supply rails VDD and NSS of the integrated circuit are connected to the core 1 via a header transistor 3 and a footer transistor 5. The header transistor 3 and footer transistor 5 allow a virtual power supply to be created for the core 1, i.e. NDD' and VSS' as shown in Fig. 1. It will be appreciated that the header transistor 3 and footer transistor 5 must be very wide to enable them to handle the large peak currents generated by the core 1 during maximum activity. For instance, in 0.13μm CMOS technology, a core of 1.3mm² with 8000 flip-flops and 50000 logic gates requires a transistor with a W/L ratio equal to 1234μm/0.13μm to guarantee that the voltage drop in the power supply stays below 5% at maximum activity. As a consequence of this requirement, the header transistor 3 and footer transistor 5 are bulky, and can therefore be a burden during the layout of an integrated circuit. Furthermore, if the header transistor 3 and the footer transistor 5 are not laid out properly, they can give rise to current crowding problems, as well as local and abnormal temperature increases. Therefore, the aim of the present invention is to provide a header and/or footer transistor arrangement that is easier to layout, and that does not create current crowding problems or localized temperature increases. According to a first aspect of the invention, there is provided a transistor circuit for connection in a power supply rail between a main power supply and a virtual power supply on an integrated circuit. The virtual power supply powers a region of the integrated circuit. The transistor circuit is partitioned into two or more segments, each segment comprising at least one transistor. The transistor circuit is configured such that the two or more segments are uniformly arranged around the region being powered. The segmentation and uniform distribution of the transistor circuit improves the layout of the transistor circuit, and has the advantage of enabling power to be uniformly distributed to the region, thereby avoiding localized temperature rises. Preferably, the transistor circuit comprises a first segment comprising at least one transistor, and a second segment comprising at least one transistor, wherein the first and second segments are arranged on a first pair of opposite sides of the region being powered. Optionally, the transistor circuit may further comprise a third segment comprising at least one transistor, and a fourth segment comprising at least one transistor, wherein the third and fourth segments are arranged on a second pair of opposite sides of the region being powered. The arrangements described above have the advantage of providing uniform distribution of power. According to one embodiment, the transistor in each segment has a common gate control signal. This enables the transistors to be switched together. Alternatively, in accordance with another embodiment the transistor in each segment has a separate gate control signal. This enables each transistor to be controlled separately, for example in response to peak current demand by the region being powered. Preferably, one or more segment is further partitioned into a plurality of sub- segments, each sub-segment comprising a transistor. This has the advantage of providing a more even distribution, and a more refined power control. According to another aspect of the invention, there is provided a method of laying out a transistor circuit on an integrated circuit, the transistor circuit connected in a power supply rail between a main power supply and a virtual power supply on an integrated circuit, the virtual power supply powering a region of the integrated circuit. The method comprises the steps of partitioning the transistor circuit into two or more segments, each segment comprising at least one transistor. The method also comprises the step of configuring the transistor circuit such that the two or more segments are uniformly arranged around the region being powered.

For a better understanding of the present invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example, to the following drawings in which: Fig. 1 shows a conventional header/footer layout for a core in an integrated circuit; Fig. 2 shows a header/footer layout according to a first embodiment of the present invention; Fig. 3 shows a header/footer layout according to a second embodiment of the present invention; Fig. 4 shows a header/footer layout according to a third embodiment of the present invention; Fig. 5 shows further details of a header segment of Figs. 2 to 4 according to another aspect of the present invention; Fig. 6 shows another layout arrangement according to the invention; Fig. 7 shows another layout arrangement according to the invention; Fig. 8 shows a power grid distribution for the header/footer arrangement of the present invention; Fig. 9 shows a more detailed layout example of one transistor footer segment; and Fig. 10 shows an example of complex cores making use of the proposed header and footer transistor layout of the present invention.

Fig. 2 shows a layout of a header transistor 3 and footer transistor 5 for a core 1. According to the invention, the header transistor 3 and footer transistor 5 are partitioned into a number of smaller transistors. For example, as shown in Fig. 2, the header transistor 3 is partitioned into a first segment 3a and a second segment 3b. As a result, the combined width of each segment 3a, 3b is the same as the width of the single header transistor 3 of Fig. 1. However, the individual width of each segment 3 a and 3b will be smaller, thereby improving the layout of the header transistor 3 in the integrated circuit design. Likewise, the footer transistor 5 is partitioned into a first segment 5a and a second segment 5b. The combined width of each segment 5a, 5b will be the same as the single footer transistor 5 of Fig. 1, but the individual width of each segment 5a and 5b will be smaller, thereby improving the layout of the footer transistor 5 in the integrated circuit design. The header transistor 3 and the footer transistor 5 are uniformly arranged around the core 1. This has the advantage of enabling the power to be uniformly distributed to the core, thereby avoiding localized temperature rises. According to the preferred embodiment, the partitioned header transistor 3 is arranged such that the first and second segments 3 a, 3b are positioned on a first pair of opposite sides of the core 1. In a similar manner, the footer transistor 5 is partitioned such that the first and second segments 5a, 5b are located on a second pair of opposite sides of the core 1. According to another embodiment, as shown in Fig. 3, rather than arranging the header transistor on a first pair of opposite sides and the footer transistor on a second pair of opposite sides, the header and footer transistors are arranged such that the header and footer transistors are on the same pair of opposite sides of the core 1. Fig. 4 shows a further embodiment, in which the header transistor 3 is partitioned into four separate segments 3a, 3b, 3c and 3d. The segments are arranged such that they are uniformly distributed over all four sides of the core 1. In a similar manner, the footer transistor 5 is partitioned into four separate segments 5a, 5b, 5c and 5d, that are uniformly distributed over all four sides of the core 1. From the above it can be seen that a header transistor 3 is partitioned into a number of segments such that the total width of the header transistor is computed as:

1=7. W -- Σ W; .=1

where N is the number of segments and w,- is the width of an individual segment transistor. It is noted that, in the embodiments of Figs. 2, 3 and 4, each transistor in each segment of the header transistor may be connected to a common gate control signal, while each transistor in each segment of the footer transistor may also be connected to a common gate control. Alternatively, each transistor in each segment of the header transistor 3 can be supplied with its own gate control signal, while each transistor in each segment of the footer transistor may also be supplied with a separate gate control signal. The latter has the advantage of allowing the power supply to the core to be controlled more finely or accurately. The gate control signal or signals may be received from a power management unit (PMU). It will be appreciated that a number of cores on an integrated circuit may have their own header/footer transistor arrangements, and that different cores may have the same, or different, arrangements for controlling the gate control signals in the respective header/footer transistor arrangements: The transistors in the segments 3_a to 3 can be configured to have the same width Wi. Alternatively, the transistors can be configured to have different widths w,-. Fig. 5 shows a further aspect of the invention, wherein one or more of the segments 3a, 3b, 3c, 3d, 5a, 5b, 5c, 5d is further partitioned into a number of smaller transistors, hereinafter referred to as "sub-segments". The Figure shows how segment 3a of the header transistor is partitioned into a number of sub-segments 3aι to 3a_x. The total width Wi of the transistor segment is computed as.

;s=X W = ∑ w,„ _.=!

where X is the number of sub-segments and w_is is the width of an individual sub-segment transistor. As described above for the separate segments, there are several variants possible for controlling the transistors 3aι to 3aχ in the sub-segments. In one embodiment, each transistor of each sub-segment 3aι to 3aχ has a common gate control, such that all sub- segments 3aι to 3aχ are switched together. Alternatively, each transistor of each sub-segment 3aι to 3a_x has a separate gate control signal, thereby allowing the sub-segments to be controlled separately, for example in response to peak current demand by the core 1. The individual transistors 3aι to 3aχ in each sub-segment can be configured to have the same width w_«. Alternatively, the transistors can be configured to have different widths Wi_S. The invention described above provides a header and/or footer transistor arrangement that is easier to layout in the integrated circuit. In addition, by further partitioning the transistors into smaller parts, the invention allows the power supply to a region or core to be controlled more uniformly and accurately. The partitioning of the header and/or footer transistors also prevents localized temperature increases. Fig. 6 shows a more detailed layout arrangement, in which the header and footer transistors are connected directly to a standard cell row. The layout comprises a first power ring 63 for NDD and a second power ring 65 for NSS. The header transistor 3 is uniformly distributed around the core and comprises a first segment 3a and a second segment 3b arranged on opposite sides of the core. The first segment 3a comprises a plurality of sub- segments 3aι to 3a , while the second segment 3b comprises a plurality of sub-segments 3bι to 3b₄. Each sub-segment comprises a transistor, such that a pair of transistors is connected to a respective standard cell row 67. Likewise, the footer transistor 5 is uniformly distributed around the core, and comprises a first segment 5 a and a second segment 5b arranged on the same pair of opposite sides of the core. The first segment 5a comprises a plurality of sub-segments 5aι to 5a₄, while the second segment 5b comprises a plurality of sub-segments 5bι to 5b₄. Again, each sub- segment comprises a transistor, such that a pair of transistors is connected to a respective standard cell row 67. In the arrangement shown in Fig. 6, the gate of each transistor is permanently connected to NDD or NSS, such that there is no programmability. This arrangement is useful for static voltage islands. The width of the basic header/footer transistor is inversely proportional to 2M (two transistors per row), where M is the number of standard cell rows. The main advantage of this embodiment is that the voltage for each standard cell row can be determined by changing the transistor width. Fig. 7 shows a detailed layout of another arrangement in which the header and footer transistors are connected directly to a standard cell row. As shown above in Fig. 6, the layout comprises a first power ring 63 for NDD and a second power ring 65 for NSS. The header transistor 3 is uniformly distributed around the core, and comprises a first segment 3 a and a second segment 3b arranged on opposite sides of the core. The first segment 3a comprises a plurality of sub-segments 3aι to 3a₄, while the second segment 3b comprises a plurality of sub-segments 3bι to 3b₄. Each sub-segment comprises a transistor, such that a pair of transistors is connected to a respective standard cell row 67. Likewise, the footer transistor 5 is uniformly distributed around the core, and comprises a first segment 5a and a second segment 5b arranged on the same pair of opposite sides of the core. The first segment 5a comprises a plurality of sub-segments 5aι to 5-U, while the second segment 5b comprises a plurality of sub-segments 5bι to 5b₄. Again, each sub- segment comprises a transistor, such that a pair of transistors is connected to a respective standard cell row 67. However, in the arrangement shown in Fig. 7, the transistor gates are controlled per standard cell row. In other words, the gates of the transistors in segments 3aι and 3bι will have gate control signals (not shown in the Figure for clarity). Likewise, the transistors in sub-segments 5aι and 5bι will have gate control signals, but separate to the gate control signals for the transistors in segments 3aι and 3bι. This layout is particularly useful when some kind of debugging is desired. For example, one can disable all rows except one to test if a defect is present in that row or not. The presence of a defect can be tested using some kind of current measurements, i.e. when there is no defect the quiescent current is almost zero, while the quiescent current is different from zero when a defect is present. As with Fig. 6, the width of the basic header/footer transistor in Fig. 7 is inversely proportional to 2M (two transistors per row), where M is the number of standard cell rows. Naturally, it is also possible to put more than one transistor in parallel (having independently steered gates) for each row. This has the advantage that the voltage per row can be programmed in multiple steps instead of being switched on and off. Fig. 8 shows how a power grid (ring style) appears with the header and footer transistors according to the present invention, for example as described above in Fig. 2. The header transistor 3 is partitioned into first and second segments 3a, 3b located on a first pair of opposite sides of the core 1, while the footer transistor 5 is partitioned into first and second segments 5a, 5b located on a second pair of opposite sides. The power grid is shown as being in a first metal layer, 81, and a second metal layer, 83. In an exemplary implementation, the first metal layer 81 can be the "metal layer 2" of the integrated circuit, while the second metal layer 83 is the "metal layer 3" of the integrated circuit. However, it is noted that the power rings can also be in the same metal layer, or more than two metal layers. The choice is based on a particular implementation. The only requirement is that the outer power rings should be connected to the core or the power switches, which means that a metal layer is required for making these connections possible. Fig. 9 provides a more detailed layout of a one-transistor segment having a NSS node 90, a bulk node 91, and a Nirtual-NSS node 92. A first metal layer 93 (Metal-1) is routed on top of a poly gate 94 to decrease the gate series resistance. Both the metal 1 line 93 and the poly gate 94 are connected via a poly contact 96. The layout shows a unit-segment MOSFET connected between two wide power-carrying lines (virtual-NSS 92 and actual-NSS 90). The gate of the transistor is connected to a third metal layer for individual access. The layout presented in this Figure is a possible implementation. A person skilled in the art could easily modify the layout without falling outside the scope of the claims. Fig. 10 shows an example of complex cores making use of the proposed header and footer transistors, wherein five cores are shown wrapped around with a header and/or footer transistor 101. The invention described above enables individual voltage islands to be created in the integrated circuit, whereby a core can be controlled by an individual virtual power supply. The invention is also applicable to provide dynamic voltage scaling (DVS). In addition, the invention has the advantage of providing easier connection to power supply pads/grids, and connection to power supply pads/grids throughout the integrated circuit. The template is also suited for use with regular design approaches. While the invention has been described with a partitioned header transistor and a partitioned footer transistor, it is noted that the partitioning could be applied to just one of the header or footer transistors. Also, the transistor arrangement for the header and footer circuits can be different from one another. For example, the header transistor could be arranged to have segments on all four sides of the core, while the footer transistor has segments on only two sides of the core. It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word 'comprising' does not exclude the presence of elements or steps other than those listed in a claim.

Claims

CLAIMS:

1. A transistor circuit for connection in a power supply rail between a main power supply and a virtual power supply on an integrated circuit, the virtual power supply powering a region (1) of the integrated circuit, wherein the transistor circuit (3; 5) is partitioned into two or more segments (3 a - 3n; 5a -5n), each segment (3a - 3n; 5a -5n) comprising at least one transistor (3n_x; 5n_x); and wherein the transistor circuit (3; 5) is configured such that the two or more segments (3a - 3n; 5a -5n) are uniformly arranged around the region (1) being powered.

2. A transistor circuit as claimed in claim 1, wherein the transistor circuit comprises: a first segment (3a; 5a) comprising at least one transistor; a second segment (3b; 5b) comprising at least one transistor; wherein the first and second segments (3a, 3b; 5a, 5b) are arranged on a first pair of opposite sides of the region (1) being powered.

3. A transistor circuit as claimed in claim 2, wherein the transistor circuit further comprises: a third segment (3c; 5c) comprising at least one transistor; a fourth segment (3d; 5d) comprising at least one transistor; wherein the third and fourth segments (3c, 3d; 5c, 5d) are arranged on a second pair of opposite sides of the region being powered.

4. A transistor circuit as claimed in claim 1, wherein the transistor in each segment has a common gate control signal.

5. A transistor circuit as claimed in claim 1, wherein the transistor in each segment has a separate gate control signal.

6. A transistor circuit as claimed in claim 1, wherein one or more segment is further partitioned into a plurality of sub-segments (3nι - 3n_x; 5nι - 5n_x), each sub-segment comprising a transistor.

7. A transistor circuit as claimed in claim 6, wherein the transistor in each sub- segment (3nι - 3n_x; 5nι - 5n_x) has a common gate control signal.

8. A transistor circuit as claimed in claim 6, wherein the transistor in each sub- segment (3nι - 3n_x; 5nι - 5n_x) has a separate gate control signal.

9. A transistor circuit as claimed in claim 6, wherein a pair of sub-segments (3nι - 3n_x; 5nι - 5n_x) is connected to a standard cell row (67).

10. A transistor circuit as claimed in claim 9, wherein different pairs of sub- segments (3nι — 3n_x; 5nι - 5n_x) connected to different standard cell rows (67) are each controlled by a separate common gate control signal.

11. A transistor circuit as claimed in claim 1, wherein each transistor is configured to have the same width.

12. A transistor circuit as claimed in claim 1, wherein two or more of the transistors are configured to have different widths.

13. A transistor circuit as claimed in claim 1, wherein a first set of transistors form a header transistor (3) for controlling the NDD power rail in the power supply, and a second set of transistors form a footer transistor (5) for controlling the NSS power rail in the power supply.

14. A transistor circuit as claimed in claim 13, wherein more than one transistor is provided in parallel for each standard cell row (67).

15. A method of laying out a transistor circuit on an integrated circuit, the transistor circuit being connected in a power supply rail between a main power supply and a virtual power supply on an integrated circuit, the virtual power supply powering a region (1) of the integrated circuit, the method comprising the steps of: partitioning the transistor circuit (3; 5) into two or more segments (3a - 3n; 5a -5n), each segment (3a - 3n; 5a -5n) comprising at least one transistor; and configuring the transistor circuit (3; 5) such that the two or more segments (3a - 3n; 5a -5n) are uniformly arranged around the region being powered.