WO2005104122A1

WO2005104122A1 - Multimedia processor system and related method

Info

Publication number: WO2005104122A1
Application number: PCT/IB2005/051263
Authority: WO
Inventors: Peter Kollig
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2004-04-20
Filing date: 2005-04-19
Publication date: 2005-11-03
Also published as: GB0408725D0

Abstract

The present invention provides for a multimedia processor system (36) arranged for receiving digital data and comprising first (38) and second (42) circuit devices having memory requirements and comprising front-end and back-end IC devices with the system, wherein memory subsystems of the first and second circuit devices are connected such that a processor of the said first circuit device can access code and variable storage in the memory subsystem (50) of the said second circuit device (42).

Description

DESCRIPTION

MULTIMEDIA PROCESSOR SYSTEM AND RELATED METHOD The present invention relates to a multimedia processor system, and related method, and in particular, but not exclusively, to such a system and related method for use within a DVD+RW system.

In currently known streaming media systems there is typically provided a pair of integrated circuit devices which comprise, for example in DVD+RW systems a so-called front-end IC processor and a so-called back-end IC codec. Memory elements are attached to each of these two programmable devices forming the front-end and back-end ICs and which, within known DVD+RW systems, comprise relative SDRAM and flash memory elements attached to each of the programmable devices. A particular disadvantage of such an arrangement is the cost that arises in view of the provision of a separate SDRAM and flash memory for each device, and also limitations that can arise through the board space occupied by such elements.

The present invention seeks to provide for a multimedia processor system, and related method, and which exhibits advantages over known such systems and method. According to one aspect of the present invention there is provided a multimedia processor system arranged for receiving digital data and comprising first and second circuit devices having memory requirements, the system including means for partitioning IP blocks in the digital data such that a buffer associated with the handling of digital data in the said first circuit device is located in the said second circuit device. According to another aspect of the present invention there is provided a multimedia processor system arranged for receiving digital data and comprising first and second circuit devices having memory requirements, wherein memory subsystems of the first and second circuit devices are connected such that a processor of the said first circuit device can access code and variable storage in the memory subsystem of the said second circuit device. The invention proves particularly advantageous and efficient in effectively allowing for the sharing of memory elements across the two devices and thereby eliminating the current need to duplicate such elements. The invention can therefore advantageously significantly lower the cost of providing multimedia processor systems and, in particular, those comprising streaming media systems through the reduction in the total number of memory element devices required. As noted, the multimedia processor system can advantageously comprise part of a streaming media system and the first and second circuit devices can advantageously comprise a front-end IC and a back-end IC respectively. The said first circuit device can then comprise a DVD engine and the said second device can advantageously comprise a codec. Such a DVD engine and codec can advantageously form part of a DVD recordable system, a DVD+RW system, or of course a mere DVD play back system. In one particular embodiment, the said means for partitioning the said IP blocks can comprise an interface between the said first and second circuit devices and, further, the means for achieving the connection between the memory subsystems on the first and second circuit devices can likewise comprise an interface device. Within the present invention, the concept of effectively sharing memories between two independent devices is advantageously achieved by means of a novel partitioning of IP blocks present within the digital media stream onto those two devices and in such a manner that the IP handling is moved from the first said device to the second said device. This effectively achieves IP repartitioning of the data parts from the optical pickup into the codec. As noted, the buffer then associated with the handling of the media stream in the front end device is effectively moved to the back-end device and the inclusion of this feature generally requires that the interface between the said first and second device can be changed from the standard AT Attachment Packet Interface (ATAPI) interface to a replacement interface of equal pin count and speed requirements. Also, the said connection between the memory subsystems of the first and second devices is arranged to provide for an efficient link such that, for example, the CPU of the front-end device is able to access code and variable storage in the memory subsystem of the back-end device. Again, the channel provided for such connection is designed specifically so as to reduce pin count and latency. Through adoption of the invention, it will be appreciated that it is possible to provide for a buffer-less DVD+RW engine since the data buffer attached to the back-end device is effectively shared with the front-end device. Thus, in this manner, the front₇end device does not require its own SDRAM. Yet further, a ROM-less DVD+RW engine can likewise be provided and in which program storage, as well as available storage space is effectively shared between the front-end and back-end devices. In this manner, and without requirement from the local storage within the DVD engine, the only flash that is required is that associated with the back-end device. According to yet another aspect of the present invention there is provided a method of processing multimedia digital data within first and second circuit devices, the method including the step of partitioning IP blocks in the digital data such that a buffer associated within the handling of digital data in the said first circuit device is located in the said second circuit device. According to yet a further aspect of the present invention there is provided a method of processing multimedia digital data within first and second circuit devices, and including the step of accessing code and variable storage in a memory subsystem of the said second circuit device by way of a processor in the said first circuit device through a connection between the said first and second circuit devices. As will be appreciated, the method is particularly advantageously used when processing streaming media within, for example, a DVD+RW processing method.

The invention is described further hereinafter, by way of example only, with reference to the accompanying drawings in which: Fig. 1 is a schematic block diagram of a streaming media system as currently known; and Fig. 2 is a schematic block diagram of a streaming media system according to one embodiment of the present invention. Turning first to Fig. 1 , there is illustrated, in block diagrammatic form, a streaming media system 10 as currently known and comprising a DVD+RW engine 12 including an optical pick-up unit (not shown) for retrieving data from, or delivering data to, an optical disk 14. Within the DVD+RW engine 12 there is provided a buffer manager 16 and a Reduced Instruction Set Computer (RISC) processor 18. The buffer manager 16 of the DVD+RW engine 12 is associated with a SDRAM element 20, and the control processor 18 is associated, by means of a memory interface unit, with an element of flash memory 22. An Integrated Drive Electronics (IDE) connection 24 provides for connection of the DVD+RW engine 12 to an MPEG codec 26. The MPEG codec 26 includes a memory subsystem 28 and a RISC control processor 30. The memory subsystem 28 is associated with a SDRAM element 32, whereas the control processor 30 is associated with an element of flash memory 34. Such a configuration is an example of the standard configuration for streaming media systems in which the DVD+RW engine 12 comprises a so- called front-end IC and the MPEG codec 26 comprises a so-called back-end IC. As will be appreciated, each of the front-end and back-end ICs 12, 26 are associated with a respective pair of memory elements, 20, 22; 32,34 which in the illustrated example comprise duplicated memory elements, and which lead to limitations arising in view of the board space required to provide such duplicated elements and increased cost. Turning now to Fig. 2 there is illustrated an embodiment of the present invention in which the number of memory elements required by the front-end and back-end devices, when considered in combination, is effectively halved. A streaming media system 36 according to one embodiment of the present invention is illustrated and which comprises a DVD+RW engine 38 again including an optical pick-up unit (not shown) and arranged for reading data from, and delivering data to, an optical disk 40. An MPEG codec 42 again effectively forming a back-end device for the system 36 is also shown. As should be appreciated a buffer manager 44 provided for handling the media stream within the front-end device 38 is actually located as part of the back-end device 42, while a RISC control processor 46 of the front-end device remains within the DVD+RW engine 38. An IDE connection 48 is again provided for allowing access between the buffer manager 44 and the memory subsystem 50 of the back-end device 42 and serves as an interface device to replace the standard ATAPI interface between the front-end 38 and back-end 42 devices. The repartioning achieved within the invention provides for an internal IDE interface which advantageously allows for the use of currently available software. This data path interface is used in DVD decode mode to transfer the actual DVD data as well as the DVD corrections. In the case of optional double buffering in DVD encode mode, the interface is arranged to transfer the DVD data twice so that it becomes possible to generate inner and outer parity words without having to store the data inside the channel codec. The data bus between the repartioned IP blocks is of asynchronous nature and can comprise, in DVD decode mode, a 16-bit bus plus three control lines for the data and another 8-bit correction bus plus an additional four control signals. In DVD encode mode, 16 data bits plus a single control bit for normal data are employed although of course an additional 16 data bits can be applied in the case of double buffering . Such a bus arrangement is advantageous in that it is asynchronous and therefore relatively easy to implement with regard to timing constraints. With regard to timing skew it offers a low pin count/cost with the pin count comparable to standard ATAPI interface. As with Fig. 1 , a separate RISC control processor 52 is likewise provided within the back-end MPEG codec device 42. In order to allow access of the control processor 46 of the front-end device 38 to the memory subsystem 50 of the back-end device 42, and thereby remove the need to provide a separate memory element for the front-end device 38, there is provided a bursty interface 54 for allowing the particular access for the control' processor 46 into the memory subsystem 50 of the back-end device 42. The interface 54 between the two memory subsystems comprises an asynchronous interface which is likewise advantageously simple to implement with regard to timing constraints and skew, it also uses a single control line plus a 16-bit data bus. This bus is used to transfer command packets as well as the actual data. The command packets will consist of a 28-bit address while the remaining bits indicate whether a read or write operation is performed, the type of data to be transferred and the length of the data burst. Normally data blocks of 32-byte length are transferred so as to minimise the impact of memory sub-system latency and command overhead. This interface link 54 offers advantages of low pin count/cost, asynchronous operation, and a burst mode to minimise memory subsystem latency and command overhead. While, from reference to Fig. 2, it will be appreciated that a buffer-less and ROM-less DVD+RW engine 38 are thus provided, the functional memory requirements for the DVD+RW engine are effectively provided by a Double Data Rate(DDR) memory device 56 associated with the memory subsystem 50 of the back-end device 42 and a flash memory element 58 connected to the back-end device 42 by way of the memory interface unit (not shown). By way of the illustrated configuration, the control processor 46 within the front-end device 38 can effectively execute code from the memory subsystem 50 of the back-end MPEG codec 42 such that no code storage, either by way of a ROM nor SDRAM element, is then required for the processor within the front-end DVD+RW engine. Thus, the data path and microprocessor of an optical disk engine can be provided in a virtually memory-less configuration with the exception of memories required for the caches for the microprocessor of the front-end engine. As will therefore be appreciated, the particular architecture partitioning arising within the present invention is distinct from that found within currently known systems since the IP processing is removed from the front-end engine 38, i.e. principally the buffer manager 16, and located, instead, within the back- end of multimedia codec 42, this overcomes the need for local storage within the front-end engine 38 which therefore provides for an additional improvement over and above the above-mentioned sharing of the bulk storage capabilities. Indeed, when considering the optical channel path within the system, the memory elements are not necessarily shared since, by means of the above-mentioned specific partitioning with regard to known architectures, the requirement for bulk storage within the front-end engine 38 is effectively removed.

Claims

1. A multimedia processor system arranged for receiving digital data and comprising first and second circuit devices having memory requirements, the system including means for partitioning IP blocks in the digital data such that a buffer associated with the handling of digital data in the said first circuit device is located in the said second circuit device.

2. A system as claimed in Claim 1 , wherein memory subsystems of the first and second circuit devices are connected such that a processor of the said first circuit device can access code and variable storage in the memory subsystem of the said second circuit device.

3. A multimedia processor system arranged for receiving digital data and comprising first and second circuit devices having memory requirements, wherein memory subsystems of the first and second circuit devices are connected such that a processor of the said first circuit device can access code and variable storage in the memory subsystem of the said second circuit device.

4. A system as claimed in Claim 1 , 2 or 3, and arranged as a streaming media system and wherein the first and second circuit devices comprise a front-end IC and a back-end IC devices respectively.

5. A system as claimed in Claim 4, wherein the said first circuit device comprises a DVD engine and the said second device comprises a codec.

6. A system as claimed in Claim 1 , 2, 3, 4 or 5, and comprising a DVD+RW system.

7. A method of processing multimedia digital data within first and second circuit devices, the method including the step of partitioning IP blocks in the digital data such that a buffer associated within the handling of digital data in the said first circuit device is located in the said second circuit device.

8. A method as claimed in Claim 7, and including the step of accessing code and variable storage in a memory subsystem of the said second circuit device by way of a processor in the said first circuit device through a connection between the said first and second circuit devices.

9. A method of processing multimedia digital data within first and second circuit devices, and including the step of accessing code and variable storage in a memory subsystem of the said second circuit device by way of a processor in the said first circuit device through a connection between the said first and second circuit devices.