WO2005101293A1

WO2005101293A1 - Real time signal recognition system and method therefor

Info

Publication number: WO2005101293A1
Application number: PCT/JP2004/013597
Authority: WO
Inventors: Makoto Sasaki
Original assignee: The University Of Tokyo
Priority date: 2004-04-06
Filing date: 2004-09-10
Publication date: 2005-10-27
Also published as: JP3951037B2; JP2005301342A

Abstract

For real time and continuously recognizing and evaluating digitalized variation of a very weak signal in an analog signal having background noise. Real time evaluation of the input signal in a range of detecting time window to find as an index of significance signal starting time and signal terminating time for a signal having maximum S/N value and in a trigger and judgment circuit the result of signal recognition i.e. signal starting time and signal terminating time and S/N value from one input or plural inputs is calculated and evaluated and only significant data as a result of signal recognition delivered to an outer bus.

Description

DESC IPTION

REALTIME SIGNAL RECOGNITION SYSTEM AND METHOD THEREFOR

[0001]

Field of the Invention The present invention related to a real time signal recognition system and method therefor in which a very weak minor digital signal occurring repeatedly and instantaneously and also varying according to lapse of time being based on an analog signal representing continuously occurring natural phenomenon is processed to recognize, evaluate and to detect it. [0002] Prior Art In the prior art, for real time recognizing of a signal, an algorithm is needed together with a circuit to realize such an algorithm, by which all the input signal waveform is at first analog to digital converted and stored in a temporary memory, then within a time frame in which the digital waveform shows overflow from the memory space the signal is recognized. [0003] However, in the known algorithm, if the time interval for effecting the signal recognition is too short, it was not possible to catch all the aspect of an air shower, and if it is too long the probability of pick up noises may increase and cause problems. [0004]

Background of the Invention Object Under the abovementioned situation, the present invention has for its object to improve the signal recognition algorithm of the digital signal recognition circuit so that a coarse real time signal recognition for a very wide range phenomenon is realized and thereafter to make it possible to realize detailed fine recognition and evaluation by an improved real time signal recognition system and method therefor. [0005]

Means to Solve the Problem Namely, in general, according to the present invention, the means for analog to digital conversion of the input signal, the signal recognition element and storing are made to be a unitary pipeline, so that removal of the noise and recognition of digital features of the signal waveform are all effected in real time. The features of signal waveform means starting time of the signal, terminating time thereof and S/N ratio (signal to noise ratio). [0006] Effect of the Invention In accordance with the present invention, it becomes possible to catch a very weak signal with high sensitivity even if there is high variation of the background noises. The real time signal recognition system according to the present invention will be able to effect a high speed automatic real time judgment by collecting information of a single or plural real time signal recognition. The system catches a high speed phenomenon forming a "retail of flying subject" or "block" in the time space and is able to make a picture image thereof and to detect it. So the invention realizes improvement of detection sensitivity and a high speed real time judgment and may contribute in the field of detection and testing of a very weak electric signal, a high speed picture recognition so that it may contribute in the field of diagnosis, anti disaster, and defense by the improvement of sensitivity and by high speed automatic real time judgement. [0007] According to the present invention a continuous real time detection and supervision for the varying signal of a very weak signal covered by noises, or that of a very weak signal coming from a high speed moving object may become possible. This will be explained in more detail afterward. [0008] Description of Drawings The invention will now be described by referring to the accompanied drawings of which; Fig. 1 shows a block diagram showing a main construction of the real time signal recognition system according to the present invention, Fig. 2 is an explanatory diagram for explaining an algorithm of the real time signal recognition of the present invention, Fig. 3 is a drawing for showing one example of a manner of sectioning in the case of a band width is 32 bin in a coarse signal recognition, Fig. 4 is an explanatory diagram showing the coarse signal recognition in which a detected signal region is 4 bin, Fig. 5A is a diagram showing an ADC (analog to digital converted) value without deducting average background noise, Fig. 5B is a diagram showing the ADC value after deducting the average background noise, and Fig. 6 is a time chart showing DSP (digital signal processor) operation in the signal recognition program. [0009] Embodiment Fig. 1 shows in block diagram the construction of a real time signal recognition system according to the present invention. In this diagram, a high speed analog to digital conversion circuit 1 acts to convert the input analog signal waveform into digital form and the converted digital data is stored in waiting memory 2. [0010] A digital signal recognition circuit 3 processes the supplied digital signal according to signal recognition algorithm which will be explained in detail hereinafter. As the result, within a range of detection window, the signal starting time and the terminating time within which the signal to noise ratio (S/N ratio) becomes maximum are evaluated in real time to set an index of significance of the signal and the value is stored in the output memory 4 together with the S/N value being considered at that time. [0011] Reference numeral 5 denotes a trigger judgment circuit and it may treat a plural number of units of which one unit consists of the circuits 1 to 3. This trigger judgment circuit 5 when handling signals coming from a two dimensional picture element via such plural units of circuits, the result of signal recognition from such signal (i.e. starting time and terminating time and S/N value) is calculated in real time and evaluate them and make a judgment to control whether or not to deliver the data stored in the output memory to outer bus 6, of which data is signal recognition result data coming from one or plural units. This outer bus 6 is connected to down stream computers or network devices and transmit the data for controlling devices in the down stream.

[0012] The function of the above digital signal recognition circuit 3 will be explained. This circuit is in cooperate with the high speed analog to digital converter 1 and the waiting memory 2 and the analog signal is supplied as explained before. The analog signal supplied from a photo electronic multiplier tube is converted into a digital signal and treated to find out a signal having largest S/N ratio embedded in the noise in the signal. This signal recognition circuit comprises an operating circuit called as a digital signal processing element (DSP). [0013] In an embodiment of this invention, a fixed decimal point type DSP, manufactured by Texas Instrument Corporation and sold under a trade name TMS 320VC5409A (hereinafter called as 5409A) is used. This DSP has its operational capacity of 150 million times per one second. [0014] In accordance with the present invention, a new signal recognition method is developed, by which the digital signal continuously fed to the DSP is divided by a certain constant interval, and compares the divided one interval signal with various signal patterns each having different starting time or rising up time and terminating time or falling down time and calculates the S/N ratio and to select out one signal interval having the maximum S/N ratio. [0015] The 5409Ahas its internal memory of 32K word capacity and it is possible to store the data corresponding to a length of 5 m sec. In this time interval, the signal recognition is effected. The result of the signal recognition is transmitted to a trail recognition circuit and await the triggering judgment of the trail recognition circuit.

[0016] One signal recognition circuit is possible to connect 16 channels of photoelectric multiplier tubes (PMT). Each channel has one DSP for the signal recognition. Furthermore, two DSP are used for board controlling and for communication with the trail recognition circuit. Thus all together 18 set of DSP are used. [0017] For the communication between these DSP, a multi-channel buffered serial port (McBSP) is used. One DSP is equipped with 3 channels of McBSP each has possibility for bi-directional communication. By this arrangement, the maximum communication speed in each channel is 50M Bit/sec. For this transferring, a Direct Memory Access (DMA) can be used without the use of a central processing unit (CPU). For the method of communication between the DSP it is further possible the use of an interrupt signal or the method of using outside an input/output pin called as BIO pin or XF pin. [0018] The data stored in each channel is transferred to the board controlling DSP in accordance with the data request from the trail recognition circuit via the McBSP. The data is finally transferred to a dual port memory being accessable from both the board controlling DSP and PC, and then passed to PC side. The transfer speed from its board controlling DSP to the dual-port memory is about 44 ns/word. [0019] The real time signal recognition algorithm of the signal recognition system according to the present invention will be explained by referring to Fig. 2. The input waveform being continuously digital time sequenced digital signal is effected the signal recognition in detection windows each having a certain constant time interval. Namely all the time sequenced digital data is subject to signal recognition in the detection windows. [0020] The noise in one detection window is processed by deduction of average noise value calculated by using noise in the previously located window, so that data of only the signal and the fluctuation of noise may be obtained.

[0021] On behalf of efficiency of the operating time, the signal recognition is effected in two steps, i.e., coarse signal recognition and fine signal recognition. In the coarse signal recognition, the time in one detection window is divided by 4, 8, 16, 32, 64, etc. In each of the divided time periods, the S/N ratio is calculated and the time period having the maximum S/N ratio is to be found. [0022] Then in the fine signal recognition, both boundaries of the detection window are varied finely by each finely divided section and processed to find further maximum S/N section. Finally, the maximum S/N value and the time section in the detection window is determined. The above is brief outline of the real time signal recognition algorithm. [0023] As one example of the present invention, the inventor had estimated the signal continuation time of the air shower of a photo multiplier transistor (PMT) by using simulation method. As the result we noted that 90 % of the air showers having 10ⁿ{21}eN being the largest energy considered at present have the signal continuation time less than 25.6μs. Under the situation, it is decided that in the present invention, to effect the signal recognition in the detection windows each having a width of 25.6μs. [0024] The analog signal delivered from the photo-electronic multiplier is sampled at each 200ns, so that one detection window is divided by 128 bin. Provided that the S/Ν ratio is compared at all possible signal widths and positions, it becomes possible of 8256 cases. Thus by the presently available DSP operation capacity, it is not possible to process all such cases. Under the situation, a two-step S/Ν maximum signal recognition algorithm is applied as will be explained hereinafter. [0025] Explanation of coarse signal recognition One signal block of 128 bin length is sub-divided by 4 bin, 8 bin, 16 bin and 32 length. Among such sub-divided regions the (S/N)' value is evaluated in each sub-divided region and search a region in which (S/N)' ratio is maximum.

[0026] The following equation shows this situation. (S/N)' = 7 FFF h/sqrt (Δ) x Q herein; Δ ; width of the region, Q ; integrated value of (ADC value - average background noise) in the region.

[0027] The value of 7 FFF h/sqrt (Δ) is previously memorized in the memory for the value in round figures after rounding the fraction less than decimal point.

So that time for calculation is short.

[0028] The 128 bin is divided equidistantly and further sub-divided by shifting half phase. The front and rear boundaries of thus found region are decided as signal starting or raising up time Ti and terminating or falling down time T₂. An example of region width is 32 bin is shown in Fig. 3 as the manner of sub-division.

[0029]

Explanation for Fine signal recognition The region found by coarse signal recognition is shifted by 1 bin forwardly and backwardly and the rising up time Ti and falling down time T₂ of the signal having maximum S/N value are obtained. (S/N)' = 7 FFF h/sqrt (Δ+dΔ) x (Q+dQ) wherein; dΔ ; shifting width of Ti or T₂, dQ ; variation value of Q by varying region 7 FFF h/ sqrt (Δ+dΔ) ; this value is previously memorized in memory for the value in rounding off values adjusting fractions less than decimal point.

[0030] So the calculation time can be saved. Both Ti and T₂ are shifted in forward and backward direction by ± Δ/2 from the position found by the coarse signal recognition.

[0031] In view of the problem of the calculation time, Ti and T are both independently treated to find the most suitable value, respectively. Fig. 4 shows, as an example, in case of the width of the signal found by the coarse signal recognition is 4 bin. [0032] Calculation of the average background value At the time of obtaining the S/N value, the average value of the background noise is deducted previously. By this the objective signal is seen clearly. [0033] In one channel of the digital signal recognition circuit, 3 integrators are used. Each of the integrators calculates a respective average value of the ADC. At the time of signal recognition, each of the integrators will acquire one ADC value for each one detection window corresponding to it and thus the average of the ADC value for 256 detection windows (corresponding to 6.6ms) are calculated. When adding a new ADC value, a value having a substantially larger deviation from the average value obtained previously is omitted. The average value of the ADC from one integrator is stored in the memory with upper 16 bits as the round number data and lower 8 bits as the decimal number data. [0034] Figs. 5A and 5B show the ADC value deducted by the average background signal and without deduction of the same, respectively. [0035] Explanation of signal recognition program Signal recognition is effected at a period of 25.6μs. The digital signal processor (DSP) is housed with a timer so that by a given program it can transmit an interrupt signal of any period to the CPU. The period of 25.6μs is provided by the timer of TrgDSP. [0036] The signal recognition circuit comprises a DSP for board controlling (TrgDSP), a DSP for transferring the result of signal recognition (resDSP) and a DSP of signal recognition in each channel (SubDSP). According to the signal recognition program the above DSP will function of the followings as shown in Fig. 6.

(1) timer interrupt is applied to TrgDSP;

(2) TrgDSP send interrupt instruction to ResDSP and SubDSP;

(3) TrgDSP initializes the DMA so as to start waveform receiving from SubDSP and trigger receiving from trail recognition circuit. After transmitting trigger pulse to SubDSP, sending out previously received data to a common memory.

(4) SubDSP starts the signal recognition by receiving interrupt signal. Transmit waveform data at each substantially 5μs, transmitting the result of signal recognition to ResDSP, and receiving a trigger signal from TrgDSP (the time is adjusted by the timer).

(5) ResDSP initializes the DMA at the receipt of interrupt signal, and start receiving the result of signal recognition from SubDSP and transmitting the result of signal recognition to the trail recognition circuit.

[0037] Fig. 6 shows a time chart of data exchange between DSP in the signal recognition circuit. As mentioned before, there are three kinds of DSP in the signal recognition circuit. Namely, TrgDSP, SubDSP and ResDSP. Among various DSP, there are CPU able to various data processing and a DMA controller being able only the data transferring process (DMA4 and DMA5 in the figure). [0038] Fig. 6 shows time bands and in which time band what kind of the data is processed by the CPU and DMA controller. [0039] For the evaluation of signal recognition ability, the inventor had developed a program using computer language (C-language), which is equivalent to the signal recognition program functioning on the signal recognition circuit. The signal recognition program in the DSP and that in the C-language may have perfectly identical signal recognition result as far as the input data is identical. [0040] The noise under night light is estimated about 20 count in ADC value (the value of analog signal after digital conversion). A simulated data of the above noise is added with a signal having length of lμs, 2μs — 8μs and S/N ratio of 2δ, 2.5δ, 3δ, 3.5δ — 6δ and the result after passing the above signal recognition programs have been evaluated. In this evaluation, if the error is within 3 bin against real Ti and T it is assumed as "right". The value 3 bin is the allowable amount for Ti and T when making trigger judgment in the trail recognition circuit. This result is shown in Table 1. [0041] The Table 1 shows the evaluation for the signal recognition ability. Namely, this table shows the degree of recognition of the signal recognition program against various signals differing in width or length and the intensity. The signal width or length is shown on top row at lμs - 8μs. The intensity is shown on left column expressed by S/N ratio 2.0 - 6.0. The numerals in the table show the degree of correct recognition in (%) and from left to right; Ti only / T₂ only / Ti and T [0042] Table 1

[0043] Industrial Applicability The content of the present invention had been described as above.

The effect and presently considered industrial applicability of the real time signal recognition system of the present invention are as follows:

(1) Detection and even obtaining picture of very weak signal of high speed moving objects which had been impossible by a conventional non-real time signal recognition method or triggering method may become possible.

(2) An automatic high sensitivity detection for weak signal embedded in noise at maximum (S/N) sensitivity becomes possible.

(3) By collecting the information of single or plural real time signal recognition to detect without any loss a high speed phenomena forming a "trail" or a "block" in a time space becomes possible.

(4) Improvement of the detection sensitivity in the field of checking weak electric signal, high speed picture recognition, diagnosis, anti-disaster or defense purposes and also realization of judgment of high speed automatic real time judgment may become possible.

(5) Even under a situation of high variation of background noise, a weak signal can be caught at high sensitivity and also by collecting information of single or plural real time signal recognition to detect to get picture without any loss for a high speed phenomena and to form the "trail" or the "block" in time space may become possible.

[0044] In summary, the system of the present invention has its particular feature being able to detect the presence of a very short continuous time pulse signal and the real time acquisition of the starting time and terminating time thereof without any non-sensitive time using a digital calculation method of signal to noise ratio among randomly occurring noise. Further the system is able to deliver the detected data to other digital processing devices. The system contributes in the field of very weak signal searching, a high speed picture recognition, diagnosis, anti-disaster and defense, etc., for the improvement of detection sensitivity and high speed automatic real time judgment and it has a great value in industrial availability.

Claims

£% A I M S 1. A real time signal recognition system comprising in combination: a high speed analog to digital conversion circuit for digitalizing an input analog signal, a waiting memory temporarily storing digital output signal of said high speed analog to digital conversion circuit, a digital signal recognition circuit for digitally processing the digital signal stored in said waiting memory according to a real time signal recognition algorithm and for evaluating the digital signal in real time by using a predetermined detection window and by a range of said predetermined detection window to find out a signal having a maximum signal to noise ratio (S/N ratio) as an index of significance of the signal and to output data of starting time and terminating time of the determined maximum S/N signal together with the S/N value, an output memory for storing said output data, and a trigger judgment circuit, which may treat a plural number of units of which one unit consists of the analog to digital conversion circuit, the waiting memory and the digital signal recognition circuit, the trigger judgment circuit when handling a signal from a two dimensional picture with such plural number of units, results of signal recognition from one or plural such units, the result being the starting time and the terminating time and S/N ratio, are calculated and evaluated in real time and are controlled whether or not to deliver resultant data of the signal recognition stored in the output memory to an outer bus. 2. A real time signal recognition system as claimed in claim 1, wherein said outer bus is connected computer devices or necessary networks in down stream to transmit the data for correction of such devices in the down stream. 3. A real time signal recognition system as claimed in claim 1, wherein the real time signal recognition algorithm of the digital signal recognition circuit is so arranged to divide into coarse signal recognition and fine signal recognition for efficiently saving processing time, in the coarse signal recognition, the time in the detection window is divided by 4, 8, 16, 32, 64, etc., and in each one of divided time frame the S/N value is calculated to detect a time frame having a maximum S/N value, and in the succeeding fine signal recognition, both time boundaries of the time frame having the maximum S/N value are finely varied to find out further time frame of maximum S/N value and in this detection window the signal recognition is effected, so that the input waveform of continuously digitalized time sequence is recognized in a certain deviation in each detection window and thus all the digital time sequence signal is recognized. 4. A real time signal recognition system as claimed in claim 3, wherein said real time signal recognition algorithm is further characterized in that noise in one detection window is deducted by a calculated value of noise in the previous detection window so that detected result is just a signal and variation of noise and a data in a detection window at which the maximum S/N ratio is detected is delivered to the output memory and wait the trigger judgment. 5. A real time signal recognition method for selectively detecting presence of a short time very weak pulse signal coexisting mixedly randomly occurring background noise signal, comprising steps of; converting an input analog signal into a digital signal by a high speed analog to digital conversion circuit, temporarily storing said converted digital signal in a waiting memory, digitally processing said stored digital signal according to a signal recognition algorithm and evaluating in real time to determine starting time and terminating time of a signal having maximum S/N value as a significance index in a detection window of a predetermined time length, and to output said data of the starting time and terminating time together with the S/N value, and triggering judging resultant data from plural units, of which one unit consists of said converting step, storing step and recognition step, by calculating above resultant data in real time and evaluating it and making judgment whether or not to deliver the result to an outer bus. 6. In a method as claimed in claim 5, wherein the signal recognizing algorithm of the digital signal recognition circuit is effected by dividing the process as a coarse signal recognition step and a fine signal recognition step for saving the processing time, in the coarse signal recognition step the time in a detection window is divided by 4, 8, 16, 32, 64 etc., and in each of the divided time frame S/N ratio is calculated to find out maximum time frame, and in the fine signal recognition, left and right boundaries of the time frame found as to having maximum S/N value are finely deviated by each one section and trying to find further maximum S/N section of the detection window and to effect recognition in that section so by this step all the continuously digitalized time sequence signal input waveform is signal recognized in a certain time frame, and by deducting a calculated noise value of previously located time frame of the detection window, the reorganized signal becomes a signal and fluctuation of the noise value and transmitting the data in said detection window where the maximum S/N value is detected to an output memory and to be subject for triggering judgment.