WO2005096366A1 - A method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same - Google Patents

A method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same Download PDF

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Publication number
WO2005096366A1
WO2005096366A1 PCT/US2005/010288 US2005010288W WO2005096366A1 WO 2005096366 A1 WO2005096366 A1 WO 2005096366A1 US 2005010288 W US2005010288 W US 2005010288W WO 2005096366 A1 WO2005096366 A1 WO 2005096366A1
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Prior art keywords
gate electrode
recited
silicided
blocking layer
polysilicon gate
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French (fr)
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Jiong-Ping Lu
Haowen Bu
Shaofeng Yu
Ping Jiang
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Texas Instruments Inc
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Texas Instruments Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H10D64/668—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the layer being a silicide, e.g. TiSi2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H10D30/0213—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation providing different silicide thicknesses on gate electrodes and on source regions or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/0131—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
    • H10D64/0132—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN the conductor being a metallic silicide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers

Definitions

  • the present invention is directed, in general, to a method for manufacturing a semiconductor device and, more specifically, to a method for manufacturing a semiconductor device having a suicided gate electrode and a method for manufacturing an integrated circuit including the same.
  • Metal gate electrodes are currently being investigated to replace polysilicon gate electrodes in today' s ever shrinking and changing transistor devices.
  • One of the principle reasons the industry is investigating replacing the polysilicon gate electrodes with metal gate electrodes is in order to solve problems of poly-depletion effects and boron penetration for future CMOS devices.
  • a polysilicon gate electrode with an overlying suicide was used for the gate electrodes in CMOS devices.
  • poly depletion becomes a serious issue when using polysilicon gate electrodes.
  • metal gates have been proposed.
  • the metal gates need dual tunable work functions.
  • the metal gates need tunable work functions for NMOS and PMOS devices similar to present polysilicon gate technology, requiring the work functions of metal gates to range from 4.1- 4.4eV for NMOS and 4.8 ⁇ 5.1eV for PMOS (see, B. Cheng, B. Maiti, S. Samayedam, J. Grant, B. Taylor, P. Tobin, J. Mogab, IEEE Intl . SOI Conf. Proc , pp. 91-92, 2001).
  • suicided metal gates have been investigated based on the extension of existing self-aligned suicide (SALICIDE) technology.
  • SALICIDE self-aligned suicide
  • polysilicon is deposited over the gate dielectric.
  • a metal is deposited over the polysilicon and reacted to completely consume the polysilicon resulting in a fully suicided metal gate, rather than a deposited metal gate.
  • the suicided metal gate provides a metal gate with the least perturbation to the conventional process and avoids contamination issues.
  • poly doping has been shown to affect the work function of the suicided metal gates.
  • the suicided metal gates are not without their problems.
  • One of the more significant problems associated with the suicided metal gates is attributed to the simultaneous formation of the suicided metal gate and the suicided source/drain regions.
  • the depth of the suicided source/drain regions is directly proportional to the thickness of the polysilicon gate electrode.
  • the polysilicon gate electrodes currently range in thickness from about 60 nm to about 120 nm, the suicided source/drain regions ultimately extend into the silicon substrate by up to about 60 nm to about 120 nm, respectively. Deep suicided source/drain regions are nonetheless undesirable.
  • Various companies in the industry have attempted to separate the silicidation of the polysilicon gate and the silicidation of the source/drain regions.
  • CMP chemical mechanical polishing
  • the present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device.
  • the method for manufacturing the semiconductor device includes forming a polysilicon gate electrode over a substrate and forming source/drain regions in the substrate proximate the polysilicon gate electrode.
  • FIGURE 1 illustrates a cross-sectional view of one embodiment of a semiconductor device constructed according to the principles of the present invention
  • FIGURE 2 illustrates a cross-sectional view of a partially completed semiconductor device manufactured in accordance with the principles of the present invention
  • FIGURE 3 illustrates a cross-sectional view of the partially completed semiconductor device illustrated in FIGURE 2 after formation of a portion of gate sidewall spacers
  • FIGURE 4 illustrates a cross-sectional view of the partially completed semiconductor device illustrated in FIGURE 3 after formation of lightly doped extension implants within the substrate
  • FIGURE 5 illustrates a cross-sectional view of the partially completed semiconductor device illustrated in FIGURE 4 after forming the remaining portions of the gate sidewall spacers
  • FIGURE 6 illustrates a cross-sectional view of the partially completed semiconductor device illustrated in FIGURE 5 after etching the cap oxide from the top of the substrate and top of the protective layer, as well as after formation of highly doped source/drain implants within the substrate
  • FIGURE 7 illustrates a cross-sectional view of the partially completed semiconductor device illustrated in FIGURE 6 after subjecting the semiconductor device
  • FIGURE 10 illustrates a cross-sectional view of the partially completed semiconductor device illustrated in FIGURE 9 after depositing a second silicidation metal over the exposed portions of the polysilicon gate electrode, as well as over the remainder of the semiconductor device;
  • FIGURE 11 illustrates a cross-sectional view of the partially completed semiconductor device illustrated in FIGURE 10 after converting the polysilicon gate electrode to a silicided gate electrode;
  • FIGURE 12 illustrates an exemplary cross-sectional view of an integrated circuit (IC) incorporating devices constructed according to the principles of the present invention;
  • FIGURE 13 illustrates another exemplary cross- sectional view of an integrated circuit (IC) incorporating devices constructed according to the principles of the present invention, where the top portion of the poly gate electrode is silicided to form a self-aligned suicide contact.
  • FIGURE 1 illustrated is a cross-sectional view of one embodiment of a semiconductor device 100 constructed according to the principles of the present invention.
  • the semiconductor device 100 includes a substrate 110.
  • a well region 120 Located within the substrate 110 in the embodiment of FIGURE 1 is a well region 120.
  • a gate structure 130 located over the substrate 110 and well region 120 is a gate structure 130.
  • the gate structure 130 illustrated in FIGURE 1 includes a gate oxide 140 located over the substrate 110, as well as a silicided gate electrode 150 located over the gate oxide 140. While the silicided gate electrode is illustrated in FIGURE 1 as a fully silicided gate electrode, those skilled in the art understand that the silicided gate electrode 150 could also comprise a partially silicided gate electrode where only the top portion of the electrode is silicided. This embodiment might be used if there was a need to reduce the contact resistance of the silicided gate electrode 150. [0024] The silicided gate electrode 150 may have a variety of thicknesses, nonetheless, a thickness ranging from about 50 nm to about 150 nm is exemplary.
  • the silicided gate electrode 150 when constructed in accordance with the principles of the present invention, may comprise a number of different materials.
  • the silicided gate electrode 150 comprises nickel, however, it is envisioned that the silicided gate electrode 150 could comprise cobalt, platinum, titanium, tantalum, molybdenum, tungsten, etc., while staying within the scope of the present invention .
  • the silicided gate electrode 150 may also include a dopant or combination of several types of dopants therein.
  • the dopant such as boron, phosphorous, arsenic or another similar dopant based on whether the semiconductor device 100 is operating as a PMOS device or an NMOS device, is configured to tune the minimum energy required to bring an electron from the Fermi level to the vacuum level, or the so called work function.
  • the gate structure 130 further contains gate sidewall spacers 160 flanking both sides of the silicided gate electrode 150 and gate oxide 140.
  • the gate sidewall spacers 160 in the embodiment of FIGURE 1 each include a number of different layers.
  • the gate sidewall spacers 160 each include L-shaped nitride spacers 163 and sidewall oxides 168.
  • the L-shaped nitride spacers 163 comprise a unique nitride layer that includes carbon.
  • the carbon content may be within a wide range, however, it is believed that a carbon content ranging from about 5% to about 10% is advantageous.
  • the other layers, among other materials, could include a collection of oxides and nitrides.
  • the gate sidewall spacers 160 may comprise many different types and numbers of layers while staying consistent with the principles of the present invention.
  • the semiconductor device 100 illustrated in FIGURE 1 additionally includes conventional source/drain regions 170 located within the substrate 110 and proximate the gate oxide 140. Located within the source/drain regions 170 are blocking layers 180.
  • the blocking layers 180 in the embodiment of FIGURE 1 function both as a protectant from the silicidation material used to form the silicided gate electrode 150, as well as source/drain contact regions.
  • the blocking layers 180 when manufactured in accordance with the principles of the present invention, comprise a metal suicide.
  • the blocking layers 180 comprise a metal suicide different from the metal suicide of the silicided gate electrode 150, however, in another embodiment they comprise a metal suicide the same as the metal suicide of the silicided gate electrode 150.
  • the silicided gate electrode 150 in the embodiment of FIGURE 1 comprise nickel suicide
  • the blocking layers 180 comprise a different metal suicide.
  • the blocking layers 180 comprise cobalt suicide. Nonetheless, other silicidation materials (e.g., nickel, platinum, titanium, tantalum, molybdenum, tungsten, etc.) could be used to form the blocking layers 180 and remain within the scope of the present invention.
  • the blocking layers 180 may have a depth into the source/drain regions 170 ranging from about 10 nm to about 35 nm, among others. This depth needs to be sufficient to prevent the silicidation metal used to form the silicided gate electrode 150 from affecting the source/drain regions 170, however, small enough to be consistent with the design of the present invention .
  • FIGURES 2-11 illustrated are cross- sectional views of detailed manufacturing steps instructing how one might, in an advantageous embodiment, manufacture a semiconductor device similar to the semiconductor device 100 depicted in FIGURE 1.
  • FIGURE 2 illustrates a cross-sectional view of a partially completed semiconductor device 200 manufactured in accordance with the principles of the present invention.
  • the partially completed semiconductor device 200 of FIGURE 2 includes a substrate 210.
  • the substrate 210 may, in an exemplary embodiment, be any layer located in the partially completed semiconductor device 200, including a wafer itself or a layer located above the wafer (e.g., epitaxial layer).
  • the substrate 210 is a P- type substrate; however, one skilled in the art understands that the substrate 210 could be an N-type substrate without departing from the scope of the present invention. In such a case, each of the dopant types described throughout the remainder of this document would be reversed. For clarity, no further reference to this opposite scheme will be discussed. [0030] Located within the substrate 210 in the embodiment shown in FIGURE 2 is a well region 220. The well region 220, in light of the P-type semiconductor substrate 210, would more than likely contain an N-type dopant.
  • the well region 220 would likely be doped with an N-type dopant dose ranging from about 1E13 atoms/cm 2 to about 1E14 atoms/cm 2 and at an energy ranging from about 100 keV to about 500 keV. This results in the well region 220 having a peak dopant concentration ranging from about 5E17 atoms/cm 3 to about 1E19 atoms/cm 3 .
  • the gate structure 230 includes a gate oxide 240 and a polysilicon gate electrode 250.
  • the gate oxide 240 may comprise a number of different materials and stay within the scope of the present invention.
  • the gate oxide 240 may comprise silicon dioxide, or in an alternative embodiment comprise a high dielectric constant (K) material.
  • the gate oxide 240 is a silicon dioxide layer having a thickness ranging from about 0.5 nm to about 5 nm.
  • Any one of a plurality of manufacturing techniques could be used to form the gate oxide 240.
  • the gate oxide 240 may be either grown or deposited.
  • the growth or deposition steps may require a significant number of different temperatures, pressures, gasses, flow rates, etc.
  • the advantageous embodiment of FIGURE 2 dictates that the polysilicon gate electrode 250 comprise standard polysilicon, other embodiments exist where the polysilicon gate electrode, or at least a portion thereof, comprises amorphous polysilicon.
  • the amorphous polysilicon embodiment may be particularly useful when a substantially planar upper surface of the polysilicon gate electrode 250 is desired.
  • the deposition conditions for the polysilicon gate electrode 250 may vary, however, if the polysilicon gate electrode 250 were to comprise standard polysilicon, such as the instance in FIGURE 2, the polysilicon gate electrode 250 could be deposited using a pressure ranging from about 100 torr to about 300 torr, a temperature ranging from about 620EC to about 700EC, and a SiH 4 or Si 2 He gas flow ranging from about 50 seem to about 150 seem.
  • the amorphous polysilicon gate electrode could be deposited using a pressure ranging from about 100 torr to about 300 torr, a temperature ranging from about 450EC to about 550EC, and a SiH 4 or Si 2 H 6 gas flow ranging from about 100 seem to about 300 seem.
  • the polysilicon gate electrode 250 desirably has a thickness ranging from about 50 nm to about 150 nm.
  • the partially completed semiconductor device 200 illustrated in FIGURE 2 further includes a protective layer 260 located over the polysilicon gate electrode 250.
  • the protective layer 260 which may comprise silicon nitride among other materials, may have a thickness ranging from about 5 nm to about 50 nm. It is desirable for the protective layer 260 to have a thickness small enough to allow a dopant to easily penetrate therethrough, however, large enough to provide the sufficient amount of protection to the polysilicon gate electrode 250.
  • a silicon dioxide layer 270 is located over the protective layer 260.
  • the optional silicon dioxide layer 270 is designed to help pattern the gate oxide 240, polysilicon gate electrode 250 and protective layer 260.
  • the gate oxide 240, polysilicon gate electrode 250, protective layer 260 and optional silicon dioxide layer 270 were originally blanket deposited. Those blanket layers were subsequently patterned resulting in the gate oxide 240, polysilicon gate electrode 250, protective layer 260 and optional silicon dioxide layer 270 illustrated in FIGURE 2.
  • the polysilicon gate electrode 250 and protective layer 260 are formed using a chemical vapor deposition (CVD) technique.
  • FIGURE 3 illustrated is a cross- sectional view of the partially completed semiconductor device 200 illustrated in FIGURE 2 after formation of portions of gate sidewall spacers 310.
  • the portions of the gate sidewall spacers 310 shown in FIGURE 3 include an oxide layer 320 and an offset nitride spacer 330.
  • the oxide layer 320 is formed at least partially using a deposition process.
  • the oxide layer 320 is initially formed using a first deposition process, and then finished using a second oxidation process.
  • the first deposition process allows the oxide layer 320 to form on the top and sidewalls of the protective layer 260.
  • the entire oxide layer 320 is deposited.
  • the offset nitride spacer 330 may comprise a standard silicon nitride spacer or a silicon nitride layer having carbon therein. If the offset nitride spacer 330 were to contain the carbon, the carbon might form from about 5% to about 10% of the layer. While the oxide layer 320 and the offset nitride spacer 330 are shown located only along the sides of the gate structure 230, those skilled in the art are aware that the layers were previously blanket formed and subsequently anisotropically etched to form the oxide layer 320 and the offset nitride spacer 330.
  • FIGURE 4 illustrated is a cross- sectional view of the partially completed semiconductor device 200 illustrated in FIGURE 3 after formation of lightly doped extension implants 410 within the substrate 210.
  • the lightly doped extension implants 410 are conventionally formed and generally have a peak dopant concentration ranging from about 1E19 atoms/cm 3 to about 2E20 atoms/cm 3 .
  • the lightly doped extension implants 410 have a dopant type opposite to that of the well region 220 they are located within. Accordingly, the lightly doped extension implants 410 are doped with a P-type dopant in the illustrative embodiment shown in FIGURE 4.
  • FIGURE 5 illustrated is a cross- sectional view of the partially completed semiconductor device 200 illustrated in FIGURE 4 after forming the remaining portions of the gate sidewall spacers 310.
  • a cap oxide 510, L-shaped nitride spacers 520 and sidewall oxides 530 complete the gate sidewall spacers 310.
  • the cap oxide 510 among other purposes, has the job of preventing the L-shaped nitride spacers 520 from directly contacting the substrate 210. Most likely, the cap oxide 510 will be deposited over the partially completed semiconductor device 200 using a process similar to that used to form the oxide layer 320.
  • the L-shaped nitride spacers 520 may comprise any type of nitride, however, in an exemplary embodiment the L-shaped nitride spacers 520 comprise a nitride material that includes carbon.
  • the carbon content which may range from about 5% to about 10% of the L-shaped nitride spacers 520, is included within the L-shaped nitride spacers 520 to change the rate at which they etch.
  • the L-shaped nitride spacers 520 may be deposited using bis t-butylaminosilane (BTBAS) and ammonia (NH 3 ) precursors in a CVD reactor.
  • BBAS bis t-butylaminosilane
  • NH 3 ammonia
  • the carbon causes the L-shaped nitride spacers 520 to etch at a slower rate than a traditional nitride layer.
  • the carbon after having been annealed using a temperature ranging from about 1000EC to about 1100EC, the carbon causes the L-shaped nitride spacers 520 to have an etch selectivity of about 50:1 when compared to the traditional nitride layer.
  • the sidewall oxides 530 that are located over the L- shaped nitride spacers 520 are conventional. In the given embodiment of FIGURE 5, the sidewall oxides 530 were blanket deposited and then subjected to an anisotropic etch. The resulting sidewall oxides 530 complete the gate sidewall spacers 310 illustrated in the embodiment of FIGURE 5. [0043] Turning now to FIGURE 6, illustrated is a cross- sectional view of the partially completed semiconductor device 200 illustrated in FIGURE 5 after etching the cap oxide 510 from the top of the substrate 210 and top of the protective layer 260, as well as after formation of highly doped source/drain implants 610 within the substrate 210. Those skilled in the art understand the conventional processes that could be used to etch the cap oxide 510.
  • the formation of the highly doped source/drain implants 610 is also conventional. Generally the highly doped source/drain implants 610 have a peak dopant concentration ranging from about 1E18 atoms/cm 3 to about 1E21 atoms/cm 3 . Also, the highly doped source/drain implants 610 should typically have a dopant type opposite to that of the well region 220 they are located within. Accordingly, in the illustrative embodiment shown in FIGURE 6, the highly doped source/drain implants 610 are doped with a P-type dopant.
  • FIGURE 7 illustrated is a cross- sectional view of the partially completed semiconductor device 200 illustrated in FIGURE 6 after subjecting the semiconductor device 200 to a standard source/drain anneal, thereby activating source/drain regions 710. It is believed that a source/drain anneal conducted at a temperature ranging from about 1000EC to about HOOEC and a time period ranging from about 1 second to about 5 seconds would be sufficient. It should be noted that other temperatures, times, and processes could be used to activate the source/drain regions 710. [0046] Additionally illustrated in FIGURE 7 is the formation of a silicidation metal 720 over the exposed portions of the source/drain regions 710 as well as over the gate structure 230.
  • the silicidation metal 720 in the embodiment shown in FIGURE 7 happens to be a thin cobalt layer, however, other materials that react with silicon to form a suicide could easily be used.
  • the silicidation metal 720 may also comprise nickel, platinum, titanium, tantalum, molybdenum, tungsten, another similar metal, or any combination thereof while staying within the scope of the present invention.
  • the silicidation metal 720 comprises a different metal than the silicidation metal 1010 (FIGURE 10) . Nonetheless, this is not required to remain within the scope of the present invention.
  • the silicidation metal 720 may be formed using a number of different processes, and may be formed to a number of different thicknesses. In one embodiment of the invention the silicidation metal 720 is deposited to a thickness ranging from about 3 nm to about 10 nm. Such thicknesses, however, might be used when the silicidation metal 720 comprises cobalt. Various other thicknesses could be used if the silicidation metal 720 were to comprise one of the different metals disclosed above. [0048] Turning now to FIGURE 8, illustrated is a cross- sectional view of the partially completed semiconductor device 200 illustrated in FIGURE 7 after subjecting it to a rapid thermal anneal (RTA) .
  • RTA rapid thermal anneal
  • This RTA attempts to cause the silicidation metal 720 to react with the silicon of the source/drain regions 710 to form blocking layers 810.
  • the RTA causes the cobalt to react with the silicon to form a cobalt suicide .
  • the RTA may be conducted using a variety of different temperatures and times. Nonetheless, it is believed that the RTA, in an exemplary embodiment, should be conducted in a rapid thermal processing tool at a temperature ranging from about 400EC to about 600EC for a time period ranging from about 5 seconds to about 60 seconds. The specific temperature and time period are typically based, however, on the ability to form the blocking layers 810 to a desired depth, as well as the suicide materials selected.
  • a selective wet etch using for example a mixture of sulfuric acid (H 2 S0 4 ) , hydrogen peroxide (H 2 0 2 ) and water (H 2 0) , may then be used to remove un-reacted silicidation metal 720 on regions other than exposed silicon, such as on sidewall and gate.
  • another optional RTA step may be used to form a low resistivity phase of the suicide.
  • the first RTA forms CoSi
  • the optional RTA forms CoSi 2 , which has lower resistivity and is more stable.
  • This optional RTA step is typically performed using a temperature ranging from about 650EC to about 800EC for a time period ranging from about 5 to about 60 seconds.
  • FIGURE 9 illustrated is a cross- sectional view of the partially completed semiconductor device 200 illustrated in FIGURE 8 after removing the protective layer 260 from over the polysilicon gate electrode 250 to form an opening 910.
  • the etchant used to remove the protective layer 260 does not substantially affect other structures or films. More specifically, the hot phosphoric acid etchant used to remove the protective layer 260 does not affect the L-shaped nitride spacer 520 and blocking layers 810. Even though the protective layer 260 and the L- shaped nitride spacer 520 both comprise silicon nitride, the carbon content of the L-shaped nitride spacer 520 provides substantial protection from the etchant.
  • FIGURE 10 illustrated is a cross- sectional view of the partially completed semiconductor device 200 illustrated in FIGURE 9 after depositing a second silicidation metal 1010 over the exposed portions of the polysilicon gate electrode 250, as well as over the remainder of the semiconductor device 200.
  • the silicidation metal 1010 is designed to fully silicidize the polysilicon gate electrode 250. As it takes approximately 1 nm of nickel to fully silicidize approximately 1.8 nm of polysilicon, the thickness of the silicidation metal 1010 should be at least 56% of the thickness of the polysilicon gate electrode 250.
  • the thickness of the silicidation metal 1010 should be at least 60% of the thickness of the polysilicon gate electrode 250.
  • the thickness of the silicidation metal 1010 should range from approximately 30 nm to about 90 nm.
  • the silicidation metal 1010 may comprise a number of different metals or combinations of metals while staying within the scope of the present invention.
  • the silicidation metal 1010 may comprise any metal known to react with polysilicon to form a metal suicide.
  • a thinner layer of silicidation metal 1010 may be formed over the exposed portions of the polysilicon gate electrode 250, as well as over the remainder of the semiconductor device 200.
  • the thinner layer of silicidation metal 1010 will only react with the top portion of the polysilicon gate electrode 250, to form a partially silicided gate electrode.
  • the thickness of the thinner layer of silicidation metal 1010 could range from about 3 nm to about 15 nm to only partially suicide the silicided gate electrode. This embodiment is particularly useful for applications where a poly-gate oxide interface is used, rather than a silicide-gate oxide interface, as is the case in the fully silicided gate electrode discussed directly above .
  • FIGURE 11 illustrated is the partially completed semiconductor device 200 illustrated in FIGURE 10 after converting the polysilicon gate electrode 250 to a silicided gate electrode 1110.
  • This RTA is designed to convert the polysilicon gate electrode 250 to the silicided gate electrode 1110.
  • the annealing temperature depends on the suicide metal being used. For example, it is believed that the RTA may be conducted at a temperature ranging from about 350EC to about 550EC and a time period ranging from about 10 second to about 100 seconds to accomplish the silicidation when nickel is used.
  • the silicidation metal 1010 fully silicidizes the polysilicon gate electrode 250.
  • the suicide does not form on the source/drain region 710 at this time because of the blocking layers 810.
  • the partially completed semiconductor device 200 may be subjected to a selective removal process.
  • the device could be subjected to an etch recipe consisting of sulfuric acid (H 2 S0 4 ) , hydrogen peroxide (H 2 0 2 ) and water (H 2 0) .
  • This specific etch recipe has a high degree of selectivity and could easily remove any remaining portions of the silicidation metal 1010.
  • the manufacture of the partially completed semiconductor device 200 would continue in a conventional manner, optimally resulting in a device similar to the semiconductor device 100 illustrated in FIGURE 1. It should be noted that the exact order of the steps illustrated with respect to FIGURES 2-11 may change depending on the process flow.
  • the method of manufacturing the semiconductor device as discussed with respect to FIGURES 2-11 provides many benefits over the prior art methods. First, and possibly most important, it separates the formation of the silicided gate electrode and blocking layers (e.g., silicided source/drain contact regions) into different steps. Advantageously, this allows the depth of the blocking layers (e.g., silicided source/drain contact regions) to be independent of the thickness of the silicided gate electrode.
  • the decoupling of the two steps is achieved by taking advantage of the chemical selectivity of thin films to certain etch chemistries. Accordingly, CMP is not needed as it is in the prior art methods capable of decoupling the steps.
  • the method of the present invention is applicable to devices having different step heights, whether by design or process variation.
  • the CMP technique of the prior art is not capable of accepting such variations in step heights.
  • the method of the present invention allows the blocking layers to also function as the silicided source/drain regions. Accordingly, the present invention requires less processing steps than the prior art options.
  • the method of the present invention allows the semiconductor device to easily choose different silicidation metals for the suicide gate electrode and blocking layers (e.g., silicided source/drain regions). In the embodiment discussed above, the silicided gate electrode benefits from using nickel as the silicidation material.
  • the nickel at least as compared to cobalt, allows the sheet resistance of the silicided gate electrode to remain small as the gate length continues to increase.
  • the blocking layers benefit from using cobalt as the silicidation material.
  • the cobalt at least as compared to nickel, reduces piping defect issues in the source/drain regions.
  • the embodiment of the method discussed with respect to FIGURE 2-11 makes the best use of both nickel and cobalt. It is believed that the other metals would have similar advantages.
  • FIGURE 12 illustrated is an exemplary cross-sectional view of an integrated circuit (IC) 1200 incorporating devices 1210 constructed according to the principles of the present invention.
  • the IC 1200 may include devices, such as transistors used to form CMOS devices, BiCMOS devices, Bipolar devices, as well as capacitors or other types of devices.
  • the IC 1200 may further include passive devices, such as inductors or resistors, or it may also include optical devices or optoelectronic devices. Those skilled in the art are familiar with these various types of devices and their manufacture.
  • the IC 1200 includes the devices 1210 having dielectric layers 1220 located thereover. Additionally, interconnect structures 1230 are located within the dielectric layers 1220 to interconnect various devices, thus, forming the operational integrated circuit 1200.
  • FIGURE 13 illustrated is another exemplary cross-sectional view of an integrated circuit (IC) 1300 incorporating devices 1310 constructed according to the principles of the present invention.
  • the IC 1300 includes devices 1310 having a gate electrode that is only partially silicided.
  • the partially silicided gate electrode is desirable to reduce contact resistance of the poly electrode while keeping the poly-gate oxide interface without a silicide forming at the interface.
  • dielectric layers 1320 Located over the devices 1310 are dielectric layers 1320.
  • interconnect structures 1330 are located within the dielectric layers 1320 to interconnect various devices, thus, forming the operational integrated circuit 1300.

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Abstract

The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device (100), among other possible steps, includes forming a polysilicon gate electrode over a substrate (110) and forming source/drain regions (170) in the substrate (110) proximate the polysilicon gate electrode. The method further includes forming a blocking layer (180) over the source/drain regions (170), the blocking layer (180) comprising. a metal silicide, and siliciding the polysilicon gate electrode to form a silicided gate electrode (150).

Description

A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A SILICIDED GATE ELECTRODE AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT INCLUDING THE SAME
TECHNICAL FIELD OF THE INVENTION [0001] The present invention is directed, in general, to a method for manufacturing a semiconductor device and, more specifically, to a method for manufacturing a semiconductor device having a suicided gate electrode and a method for manufacturing an integrated circuit including the same.
BACKGROUND OF THE INVENTION [0002] Metal gate electrodes are currently being investigated to replace polysilicon gate electrodes in today' s ever shrinking and changing transistor devices. One of the principle reasons the industry is investigating replacing the polysilicon gate electrodes with metal gate electrodes is in order to solve problems of poly-depletion effects and boron penetration for future CMOS devices. Traditionally, a polysilicon gate electrode with an overlying suicide was used for the gate electrodes in CMOS devices. However, as device feature size continues to shrink, poly depletion becomes a serious issue when using polysilicon gate electrodes.
[0003] Accordingly, metal gates have been proposed. However, in order to optimize the threshold voltage (Vt) in CMOS devices, the metal gates need dual tunable work functions. For instance, the metal gates need tunable work functions for NMOS and PMOS devices similar to present polysilicon gate technology, requiring the work functions of metal gates to range from 4.1- 4.4eV for NMOS and 4.8~5.1eV for PMOS (see, B. Cheng, B. Maiti, S. Samayedam, J. Grant, B. Taylor, P. Tobin, J. Mogab, IEEE Intl . SOI Conf. Proc , pp. 91-92, 2001). [0004] Recently, suicided metal gates have been investigated based on the extension of existing self-aligned suicide (SALICIDE) technology. In this approach, polysilicon is deposited over the gate dielectric. A metal is deposited over the polysilicon and reacted to completely consume the polysilicon resulting in a fully suicided metal gate, rather than a deposited metal gate. The suicided metal gate provides a metal gate with the least perturbation to the conventional process and avoids contamination issues. Furthermore, poly doping has been shown to affect the work function of the suicided metal gates.
[0005] The suicided metal gates are not without their problems. One of the more significant problems associated with the suicided metal gates is attributed to the simultaneous formation of the suicided metal gate and the suicided source/drain regions. When formed simultaneously, the depth of the suicided source/drain regions is directly proportional to the thickness of the polysilicon gate electrode. As the polysilicon gate electrodes currently range in thickness from about 60 nm to about 120 nm, the suicided source/drain regions ultimately extend into the silicon substrate by up to about 60 nm to about 120 nm, respectively. Deep suicided source/drain regions are nonetheless undesirable. [0006] Various companies in the industry have attempted to separate the silicidation of the polysilicon gate and the silicidation of the source/drain regions. Those companies employ chemical mechanical polishing (CMP) technology to separate the steps. In such integration schemes, the gate electrode is masked by a silicon oxide layer and a suicide is then formed on the source/drain regions. Next, a blanket dielectric layer is deposited over the gate stack and silicided source/drain regions. The CMP process is then employed to expose the gate electrode for silicidation, while the source/drain regions are covered by the protective dielectric layer. The main drawback of this approach originates from the across-wafer non-uniformity inherently associated with polishing (such as dishing, etc.). In addition, the poly height on the active area may be different from the designed poly height. As a result, the height of the poly gate after polishing may suffer significant variation. Therefore, the silicidation may be inconsistent across-wafer, and/or wafer-to-wafer due to the thickness variation in poly-gate.
[0007] Accordingly, what is needed is a method for manufacturing silicided metal gate structures separate from the silicided source/drain regions that does not experience the drawbacks of the prior art methods. SUMMARY OF THE INVENTION [0008] To address the above-discussed deficiencies of the prior art, the present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device, among other possible steps, includes forming a polysilicon gate electrode over a substrate and forming source/drain regions in the substrate proximate the polysilicon gate electrode. The method further includes forming a blocking layer over the source/drain regions, the blocking layer comprising a metal suicide, and suiciding the polysilicon gate electrode to form a silicided gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS [0009] FIGURE 1 illustrates a cross-sectional view of one embodiment of a semiconductor device constructed according to the principles of the present invention;
[0010] FIGURE 2 illustrates a cross-sectional view of a partially completed semiconductor device manufactured in accordance with the principles of the present invention; [0011] FIGURE 3 illustrates a cross-sectional view of the partially completed semiconductor device illustrated in FIGURE 2 after formation of a portion of gate sidewall spacers; [0012] FIGURE 4 illustrates a cross-sectional view of the partially completed semiconductor device illustrated in FIGURE 3 after formation of lightly doped extension implants within the substrate; [0013] FIGURE 5 illustrates a cross-sectional view of the partially completed semiconductor device illustrated in FIGURE 4 after forming the remaining portions of the gate sidewall spacers; [0014] FIGURE 6 illustrates a cross-sectional view of the partially completed semiconductor device illustrated in FIGURE 5 after etching the cap oxide from the top of the substrate and top of the protective layer, as well as after formation of highly doped source/drain implants within the substrate; [0015] FIGURE 7 illustrates a cross-sectional view of the partially completed semiconductor device illustrated in FIGURE 6 after subjecting the semiconductor device to a standard source/drain anneal, thereby activating source/drain regions, and after depositing a silicidation metal; [0016] FIGURE 8 illustrates a cross-sectional view of the partially completed semiconductor device illustrated in FIGURE 7 after subjecting it to a rapid thermal anneal (RTA) , and after a selective wet etch to remove un-reacted silicidation metal; [0017] FIGURE 9 illustrates a cross-sectional view of the partially completed semiconductor device illustrated in FIGURE 8 after removing the protective layer from over the polysilicon gate electrode to form an opening;
[0018] FIGURE 10 illustrates a cross-sectional view of the partially completed semiconductor device illustrated in FIGURE 9 after depositing a second silicidation metal over the exposed portions of the polysilicon gate electrode, as well as over the remainder of the semiconductor device; [0019] FIGURE 11 illustrates a cross-sectional view of the partially completed semiconductor device illustrated in FIGURE 10 after converting the polysilicon gate electrode to a silicided gate electrode; [0020] FIGURE 12 illustrates an exemplary cross-sectional view of an integrated circuit (IC) incorporating devices constructed according to the principles of the present invention; and [0021] FIGURE 13 illustrates another exemplary cross- sectional view of an integrated circuit (IC) incorporating devices constructed according to the principles of the present invention, where the top portion of the poly gate electrode is silicided to form a self-aligned suicide contact. DETAILED DESCRIPTION
[0022] Referring initially to FIGURE 1, illustrated is a cross-sectional view of one embodiment of a semiconductor device 100 constructed according to the principles of the present invention. In the embodiment illustrated in FIGURE 1, the semiconductor device 100 includes a substrate 110. Located within the substrate 110 in the embodiment of FIGURE 1 is a well region 120. Additionally located over the substrate 110 and well region 120 is a gate structure 130.
[0023] The gate structure 130 illustrated in FIGURE 1 includes a gate oxide 140 located over the substrate 110, as well as a silicided gate electrode 150 located over the gate oxide 140. While the silicided gate electrode is illustrated in FIGURE 1 as a fully silicided gate electrode, those skilled in the art understand that the silicided gate electrode 150 could also comprise a partially silicided gate electrode where only the top portion of the electrode is silicided. This embodiment might be used if there was a need to reduce the contact resistance of the silicided gate electrode 150. [0024] The silicided gate electrode 150 may have a variety of thicknesses, nonetheless, a thickness ranging from about 50 nm to about 150 nm is exemplary. The silicided gate electrode 150, when constructed in accordance with the principles of the present invention, may comprise a number of different materials. For instance, in the illustrative embodiment shown in FIGURE 1 the silicided gate electrode 150 comprises nickel, however, it is envisioned that the silicided gate electrode 150 could comprise cobalt, platinum, titanium, tantalum, molybdenum, tungsten, etc., while staying within the scope of the present invention .
[0025] The silicided gate electrode 150 may also include a dopant or combination of several types of dopants therein. The dopant, such as boron, phosphorous, arsenic or another similar dopant based on whether the semiconductor device 100 is operating as a PMOS device or an NMOS device, is configured to tune the minimum energy required to bring an electron from the Fermi level to the vacuum level, or the so called work function. [0026] The gate structure 130 further contains gate sidewall spacers 160 flanking both sides of the silicided gate electrode 150 and gate oxide 140. The gate sidewall spacers 160 in the embodiment of FIGURE 1 each include a number of different layers. For instance the gate sidewall spacers 160, among other layers, each include L-shaped nitride spacers 163 and sidewall oxides 168. In this particular embodiment the L-shaped nitride spacers 163 comprise a unique nitride layer that includes carbon. The carbon content may be within a wide range, however, it is believed that a carbon content ranging from about 5% to about 10% is advantageous. The other layers, among other materials, could include a collection of oxides and nitrides. The gate sidewall spacers 160 may comprise many different types and numbers of layers while staying consistent with the principles of the present invention.
[0027] The semiconductor device 100 illustrated in FIGURE 1 additionally includes conventional source/drain regions 170 located within the substrate 110 and proximate the gate oxide 140. Located within the source/drain regions 170 are blocking layers 180. The blocking layers 180 in the embodiment of FIGURE 1 function both as a protectant from the silicidation material used to form the silicided gate electrode 150, as well as source/drain contact regions.
[0028] The blocking layers 180, when manufactured in accordance with the principles of the present invention, comprise a metal suicide. In one embodiment, the blocking layers 180 comprise a metal suicide different from the metal suicide of the silicided gate electrode 150, however, in another embodiment they comprise a metal suicide the same as the metal suicide of the silicided gate electrode 150. As the silicided gate electrode 150 in the embodiment of FIGURE 1 comprise nickel suicide, the blocking layers 180 comprise a different metal suicide. In this particular embodiment the blocking layers 180 comprise cobalt suicide. Nonetheless, other silicidation materials (e.g., nickel, platinum, titanium, tantalum, molybdenum, tungsten, etc.) could be used to form the blocking layers 180 and remain within the scope of the present invention. The blocking layers 180 may have a depth into the source/drain regions 170 ranging from about 10 nm to about 35 nm, among others. This depth needs to be sufficient to prevent the silicidation metal used to form the silicided gate electrode 150 from affecting the source/drain regions 170, however, small enough to be consistent with the design of the present invention .
[0029] Turning now to FIGURES 2-11, illustrated are cross- sectional views of detailed manufacturing steps instructing how one might, in an advantageous embodiment, manufacture a semiconductor device similar to the semiconductor device 100 depicted in FIGURE 1. FIGURE 2 illustrates a cross-sectional view of a partially completed semiconductor device 200 manufactured in accordance with the principles of the present invention. The partially completed semiconductor device 200 of FIGURE 2 includes a substrate 210. The substrate 210 may, in an exemplary embodiment, be any layer located in the partially completed semiconductor device 200, including a wafer itself or a layer located above the wafer (e.g., epitaxial layer). In the embodiment illustrated in FIGURE 2, the substrate 210 is a P- type substrate; however, one skilled in the art understands that the substrate 210 could be an N-type substrate without departing from the scope of the present invention. In such a case, each of the dopant types described throughout the remainder of this document would be reversed. For clarity, no further reference to this opposite scheme will be discussed. [0030] Located within the substrate 210 in the embodiment shown in FIGURE 2 is a well region 220. The well region 220, in light of the P-type semiconductor substrate 210, would more than likely contain an N-type dopant. For example, the well region 220 would likely be doped with an N-type dopant dose ranging from about 1E13 atoms/cm2 to about 1E14 atoms/cm2 and at an energy ranging from about 100 keV to about 500 keV. This results in the well region 220 having a peak dopant concentration ranging from about 5E17 atoms/cm3 to about 1E19 atoms/cm3.
[0031] Located over the substrate 210 in the embodiment of FIGURE 2 is a gate structure 230. The gate structure 230 includes a gate oxide 240 and a polysilicon gate electrode 250. The gate oxide 240 may comprise a number of different materials and stay within the scope of the present invention. For example, the gate oxide 240 may comprise silicon dioxide, or in an alternative embodiment comprise a high dielectric constant (K) material. In the illustrative embodiment of FIGURE 2, however, the gate oxide 240 is a silicon dioxide layer having a thickness ranging from about 0.5 nm to about 5 nm. [0032] Any one of a plurality of manufacturing techniques could be used to form the gate oxide 240. For example, the gate oxide 240 may be either grown or deposited. Additionally, the growth or deposition steps may require a significant number of different temperatures, pressures, gasses, flow rates, etc. [0033] While the advantageous embodiment of FIGURE 2 dictates that the polysilicon gate electrode 250 comprise standard polysilicon, other embodiments exist where the polysilicon gate electrode, or at least a portion thereof, comprises amorphous polysilicon. The amorphous polysilicon embodiment may be particularly useful when a substantially planar upper surface of the polysilicon gate electrode 250 is desired. [0034] The deposition conditions for the polysilicon gate electrode 250 may vary, however, if the polysilicon gate electrode 250 were to comprise standard polysilicon, such as the instance in FIGURE 2, the polysilicon gate electrode 250 could be deposited using a pressure ranging from about 100 torr to about 300 torr, a temperature ranging from about 620EC to about 700EC, and a SiH4 or Si2He gas flow ranging from about 50 seem to about 150 seem. If, however, amorphous polysilicon were desired, the amorphous polysilicon gate electrode could be deposited using a pressure ranging from about 100 torr to about 300 torr, a temperature ranging from about 450EC to about 550EC, and a SiH4 or Si2H6 gas flow ranging from about 100 seem to about 300 seem. In any instance, the polysilicon gate electrode 250 desirably has a thickness ranging from about 50 nm to about 150 nm.
[0035] The partially completed semiconductor device 200 illustrated in FIGURE 2 further includes a protective layer 260 located over the polysilicon gate electrode 250. The protective layer 260, which may comprise silicon nitride among other materials, may have a thickness ranging from about 5 nm to about 50 nm. It is desirable for the protective layer 260 to have a thickness small enough to allow a dopant to easily penetrate therethrough, however, large enough to provide the sufficient amount of protection to the polysilicon gate electrode 250. [0036] Optionally located over the protective layer 260 is a silicon dioxide layer 270. The optional silicon dioxide layer 270 is designed to help pattern the gate oxide 240, polysilicon gate electrode 250 and protective layer 260. With that said, those skilled in the art understand that the gate oxide 240, polysilicon gate electrode 250, protective layer 260 and optional silicon dioxide layer 270 were originally blanket deposited. Those blanket layers were subsequently patterned resulting in the gate oxide 240, polysilicon gate electrode 250, protective layer 260 and optional silicon dioxide layer 270 illustrated in FIGURE 2. In one embodiment, the polysilicon gate electrode 250 and protective layer 260 are formed using a chemical vapor deposition (CVD) technique.
[0037] Turning briefly to FIGURE 3 illustrated is a cross- sectional view of the partially completed semiconductor device 200 illustrated in FIGURE 2 after formation of portions of gate sidewall spacers 310. The portions of the gate sidewall spacers 310 shown in FIGURE 3 include an oxide layer 320 and an offset nitride spacer 330. The oxide layer 320, as compared to similar layers used in the prior art, is formed at least partially using a deposition process. In an exemplary process the oxide layer 320 is initially formed using a first deposition process, and then finished using a second oxidation process. The first deposition process allows the oxide layer 320 to form on the top and sidewalls of the protective layer 260. In an alternative embodiment the entire oxide layer 320 is deposited. [0038] The offset nitride spacer 330 may comprise a standard silicon nitride spacer or a silicon nitride layer having carbon therein. If the offset nitride spacer 330 were to contain the carbon, the carbon might form from about 5% to about 10% of the layer. While the oxide layer 320 and the offset nitride spacer 330 are shown located only along the sides of the gate structure 230, those skilled in the art are aware that the layers were previously blanket formed and subsequently anisotropically etched to form the oxide layer 320 and the offset nitride spacer 330.
[0039] Turning now to FIGURE 4, illustrated is a cross- sectional view of the partially completed semiconductor device 200 illustrated in FIGURE 3 after formation of lightly doped extension implants 410 within the substrate 210. The lightly doped extension implants 410 are conventionally formed and generally have a peak dopant concentration ranging from about 1E19 atoms/cm3 to about 2E20 atoms/cm3. As is standard in the industry, the lightly doped extension implants 410 have a dopant type opposite to that of the well region 220 they are located within. Accordingly, the lightly doped extension implants 410 are doped with a P-type dopant in the illustrative embodiment shown in FIGURE 4. [0040] Turning now to FIGURE 5, illustrated is a cross- sectional view of the partially completed semiconductor device 200 illustrated in FIGURE 4 after forming the remaining portions of the gate sidewall spacers 310. Particularly, a cap oxide 510, L-shaped nitride spacers 520 and sidewall oxides 530 complete the gate sidewall spacers 310. The cap oxide 510, among other purposes, has the job of preventing the L-shaped nitride spacers 520 from directly contacting the substrate 210. Most likely, the cap oxide 510 will be deposited over the partially completed semiconductor device 200 using a process similar to that used to form the oxide layer 320. [0041] The L-shaped nitride spacers 520 may comprise any type of nitride, however, in an exemplary embodiment the L-shaped nitride spacers 520 comprise a nitride material that includes carbon. The carbon content, which may range from about 5% to about 10% of the L-shaped nitride spacers 520, is included within the L-shaped nitride spacers 520 to change the rate at which they etch. In the embodiment where the L-shaped nitride spacers 520 include carbon, the L-shaped nitride spacers 520 may be deposited using bis t-butylaminosilane (BTBAS) and ammonia (NH3) precursors in a CVD reactor. Advantageously, the carbon causes the L-shaped nitride spacers 520 to etch at a slower rate than a traditional nitride layer. In an exemplary situation, after having been annealed using a temperature ranging from about 1000EC to about 1100EC, the carbon causes the L-shaped nitride spacers 520 to have an etch selectivity of about 50:1 when compared to the traditional nitride layer. [0042] The sidewall oxides 530 that are located over the L- shaped nitride spacers 520 are conventional. In the given embodiment of FIGURE 5, the sidewall oxides 530 were blanket deposited and then subjected to an anisotropic etch. The resulting sidewall oxides 530 complete the gate sidewall spacers 310 illustrated in the embodiment of FIGURE 5. [0043] Turning now to FIGURE 6, illustrated is a cross- sectional view of the partially completed semiconductor device 200 illustrated in FIGURE 5 after etching the cap oxide 510 from the top of the substrate 210 and top of the protective layer 260, as well as after formation of highly doped source/drain implants 610 within the substrate 210. Those skilled in the art understand the conventional processes that could be used to etch the cap oxide 510.
[0044] The formation of the highly doped source/drain implants 610 is also conventional. Generally the highly doped source/drain implants 610 have a peak dopant concentration ranging from about 1E18 atoms/cm3 to about 1E21 atoms/cm3. Also, the highly doped source/drain implants 610 should typically have a dopant type opposite to that of the well region 220 they are located within. Accordingly, in the illustrative embodiment shown in FIGURE 6, the highly doped source/drain implants 610 are doped with a P-type dopant.
[0045] Turning now to FIGURE 7, illustrated is a cross- sectional view of the partially completed semiconductor device 200 illustrated in FIGURE 6 after subjecting the semiconductor device 200 to a standard source/drain anneal, thereby activating source/drain regions 710. It is believed that a source/drain anneal conducted at a temperature ranging from about 1000EC to about HOOEC and a time period ranging from about 1 second to about 5 seconds would be sufficient. It should be noted that other temperatures, times, and processes could be used to activate the source/drain regions 710. [0046] Additionally illustrated in FIGURE 7 is the formation of a silicidation metal 720 over the exposed portions of the source/drain regions 710 as well as over the gate structure 230. The silicidation metal 720 in the embodiment shown in FIGURE 7 happens to be a thin cobalt layer, however, other materials that react with silicon to form a suicide could easily be used. For instance it is known that the silicidation metal 720 may also comprise nickel, platinum, titanium, tantalum, molybdenum, tungsten, another similar metal, or any combination thereof while staying within the scope of the present invention. In the embodiment of FIGURE 7, the silicidation metal 720 comprises a different metal than the silicidation metal 1010 (FIGURE 10) . Nonetheless, this is not required to remain within the scope of the present invention.
[0047] The silicidation metal 720 may be formed using a number of different processes, and may be formed to a number of different thicknesses. In one embodiment of the invention the silicidation metal 720 is deposited to a thickness ranging from about 3 nm to about 10 nm. Such thicknesses, however, might be used when the silicidation metal 720 comprises cobalt. Various other thicknesses could be used if the silicidation metal 720 were to comprise one of the different metals disclosed above. [0048] Turning now to FIGURE 8, illustrated is a cross- sectional view of the partially completed semiconductor device 200 illustrated in FIGURE 7 after subjecting it to a rapid thermal anneal (RTA) . This RTA attempts to cause the silicidation metal 720 to react with the silicon of the source/drain regions 710 to form blocking layers 810. In the instance where the silicidation metal 720 comprises cobalt, the RTA causes the cobalt to react with the silicon to form a cobalt suicide . [0049] The RTA may be conducted using a variety of different temperatures and times. Nonetheless, it is believed that the RTA, in an exemplary embodiment, should be conducted in a rapid thermal processing tool at a temperature ranging from about 400EC to about 600EC for a time period ranging from about 5 seconds to about 60 seconds. The specific temperature and time period are typically based, however, on the ability to form the blocking layers 810 to a desired depth, as well as the suicide materials selected.
[0050] A selective wet etch, using for example a mixture of sulfuric acid (H2S04) , hydrogen peroxide (H202) and water (H20) , may then be used to remove un-reacted silicidation metal 720 on regions other than exposed silicon, such as on sidewall and gate. Additionally, another optional RTA step may be used to form a low resistivity phase of the suicide. In the case of using cobalt silicidation metal, the first RTA forms CoSi, while the optional RTA forms CoSi2, which has lower resistivity and is more stable. This optional RTA step is typically performed using a temperature ranging from about 650EC to about 800EC for a time period ranging from about 5 to about 60 seconds. [0051] Turning now to FIGURE 9, illustrated is a cross- sectional view of the partially completed semiconductor device 200 illustrated in FIGURE 8 after removing the protective layer 260 from over the polysilicon gate electrode 250 to form an opening 910. Unique to the present invention, the etchant used to remove the protective layer 260 does not substantially affect other structures or films. More specifically, the hot phosphoric acid etchant used to remove the protective layer 260 does not affect the L-shaped nitride spacer 520 and blocking layers 810. Even though the protective layer 260 and the L- shaped nitride spacer 520 both comprise silicon nitride, the carbon content of the L-shaped nitride spacer 520 provides substantial protection from the etchant. [0052] Turning now to FIGURE 10, illustrated is a cross- sectional view of the partially completed semiconductor device 200 illustrated in FIGURE 9 after depositing a second silicidation metal 1010 over the exposed portions of the polysilicon gate electrode 250, as well as over the remainder of the semiconductor device 200. In a preferred embodiment, the silicidation metal 1010 is designed to fully silicidize the polysilicon gate electrode 250. As it takes approximately 1 nm of nickel to fully silicidize approximately 1.8 nm of polysilicon, the thickness of the silicidation metal 1010 should be at least 56% of the thickness of the polysilicon gate electrode 250. To be comfortable, however, it is suggested that the thickness of the silicidation metal 1010 should be at least 60% of the thickness of the polysilicon gate electrode 250. Thus, where the thickness of the polysilicon gate electrode 250 ranges from about 50 nm to about 150 nm, as described above, the thickness of the silicidation metal 1010 should range from approximately 30 nm to about 90 nm. It should also be noted that the silicidation metal 1010 may comprise a number of different metals or combinations of metals while staying within the scope of the present invention. For example, the silicidation metal 1010 may comprise any metal known to react with polysilicon to form a metal suicide.
[0053] In an alternative embodiment of the invention, a thinner layer of silicidation metal 1010 may be formed over the exposed portions of the polysilicon gate electrode 250, as well as over the remainder of the semiconductor device 200. In this instance, the thinner layer of silicidation metal 1010 will only react with the top portion of the polysilicon gate electrode 250, to form a partially silicided gate electrode. The thickness of the thinner layer of silicidation metal 1010 could range from about 3 nm to about 15 nm to only partially suicide the silicided gate electrode. This embodiment is particularly useful for applications where a poly-gate oxide interface is used, rather than a silicide-gate oxide interface, as is the case in the fully silicided gate electrode discussed directly above . [0054] Turning now to FIGURE 11, illustrated is the partially completed semiconductor device 200 illustrated in FIGURE 10 after converting the polysilicon gate electrode 250 to a silicided gate electrode 1110. Those skilled in the art understand the steps that might be required to form the silicided gate electrode 1110, including subjecting the polysilicon gate electrode 250 and metal suicide layer 1010 to another RTA. This RTA is designed to convert the polysilicon gate electrode 250 to the silicided gate electrode 1110. The annealing temperature depends on the suicide metal being used. For example, it is believed that the RTA may be conducted at a temperature ranging from about 350EC to about 550EC and a time period ranging from about 10 second to about 100 seconds to accomplish the silicidation when nickel is used. It should be noted that other temperatures, times, and processes could be used if another metal were used. In a preferred embodiment, the silicidation metal 1010 fully silicidizes the polysilicon gate electrode 250. The suicide, however, does not form on the source/drain region 710 at this time because of the blocking layers 810.
[0054] After completing the silicided gate electrode 1110, the partially completed semiconductor device 200 may be subjected to a selective removal process. For instance, in one embodiment of the invention the device could be subjected to an etch recipe consisting of sulfuric acid (H2S04) , hydrogen peroxide (H202) and water (H20) . This specific etch recipe has a high degree of selectivity and could easily remove any remaining portions of the silicidation metal 1010. Thereafter the manufacture of the partially completed semiconductor device 200 would continue in a conventional manner, optimally resulting in a device similar to the semiconductor device 100 illustrated in FIGURE 1. It should be noted that the exact order of the steps illustrated with respect to FIGURES 2-11 may change depending on the process flow. Additionally, various other steps could be added to the description of FIGURES 2-11. [0055] The method of manufacturing the semiconductor device as discussed with respect to FIGURES 2-11 provides many benefits over the prior art methods. First, and possibly most important, it separates the formation of the silicided gate electrode and blocking layers (e.g., silicided source/drain contact regions) into different steps. Advantageously, this allows the depth of the blocking layers (e.g., silicided source/drain contact regions) to be independent of the thickness of the silicided gate electrode. The decoupling of the two steps is achieved by taking advantage of the chemical selectivity of thin films to certain etch chemistries. Accordingly, CMP is not needed as it is in the prior art methods capable of decoupling the steps. As such, the method of the present invention is applicable to devices having different step heights, whether by design or process variation. The CMP technique of the prior art is not capable of accepting such variations in step heights. [0056] Additionally, the method of the present invention allows the blocking layers to also function as the silicided source/drain regions. Accordingly, the present invention requires less processing steps than the prior art options. Further, the method of the present invention allows the semiconductor device to easily choose different silicidation metals for the suicide gate electrode and blocking layers (e.g., silicided source/drain regions). In the embodiment discussed above, the silicided gate electrode benefits from using nickel as the silicidation material. The nickel, at least as compared to cobalt, allows the sheet resistance of the silicided gate electrode to remain small as the gate length continues to increase. Similarly, the blocking layers benefit from using cobalt as the silicidation material. The cobalt, at least as compared to nickel, reduces piping defect issues in the source/drain regions. Thus the embodiment of the method discussed with respect to FIGURE 2-11 makes the best use of both nickel and cobalt. It is believed that the other metals would have similar advantages. [0057] Referring now to FIGURE 12, illustrated is an exemplary cross-sectional view of an integrated circuit (IC) 1200 incorporating devices 1210 constructed according to the principles of the present invention. The IC 1200 may include devices, such as transistors used to form CMOS devices, BiCMOS devices, Bipolar devices, as well as capacitors or other types of devices. The IC 1200 may further include passive devices, such as inductors or resistors, or it may also include optical devices or optoelectronic devices. Those skilled in the art are familiar with these various types of devices and their manufacture. In the particular embodiment illustrated in FIGURE 12, the IC 1200 includes the devices 1210 having dielectric layers 1220 located thereover. Additionally, interconnect structures 1230 are located within the dielectric layers 1220 to interconnect various devices, thus, forming the operational integrated circuit 1200. [0058] Referring finally to FIGURE 13, illustrated is another exemplary cross-sectional view of an integrated circuit (IC) 1300 incorporating devices 1310 constructed according to the principles of the present invention. In the particular embodiment illustrated in FIGURE 13, the IC 1300 includes devices 1310 having a gate electrode that is only partially silicided. The partially silicided gate electrode is desirable to reduce contact resistance of the poly electrode while keeping the poly-gate oxide interface without a silicide forming at the interface. Located over the devices 1310 are dielectric layers 1320. Additionally, interconnect structures 1330 are located within the dielectric layers 1320 to interconnect various devices, thus, forming the operational integrated circuit 1300.

Claims

CLAIMS :
1. A method for manufacturing a semiconductor device, comprising: forming a polysilicon gate electrode over a substrate; forming source/drain regions in said substrate proximate said polysilicon gate electrode; forming a blocking layer over said source/drain regions, said blocking layer comprising a metal silicide; suiciding said polysilicon gate electrode to form a silicided gate electrode.
2. The method as recited in Claim 1 wherein said forming a blocking layer occurs prior to said suiciding said polysilicon gate electrode.
3. The method as recited in Claim 1 wherein said blocking layer is a silicided source/drain contact region. . The method as recited in Claim 1 wherein said silicided gate electrode comprises a different metal silicide than said blocking layer.
5. The method as recited in Claim 4 wherein said blocking layer comprises a cobalt silicide and said silicided gate electrode comprises a nickel silicide.
6. The method as recited in Claim 1 wherein said blocking layer has a thickness ranging from about 10 nm to about 35 nm.
7. The method as recited in Claim 1 further including forming a protective layer over said polysilicon gate electrode prior to said forming a blocking layer over said source/drain regions .
8. The method as recited in Claim 7 wherein said protective layer is a silicon nitride protective layer.
9. The method as recited in Claim 1 wherein suiciding said polysilicon gate electrode to form a silicided gate electrode includes fully suiciding said polysilicon gate electrode to form a fully silicided gate electrode.
10. A method for manufacturing an integrated circuit, comprising: forming semiconductor devices over a substrate, including; forming a polysilicon gate electrode over a substrate; forming source/drain regions in said substrate proximate said polysilicon gate electrode; forming a blocking layer over said source/drain regions, said blocking layer comprising a metal silicide; suiciding said polysilicon gate electrode to form a silicided gate electrode; and forming interconnects within dielectric layers located over said substrate for electrically contacting said semiconductor devices .
11. The method as recited in Claim 10 wherein said forming a blocking layer occurs prior to said suiciding said polysilicon gate electrode.
12. The method as recited in Claim 10 wherein said blocking layer is a silicided source/drain contact region.
13. The method as recited in Claim 10 wherein said silicided gate electrode comprises a different metal silicide than said blocking layer.
14. The method as recited in Claim 13 wherein said blocking layer comprises a cobalt silicide and said silicided gate electrode comprises a nickel silicide.
15. The method as recited in Claim 10 wherein said blocking layer has a thickness ranging from about 10 nm to about 35 nm.
16. The method as recited in Claim 10 further including forming a protective layer over said polysilicon gate electrode prior to said forming a blocking layer over said source/drain regions .
17. The method as recited in Claim 16 wherein said protective layer is a silicon nitride protective layer.
18. The method as recited in Claim 10 wherein suiciding said polysilicon gate electrode to form a silicided gate electrode includes fully suiciding said polysilicon gate electrode to form a fully silicided gate electrode.
PCT/US2005/010288 2004-03-26 2005-03-28 A method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same Ceased WO2005096366A1 (en)

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