WO2005093954A1

WO2005093954A1 - Device comprising a frequency divider

Info

Publication number: WO2005093954A1
Application number: PCT/IB2005/050925
Authority: WO
Inventors: Cicero S. Vaucher; Melania Apostolidou
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2004-03-29
Filing date: 2005-03-16
Publication date: 2005-10-06

Abstract

Frequency dividers (2) comprising a first transistor circuit (21) with four transistor pairs (31-34, 81-84), two gate pairs (31, 33, 81, 83) and two latch pairs (32, 34, 82, 84) and comprising a second transistor circuit (22) with two transistor pairs (35-36, 85-86) and comprising an impedance circuit (23) have a relatively low frequency reach. By replacing the prior art load resistors in the impedance circuit (23) by active load impedances comprising transistors (37-40, 87-90), the frequency reach of the frequency divider (2) is improved significantly. An impedance (41-44) coupled to the emitter of a transistor (37-40, 87-90) defines the operation frequency range of the frequency divider (2), and an impedance (45-48) coupled to the basis of a transistor (37-40, 87-90) allows the frequency divider (2) to be tuned for maximum operation frequency.

Description

Device comprising a frequency divider

The invention relates to a device comprising a frequency divider, and also relates to a phase locked loop comprising a frequency divider, and to a frequency divider. Examples of such a device are transmitters, receivers and transceivers, such as satellite transmitters, satellite receivers and car-radar transceivers.

A prior art device comprises a first transistor stage coupled via a load resistor to a voltage supply, and a second transistor stage for controlling parts of the first transistor stage. The second transistor stage receives an input signal to be frequency divided, and the first transistor stage generates an output signal, directly, or indirectly via the load resistor. The known device is disadvantageous, inter alia, owing to the fact that it has a relatively low frequency reach.

It is an object of the invention, inter alia, to provide a device comprising a frequency divider having a relatively high frequency reach. Furthers objects of the invention are, inter alia, to provide a phase locked loop comprising a frequency divider and to provide a frequency divider having a relatively high frequency reach. The device according to the invention comprises a frequency divider, which frequency divider comprises: a first transistor circuit coupled to an impedance circuit and coupled to an output of the frequency divider; a second transistor circuit coupled to the first transistor circuit and coupled to an input of the frequency divider; which impedance circuit comprises a transistor. By providing the impedance circuit with an active load impedance in the form of a transistor, the prior art load resistor is replaced or represented by the transistor. A control electrode and a first main electrode of this transistor are for example coupled to a reference terminal and a second main electrode of this transistor is for example coupled to the first transistor circuit. As a result, the frequency reach of the frequency divider is improved significantly. Either at least the maximum frequency of the input signal which can still be divided is increased, or at least the operation frequency range of the frequency divider is increased. Summarising, the insufficient frequency behaviour of the prior art frequency divider is improved. The fact that the transistor replaces or represents the prior art load resistor requires a little more chip surface and introduces a little more noise, but this noise is of minor importance in the device or in the phase locked loop. Further, these disadvantages are neglectable compared to the advantage of the increased frequency reach. An embodiment of the device according to the invention is defined by the first transistor circuit comprisings four transistor pairs and the second transistor circuit comprises two transistor pairs. This is a so-called balanced frequency divider having balanced inputs and balanced outputs. An embodiment of the device according to the invention is defined by, in the first transistor circuit, a first transistor pair being a first gate pair, a second transistor pair being a first latch pair, a third transistor pair being a second gate pair, and a fourth transistor pair being a second latch pair. In dependance of the input signal, either the first gate pair and the second latch pair are active, or the second gate pair and the first latch pair are active. An embodiment of the device according to the invention is defined by, in the first transistor circuit, second main electrodes of each transistor pair being coupled to each other and to a first main electrode of one of the transistors of the transistor pairs of the second transistor circuit, with first main electrodes of the transistors of the first gate pair being coupled to control electrodes of the transistors of the second gate pair and to control electrodes and first main electrodes of the transistors of the first latch pair, and with first main electrodes of the transistors of the second gate pair being coupled to control electrodes of the transistors of the first gate pair and to control electrodes and first main electrodes of the transistors of the second latch pair. In this case, the output signal may be retrieved from the first main electrodes of the second gate pair, possibly via emitter followers. An embodiment of the device according to the invention is defined by the impedance circuit comprising a transistor per transistor of the gate pairs. In this case, the impedance circuit comprises four transistors. An embodiment of the device according to the invention is defined by a second control electrode of the transistor in the impedance circuit being coupled to the first transistor circuit via a first impedance. This first impedance, such as for example a first resistor, defines the operation frequency range of the frequency divider: for larger values of this first impedance, the operation frequency range will increase, and the maximum frequency of the input signal which can still be divided will decrease. An embodiment of the device according to the invention is defined by a control electrode of the transistor in the impedance circuit being coupled to a reference terminal via a second impedance. T iis second impedance, such as for example a second resistor, allows the frequency divider to be tuned. An embodiment of the device according to the invention is defined by a first main electrode of the transistor in the impedance circuit being coupled to a reference terminal via a third impedance. This third impedance, such as for example a third resistor, allows the output signal to be retrieved from this third impedance, possibly via emitter followers, without disturbing the signals at the first main electrodes of the second gate pair. Embodiments of the phase locked loop according to the invention and of the frequency divider according to the invention correspond with the embodiments of the device according to the invention. The invention is based upon an insight, inter alia, that prior art frequency dividers show an insufficient frequency behaviour, and is based upon a basic idea, inter alia, that the load resistor is to be replaced or represented by an active load impedance in the form of a transistor in the impedance circuit. The invention solves the problem, inter alia, to provide a device comprising a frequency divider having a relatively high frequency reach, and is advantageous, inter alia, in that either at least the operation frequency range of the frequency divider is increased, or at least the maximum frequency of the input signal which can still be divided is increased. These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments(s) described hereinafter.

In the drawings: Fig. 1 shows in block diagram form a device according to the invention comprising a frequency divider according to the invention; Fig. 2 shows in block diagram form a frequency divider according to the invention in greater detail; Fig. 3 shows in block diagram form a phase locked loop according to the invention comprising a frequency divider according to the invention; Fig. 4 shows in block diagram form an other frequency divider according to the invention in greater detail; Fig. 5 shows the minimum input power versus input frequency characteristics for two prior art frequency dividers and a frequency divider according to the invention; and Fig. 6 shows the minimum input power versus input frequency characteristics for two frequency dividers according to the invention comprising different impedances.

The device 1 according to the invention shown in Fig. 1, such as for example a transmitter, a receiver or a transceiver, such as a satellite transmitter, a satellite receiver and a car-radar transceiver, comprises a frequency divider 2 according to the invention located between an input stage 3 and an output stage 4. The input stage 3 provides an input signal to the input 26 of the frequency divider 2, which input signal is to be frequency divided, and the output stage 4 receives an output signal from the output 27 of the frequency divider 2, which output signal has been frequency divided. The frequency divider 2 comprises an impedance circuit 23 coupled to a first transistor 21. The first transistor circuit 21 is coupled via an level shifting circuit 25 to the output 27, and is coupled to a second transistor circuit 22. The second transistor circuit 22 is coupled to the input 26 and is coupled to a biasing circuit 24, which is further coupled to the level shifting circuit 25. The frequency divider 2 according to the invention shown in Fig. 2 in greater detail discloses the transistor circuits 21,22 and the impedance circuit 23. The impedance circuit 23 comprises four transistors 37-40 of which the control electrodes (basis) are coupled via impedances 45-48 such as for example resistors to a reference terminal 53. The first main electrodes (collectors) are coupled via impedances 49-52 such as for example resistors to the reference terminal 53. The second main electrodes (emitters) are coupled via impedances 41- 44 such as for example resistors to two transistors pairs 31,33 also called gate pairs. The first transistor circuit 21 comprises the two gate pairs 31 ,33 and comprises two further transistor pairs 32,34 also called latch pairs. Of each transistor pair 31-34, the second main electrodes (emitters) are coupled to each other. The first main electrodes (collectors) of the transistors of a first gate pair 31 are coupled to the control electrodes (basis) of the transistors of a second gate pair 33 and to the control electrodes (basis) and the first main electrodes (collectors) of the transistors of a first latch pair 32. The first main electrodes (collectors) of the transistors of the second gate pair 33 are coupled to the control electrodes (basis) of the transistors of the first gate pair 31 and to the control electrodes (basis) and the first main electrodes (collectors) of the transistors of a second latch pair 34. The first main electrodes (collectors) of the second gate pair 33 are coupled to output electrodes 55, which are further coupled to the level shifting circuit 25. The second transistor circuit 22 comprises two transistor pairs 35-36 of which the second main electrodes (emitters) per pair 35-36 are coupled to each other. The first main electrode (collector) of a first transistor of a first transistor pair 35 is coupled to the second main electrode (emitter) of the first gate pair 31. The control electrode (basis) of this first transistor of the first transistor pair 35 is coupled to a first input electrode 54. The first main electrode (collector) of a second transistor of the first transistor pair 35 is coupled to the , second main electrode (emitter) of the second gate pair 33. The control electrode (basis) of this second transistor of the first transistor pair 35 is coupled to a second input electrode 54. The first main electrode (collector) of a first transistor of a second transistor pair 36 is coupled to the second main electrode (emitter) of the first latch pair 32. The control electrode (basis) of this first transistor of the second transistor pair 36 is coupled to the second input electrode 54. The first main electrode (collector) of a second transistor of the second transistor pair 36 is coupled to the second main electrode (emitter) of the second latch pair 34. The control electrode (basis) of this second transistor of the second transistor pair 36 is coupled to the first input electrode 54. Both input electrodes 54 are coupled to the input 26. The second main electrodes of both transistor pairs 35-36 are coupled to electrodes 56,57, which are further coupled to the biasing circuit 24. The phase locked loop 6 according to the invention as shown in Fig. 3 comprises the frequency divider 2 according to the invention. The input 26 of the frequency divider 2 is coupled to an output of a voltage controlled oscillator 64. The output 27 of the frequency divider 2 is coupled to an input of a programmable divider 65, of which an output is coupled to a first input of a phase detector 62, of which a second input is coupled to an oscillator 61. An output of the phase detector 62 is coupled to an input of a filter 63, of which an output is coupled to an input of the voltage controlled oscillator 64. The output of the voltage controlled oscillator 64 is further coupled to a first input of a mixer 71 of a receiver 7. A second input of this mixer 71 receives a radio frequency signal 72 and an output of the mixer 71 generates an intermediate frequency signal 73. The operation of the device 1, of the frequency divider 2 and of the phase locked loop 6 is common in the art. In a prior art situation, the impedance circuit 23 comprises, instead of the elements 37-52, four prior art load resistors coupled to the reference terminal 53 and to the first main electrodes of the transistors of the gate pairs 31,33. This prior art frequency divider has a relatively low frequency reach. By introducing the transistors 37-40, the frequency reach of the frequency divider 2 according to the invention is improved significantly. Either at least the maximum frequency of the input signal which can still be divided is increased, or at least the operation frequency range of the frequency divider 2 is increased. The four transistor pairs 31 -34 and the two transistor pairs 35-36 are necessary in case the frequency divider 2 must be fully balanced. Of course, a similar solution for the impedance circuit 23 can be used in case of the frequency divider not needing to be balanced. In the balanced situation, generally, a positive input signal at the first input electrode 54 (together with a negative or zero input signal at the second input electrode 54) makes the first gate pair 31 and the second latch pair 34 active, and a positive input signal at the second input electrode 54 (together with a negative or zero input signal at the first input electrode 54) makes the second gate pair 33 and the first latch pair 32 active. Instead of bipolar NPN transistors, other kinds of transistors may be used, such as bipolar PNP transistors, or Field Effect Transistors, MOS transistors etc. An other way of looking at the frequency divider 2 as shown in Fig. 2 is as follows. In case of a vertical line being drawn in the middle of Fig. 2, all elements at the left side together form a first D-latch, and all elements at the right side form a second D-latch. The outputs of the first D-latch (the collectors of the first gate pair 31) are coupled to the inputs of the second D-latch (the basis of the second gate pair 33). The inputs of the first D- latch (the basis of the first gate pair 31) are coupled to the outputs of the second D-latch (the collectors of the second gate pair 33). The transistor pairs 35,36 of the D-latches receive a clock frequency signal. As a result, the combination of both D-latches divide a frequency of their clock frequency signal by a factor "two". An other frequency divider 2 according to the invention as shown in Fig. 4 in greater detail discloses the transistor circuits 21 ',22' and the impedance circuit 23'. These circuits 21', 22' and 23' correspond with the circuits 21, 22 and 23 as shown in Fig. 2, apart from the fact that MOS transistor pairs 81-86 and MOS transistors 87-90 have been used. The impedance 41-44, such as for example a resistor, defines the operation frequency range of the frequency divider 2: for larger values of this impedance 41-44, the operation frequency range will increase, and the maximum frequency of the input signal which can still be divided will decrease, and vice versa. The impedance 45-48, such as for example a resistor, allows the frequency divider 2 to be tuned. This can be derived from calculating the input impedance when looking via the impedance 41-44 to the transistor 37- 40. Its control electrode is coupled via the impedance 45-48 to the reference terminal 53 and its first main electrode is coupled directly to this reference terminal 53. Then, a Z.„ = f(Req,L_eq,Ceq) can be defined. The result clearly shows the influence of the external impedances 41-48 on the resistive, capacitive and inductive parts of the active load impedance. The impedance 49-52, such as for example a resistor, allows the output signal to be retrieved from this impedance 49-52, for example via the level shifting circuit 25, to prevent disturbing the signals at the first main electrodes of the second gate pair 33. The biasing circuit 24 for example comprises two current sources, each for example realised via a transistor with a resistor coupled to its second main electrode (emitter), for generating a gate pair current and a latch pair current. Then, the first main electrodes (collectors) of these transistors are coupled to the electrodes 56,57, and the control electrodes (basis) of these transistors receive current adjustment signals. The level shifting circuit 25 for example comprises two emitter followers realised via two transistors of which the control electrodes (basis) are coupled to the output electrodes 55. Such emitter followers reduce the load at the first main electrodes of the second gate pair 33 (or reduce the load across the impedances 49-52), and take care of level shifting. The first main electrodes

(collectors) of these transistors are coupled to the reference terminal 53 and the second main electrodes (emitters) of these transistors are coupled to the first main electrodes (collectors) of two biasing transistors of the biasing circuit 24. The control electrodes (basis) of these biasing transistors are coupled to each other for receiving a biasing signal, and the second main electrodes (emitters) of these biasing transistors are coupled to resistors. All resistors of the biasing circuit 24 are coupled to ground. Again, instead of bipolar NPN transistors, other kinds of transistors may be used, such as bipolar PNP transistors, or Field Effect Transistors, MOS transistors etc. So, two elements coupled to each other may be coupled directly to each other without a third element being in between, but may also be coupled indirectly to each other, with a third element being in between. Of course, a frequency divider 2 may comprise more than one section (in serial), to increase the divisor, with each section comprising the circuits 21-23 as shown in Fig. 2. With the active load impedance, the frequency divider 2 according to the invention may divide signals having a frequency up to 40 or 50 Ghz for a transition frequency fr being 70 GHz (bipolar process parameter). Fig. 5 shows the minimum input power versus input frequency characteristics for two prior art frequency dividers and a frequency divider according to the invention. The two prior art frequency dividers reach 21 GHz (QUBiC4 process) and 32 GHZ (QUBiC4G process). The frequency divider according to the invention reaches 38 GHz (QUBiC4G process with an active load). Fig. 6 shows the minimum input power versus input frequency characteristics for two frequency dividers according to the invention comprising different impedances Rlf. When increasing the value for the impedance 41-44 (Rlf in Fig. 6) from 50 Ohm to 100 Ohm, a operation frequency range from 3-37 GHz is reduced to 20-40 GHz, with the maximum frequency of the input signal to be divided obviously having increased from 37 GHz to 40 GHz. For a fixed value of the impedance 41-44, the active load impedance usually increases, compared to the prior art load resistor, the maximum frequency of the input signal to be divided as well as the operation frequency range of the frequency divider 2. This is a great advantage. It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. Use of the verb "to comprise" and its conjugations does not exclude the presence of elements or steps other than those stated in a claim. The article "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. In the device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:

1. Device (1) comprising a frequency divider (2), which frequency divider (2) comprises: a first transistor circuit (21) coupled to an impedance circuit (23) and coupled to an output (27) of the frequency divider (2); - a second transistor circuit (22) coupled to the first transistor circuit (21) and coupled to an input (26) of the frequency divider (2); which impedance circuit (23) comprises a transistor (37-40, 87-90).

2. Device (1) according to claim 1, wherein the first transistor circuit (21) comprises four transistor pairs (31 -34, 81 -84) and the second transistor circuit (22) comprises two transistor pairs (35-36, 85-86).

3. Device (1) according to claim 2, wherein, in the first transistor circuit (21), a first transistor pair (31,81) is a first gate pair, a second transistor pair (32,82) is a first latch pair, a third transistor pair (33,83) is a second gate pair, and a fourth transistor pair (34,84) is a second latch pair.

4. Device (1) according to claim 3, wherein, in the first transistor circuit (21), second main electrodes of each transistor pair (31-34, 81-84) are coupled to each other and to a first main electrode of one of the transistors of the transistor pairs (35-36, 85-86) of the second transistor circuit (22), with first main electrodes of the transistors of the first gate pair (31,81) being coupled to control electrodes of the transistors of the second gate pair (33,83) and to control electrodes and first main electrodes of the transistors of the first latch pair (32,82), and with first main electrodes of the transistors of the second gate pair (33,83) being coupled to control electrodes of the transistors of the first gate pair (31,81) and to control electrodes and first main electrodes of the transistors of the second latch pair (34,84).

5. Device (1) according to claim 4, wherein the impedance circuit (23) comprises atransistor (37-40, 87-90) per transistor of the gate pairs (31,33,81,83).

6. Device (1) according to claim 1, wherein a second control electrode of the transistor (37-40, 87-90) in the impedance circuit is coupled to the first transistor circuit (21) via a first impedance (41-44).

7. Device (1) according to claim 1, wherein a control electrode of the transistor (37-40, 87-90) in the impedance circuit (23) is coupled to a reference terminal (53) via a second impedance (45-48).

8. Device (1) according to claim 1, wherein a first main electrode of the transistor (37-40, 87-90) in the impedance circuit (23) is coupled to a reference terminal (53) via a third impedance (49-52).

9. Phase Locked Loop (6) comprising a frequency divider (2), which frequency divider (2) comprises: a first transistor circuit (21) coupled to an impedance circuit (23) and coupled to an output (27) of the frequency divider (2); a second transistor circuit (22) coupled to the first transistor circuit (21) and coupled to an iput (26) of the frequency divider (2); which impedance circuit (23) comprises a transistor (37-40, 87-90).

10. Frequency divider (2) comprising: a first transistor circuit (21) coupled to an impedance circuit (23) and coupled to an output (27) of the frequency divider (2); - a second transistor circuit (22) coupled to the first transistor circuit (21) and coupled to an input (26) of the frequency divider (2); which impedance circuit (23) comprises a transistor (37-40, 87-90).