WO2005093822A1 - Method for the epitaxial deposition of an si-based material on a layer of si-based material belonging to a semiconductor-on-insulator-type substrate - Google Patents

Method for the epitaxial deposition of an si-based material on a layer of si-based material belonging to a semiconductor-on-insulator-type substrate Download PDF

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WO2005093822A1
WO2005093822A1 PCT/FR2005/050183 FR2005050183W WO2005093822A1 WO 2005093822 A1 WO2005093822 A1 WO 2005093822A1 FR 2005050183 W FR2005050183 W FR 2005050183W WO 2005093822 A1 WO2005093822 A1 WO 2005093822A1
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silicon
substrate
layer
equal
based layer
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PCT/FR2005/050183
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French (fr)
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Jean-Michel Hartmann
Olivier Faynot
Carine Jahan
Lucie Tosti
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Commissariat A L'energie Atomique
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure

Definitions

  • the present invention relates to a process for the deposition by epitaxy of a silicon-based material on a layer of a silicon-based material of a substrate of the semiconductor on insulator type.
  • silicon on insulator substrates (known under the abbreviation SOI for silicon on insulator) are more and more often used as a support for the development of MOS transistors.
  • Silicon germanium substrates on insulator are beginning to appear.
  • a conventional SOI substrate consists of a solid silicon base covered with a layer of insulating material (generally silicon oxide), itself covered with a thin layer of silicon.
  • Such substrates make it possible to produce components with very fine source / drain junctions and to obtain low threshold voltages with low leakage currents in low voltage and low power integrated circuits used for applications of portable electronic devices for example . They also allow, among other things, to reduce the parasitic source / drain capacities for high-performance microwave components that consume more energy and have circuits that can operate at high temperature and are resistant to radiation. In the microelectronics industry, the tendency is to miniaturize the components in all dimensions, which will require in the short term to start from semiconductor substrates on ultra thin insulation of which the layers of semiconductor material and insulation are many thinner than those currently used. In commercial SOI substrates, the thickness of the silicon layer is approximately 200 nanometers and that of the silicon oxide layer is approximately 400 nanometers.
  • the thickness of the silicon layer will be less than about 10 nanometers, that of the silicon oxide layer will be less than about 100 nanometers.
  • the material deposited by epitaxy is of the same nature as that of the surface layer. This is the case for locally producing the drain and source zones of an MOS transistor. In other cases, a material of a different nature will be grown (for example Si on SiGe or the reverse).
  • FIGS. 1A, 1B show two known steps for producing an MOS transistor on an ultra-thin SOI 10 substrate.
  • the insulation layer generally silicon oxide
  • BOX the acronym standing for Buried OXide.
  • the solid silicon layer is not shown opposite to the insulating layer 1 with respect to the surface silicon layer 2.
  • an insulation trench 3 has been made intended to isolate the MOS transistor of a neighboring component formed on the same substrate 10.
  • This isolation trench 3 known by the English acronym STI of Shallo Trench Isolation or shallow isolation trench 3 is intended to be filled with material insulating. It reaches the insulating layer 1.
  • the SOI substrate 10 is partly covered with an insulating layer 5 (silicon oxide Si0 2 for insulation), in particular at the place where the grid 4 will be located. of the transistor.
  • This grid 4 generally made of polycrystalline silicon, is flanked by lateral spacers 6 made of insulating material, for example made of silicon nitride Si 3 N 4 .
  • the thickness of silicon 2 under the grid 4 is only about 10 nanometers.
  • windows 7 have been opened in the insulation layer 5, on either side of the gate 4, in which we will selectively deposit with respect to silicon oxide or silicon nitride, a monocrystalline semiconductor material, for example silicon or a silicon-germanium mixture.
  • the opening of the windows 7 is carried out by selective dry etching with stopping on the insulation layer 5, then chemical removal of this insulation layer 5 of silicon oxide at the level of the windows 7.
  • the insulation layer 5 in silicon oxide located in the stack of the grid 4 is not attacked because protected by the polycrystalline silicon of the grid 4. During this step, there may be consumption of a few angstroms or even a few nanometers (typically no more 2 nanometers) of silicon at the level of the windows 7.
  • the deposition by epitaxy takes place in the vapor phase, it is selective, that is to say that it takes place only on the semiconductor material of the surface layer 2 which is bare, it is not done on the insulating material of the spacers 6 or on the insulation layer 5 for example.
  • Document [1] describes a standard process for deposition by epitaxy in the gas phase of silicon on an SOI substrate. We start by carrying out a treatment to prepare the surface of the area to be covered in a wet bench, outside the deposition reactor
  • the last three steps of this preparation treatment consist in immersing the substrate in a hydrofluoric acid bath diluted in deionized water at about 23 ° C for a few minutes, rinsing it in deionized and deoxygenated water and then dry it with isopropyl alcohol.
  • This treatment is known by the Anglo-Saxon name "HF-last”.
  • This surface preparation is followed by the deposition step by gas phase epitaxy. This step has two phases.
  • the first phase is an annealing phase in the deposition reactor (in-situ) in the presence of hydrogen, at a temperature of approximately 800 ° C. for approximately 2 minutes at a pressure of 2.666 10 3 Pa.
  • the second phase is a silicon growth phase in the deposition reactor (in situ) in the presence of a mixture of dichlorosilane SiH 2 Cl 2 , hydrochloric acid HC1 and molecular hydrogen H 2 as carrier gas, at temperatures typically of the order of 800 ° C.
  • the surface silicon layer 2 intended to receive the deposit may have a thickness of less than approximately 8 nanometers while it may have a thickness of more than approximately 10 nanometers under the grid 4.
  • the deposited silicon may reach several tens of nanometers. We can speak of an elevated silicon drain and source. The result obtained is not at all satisfactory.
  • Figure 1B The overall silicon layer including the surface layer 2 of silicon and the silicon which has just been deposited bears the reference 8.
  • FIG. 2A which show the effect of the annealing step, for approximately 2 minutes, at a pressure of 2,666.10 3 Pa and at temperatures of 800 ° C and 950 ° C respectively, on the layer of ultra-fine surface silicon (of the order of 8 nanometers) of an SOI substrate.
  • FIG. 2A a withdrawal 11 from the surface silicon layer 2, at the edge of delimited zones and adjoining the insulating material 21.
  • FIG. 2B in addition to the withdrawal, an agglomeration in islands 9 of the layer of silicon has occurred.
  • the object of the present invention is precisely to propose a process for the deposition by epitaxy of a silicon-based semiconductor material on a silicon-based layer of a substrate of semiconductor type on ultrathin insulator which does not not have the disadvantages mentioned above.
  • An object is in particular to propose such a method which makes it possible to obtain a continuous, homogeneous layer of semiconductor material, substantially without shrinkage or agglomerated islands.
  • the invention relates more precisely to a method of epitaxy deposition of a silicon-based material on a silicon-based layer of a semiconductor-type substrate on an ultra-thin insulator, comprising an annealing phase of the substrate followed by a phase of growth of the silicon-based material, characterized in that the annealing phase takes place at an annealing temperature substantially lower than or equal to 700 ° C. if the silicon-based layer of the substrate is delimited and at an annealing temperature substantially lower than or equal to 800 ° C. if the silicon-based layer of the substrate is full plate, the growth phase taking place, at least at the start, at a growth temperature substantially lower than or equal to 750 ° C.
  • the silicon-based layer of the substrate is defined and at a growth temperature substantially lower than or equal to 775 ° C. if the silicon-based layer of the substrate is pl niepid plaque.
  • the fact that the silicon-based layer of the substrate is delimited means that the silicon-based material covers an area smaller than that of the substrate. This stems from the fact that either it is masked by insulation, or that locally it has been removed, possibly revealing the insulation.
  • the silicon-based layer to receive the deposit is full plate when its surface area corresponds to that of the substrate.
  • the annealing phase can be carried out in the presence of hydrogen and / or nitrogen.
  • the silicon-based material which is deposited is either silicon or silicon-germanium.
  • the material of the substrate layer is either silicon or silicon-germanium.
  • the growth temperature can be substantially less than or equal to 750 ° C. as long as the assembly formed of the layer based on silicon and the deposited material has a thickness substantially less than or equal to ten nanometers. It can be substantially less than or equal to 800 ° C. as soon as said thickness is substantially greater. We can thus benefit from growth rates compatible with industrial processes, while maintaining a relatively reduced thermal budget.
  • the silicon-based material which is deposited is silicon-germanium and the silicon-based layer of the substrate is delimited, the growth temperature can be substantially constant and substantially less than or equal to 700 ° C.
  • the growth temperature can be substantially less than or equal to 775 ° C. as long as the assembly formed of the layer based on silicon and on the deposited material has a thickness substantially less than or equal to ten nanometers. It can be significantly lower or equal to 800 ° C. as soon as said thickness is substantially greater.
  • the growth temperature can be substantially constant and substantially less than or equal to 750 ° C.
  • the substrate of the semiconductor on insulator type may be a silicon on insulator substrate, a strained silicon on insulator substrate or a silicon-germanium on insulator substrate.
  • the growth phase can use chlorinated chemistry, for example based on SiH 2 Cl 2 + GeH 4 + HCl + H 2 if it is desired to deposit silicon or silicon-germanium locally.
  • it can use hydrogenated chemistry based on SiH 4 + GeH 4 + H 2 if it is only desired to re-thicken a full plate substrate.
  • FIGS. 1A, 1B show a substrate of the type SOI on which we are preparing to deposit a semiconductor material based on silicon and the substrate obtained after the deposition by a process of the prior art
  • Figures 2A, 2B are photos showing the defects of a silicon layer obtained after deposition by the method of the prior art
  • Figures 3A, 3B are views showing a silicon layer obtained after deposition by the method of the invention
  • Figures 3C, 3D are sections of the substrate obtained after deposition by the method of the invention when the surface layer of the substrate is delimited or full plate
  • FIGS. 1A, 1B show a substrate of the type SOI on which we are preparing to deposit a semiconductor material based on silicon and the substrate obtained after the deposition by a process of the prior art
  • Figures 2A, 2B are photos showing the defects of a silicon layer obtained after deposition by the method of the prior art
  • Figures 3A, 3B are views showing a silicon layer obtained after deposition by the method of the invention
  • FIGS. 4A to 4D are views showing a layer of silicon obtained by the method according to the invention as a function of the thickness of the surface layer of silicon of the substrate before deposition.
  • Identical, similar or equivalent parts of the different figures described below have the same reference numerals so as to facilitate the passage from one figure to another.
  • the different parts shown in the figures are not necessarily shown on a uniform scale, to make the figures more readable.
  • semiconductor type substrate on ultrathin insulation is meant a substrate whose layer of semiconductor material has a thickness substantially less than or equal to 10 nanometers. We assumes that the surface silicon layer is delimited and that it is masked by insulation.
  • the method could also be applied to other types of substrate of semiconductor on insulator type such as substrates of silicon constrained on insulator (known under the acronym of sSOI for strained Silicon On Insulator), substrates silicon-germanium on insulator (SiGe-On-Insulator) which are substrates having a layer of insulator covered with a layer of SiGe almost completely relaxed which one seeks to thicken or cover with a layer of silicon in tension .
  • the layer of silicon-based material on which the deposit will be made could be full plate.
  • the deposition process according to the invention comprises, as in the prior art, a surface preparation step.
  • This surface preparation can be conventional wet type and on this subject, we can refer to what has been described above or to document [4] which describes the process known under the name "HF-last". Other types of surface preparation would be possible.
  • This surface preparation step is followed by the deposition step by epitaxy proper in situ. This deposit step breaks down into two phases as in the prior art. We start with an annealing phase and continue with a growth phase.
  • the annealing phase is carried out under a gaseous atmosphere, for example based on hydrogen and / or nitrogen at a pressure of the order of 2,666.10 3 Pa and lasts for a few minutes (for example 2 minutes). This phase takes place at a lower temperature than that usually used.
  • the annealing temperature is substantially less than or equal to 700 ° C. for an ultrathin SOI substrate (or more generally a semiconductor type substrate on ultrathin insulator) whose surface silicon layer (based on surface silicon) is delimited as the deposition of either silicon or silicon-germanium.
  • FIGS. 3A, 3B show the effect of this annealing on the one hand at a temperature of 700 ° C.
  • FIGS 3C, 3D show in the manner of Figure 1B, the appearance of the deposit according to the invention carried out on a substrate of the semiconductor type on ultrathin insulator 10, the silicon-based layer of which is delimited or full plate respectively .
  • the same references as in Figure 1B have been used.
  • the technological steps implemented subsequently are the implantation of dopants (for example As, B, Ph) which make the deposited layer amorphous , recrystallization annealing and electrical activation of dopants. It is therefore preferable to reduce the temperature during annealing so as to avoid shrinkage and agglomeration during deposition.
  • dopants for example As, B, Ph
  • the growth phase of the silicon-based semiconductor material Si or SiGe will also take place at a lower temperature than in the prior art.
  • This growth can take place in chlorinated chemistry, that is to say in the presence of chlorosilane (generally dichlorosilane SiH 2 Cl 2 ) and optionally hydrochloric acid HCl which makes it possible to increase the selectivity of the deposit with respect to the zones of silicon oxide or of silicon nitride.
  • chlorosilane generally dichlorosilane SiH 2 Cl 2
  • optionally hydrochloric acid HCl which makes it possible to increase the selectivity of the deposit with respect to the zones of silicon oxide or of silicon nitride.
  • germane GeH 4 is used in addition.
  • the growth temperature at least initially, is substantially less than or equal to 750 ° C.
  • the growth rate is very low, on the order of a nanometer per minute.
  • a total thickness of silicon of the order of ten nanometers has been reached, to increase the growth temperature to accelerate the speed and make it more compatible with an industrial process. It can then be substantially less than or equal to 800 ° C. By working at a temperature of the order of 750 ° C., one can reach a growth rate of the order of 2 nanometers per minute. If the deposit is SiGe, and in particular for high concentrations of Ge (typically greater than or equal to 10%), a low growth temperature can be kept substantially less than or equal to 700 ° C., throughout the growth phase until 'until the desired thickness is reached.
  • FIG. 4A to 4C show the morphology of a silicon layer 70 to 75 nanometers thick deposited on four samples of substrates I am ultra-thin.
  • the thickness of the surface silicon of the SOI substrate before the deposition is worth 9 nanometers, it is worth 7 nanometers in FIG. 4B, 6 nanometers in FIG. 4C and only 4.5 nanometers in FIG. 4D.
  • the annealing step took place at 650 ° C. for two minutes in the presence of hydrogen, at a pressure of 2,666.10 3 Pa.
  • the growth step was carried out in the presence of dichlorosilane and hydrochloric acid.
  • the temperature was worth 700 ° C during the deposition of the first 8 nanometers approximately of silicon, then 750 ° C during the growth of the rest of the layer (approximately 60 to 65 nanometers). It is noted that for the samples of FIGS. 4A to 4C for which the thickness of the surface silicon layer of the substrate before deposition is less than or equal to 6 nanometers, neither shrinkage nor agglomeration of the silicon is observed. In fact the annealing temperature and that of growth are a function of the thickness of the silicon-based layer of the substrate before deposition. In microelectronics, during the deposition of thin layers, it is usual to consider the deposition time and therefore the yield as one of the key parameters of the process.
  • the constraints with regard to temperatures are less drastic.
  • Annealing will take place at a temperature substantially lower than or equal to 800 ° C.
  • it can be done in chlorinated chemistry in the presence or not of germane depending on the material to be deposited.
  • the growth temperature will be substantially less than or equal to 750 ° C at least as long as the silicon-based layer has not reached about ten nanometers.
  • Si deposition to accelerate the growth rate, it is then possible to increase the growth temperature so that it is substantially less than or equal to 800 ° C.
  • deposition of SiGe, and in particular for high concentrations of Ge for example of the order of 10% and more
  • it is possible to keep a low growth temperature for example substantially less than or equal to 700 ° C., throughout the growth phase until the desired thickness is reached.

Abstract

The invention relates to a method for the epitaxial deposition of a silicon-based material on a silicon-based layer belonging to an ultrathin semiconductor-on-insulator-type substrate. The inventive method consists of a phase comprising the annealing of the substrate, followed by a phase comprising the growth of the silicon-based material. The annealing phase is performed at an annealing temperature that is essentially less than or equal to 700 °C if the silicon-based layer of the substrate is delimited or at an annealing temperature that is essentially less than or equal to 800 °C if the silicon-based layer of the substrate comprises a whole wafer. Moreover, the growth phase is performed, at least at the start, at a growth temperature that is essentially less than or equal to 750 °C if the silicon-based layer of the substrate is delimited or at a growth temperature that is essentially less than or equal to 775 °C if the silicon-based layer of the substrate comprises a whole wafer. The invention is suitable for the production of electronic components.

Description

PROCEDE DE DEPOT PAR EPITAXIE D'UN MATERIAU A BASE DE Si SUR UNE COUCHE DE MATERIAU A BASE DE Si D'UN SUBSTRAT DE TYPE SEMI-CONDUCTEUR SUR ISOLANT METHOD FOR THE EPITAXY DEPOSITION OF A MATERIAL BASED ON Si ON A LAYER OF MATERIAL BASED ON Si OF A SUBSTRATE OF SEMICONDUCTOR TYPE ON INSULATOR
DESCRIPTIONDESCRIPTION
DOMAINE TECHNIQUE La présente invention est relative à un procédé de dépôt par épitaxie d'un matériau à base de silicium sur une couche d'un matériau à base de silicium d'un substrat de type semi-conducteur sur isolant . Dans l'industrie de la micro-électronique, des substrats de silicium sur isolant (connus sous l'abréviation SOI pour silicon on insulator) sont de plus en plus souvent utilisés comme support pour l'élaboration de transistors MOS . Les substrats de silicium-germanium sur isolant commencent à faire leur apparition. Un substrat SOI conventionnel se compose d'une base en silicium massif recouverte d'une couche en matériau isolant (généralement de l'oxyde de silicium), elle même recouverte d'une couche mince de silicium. De tels substrats permettent de réaliser des composants à jonctions source/drain très fins et d' obtenir des tensions de seuil faibles avec des courants de fuite bas dans des circuits intégrés faibles tensions et faibles puissances utilisés pour des applications d'appareils électroniques portables par exemple. Ils permettent également entre autre de réduire les capacités source/drain parasites pour des composants hyperfréquences très performants mais plus gourmands en énergie et de disposer de circuits pouvant opérer à haute température et résistants aux radiations . Dans l' industrie de la microélectronique, la tendance est de miniaturiser les composants dans toutes les dimensions, ce qui nécessitera à court terme de partir de substrats semi-conducteur sur isolant ultraminces dont les couches de matériau semi- conducteur et d' isolant sont beaucoup plus minces que celles employées actuellement. Dans les substrats SOI du commerce, l'épaisseur de la couche de silicium vaut environ 200 nanomètres et celle de la couche d'oxyde de silicium vaut environ 400 nanomètres. A court terme, l'épaisseur de couche de silicium sera inférieure à environ 10 nanomètres, celle de la couche d'oxyde de silicium sera inférieure à environ 100 nanomètres. Dans certaines applications, il est intéressant d'épaissir par épitaxie la couche superficielle du substrat. Le matériau déposé par épitaxie est de même nature que celui de la couche superficielle. C'est le cas pour réaliser localement les zones de drain et de source d'un transistor MOS. Dans d'autres cas, on fera croître un matériau de nature différente (par exemple Si sur du SiGe ou 1' inverse) .TECHNICAL FIELD The present invention relates to a process for the deposition by epitaxy of a silicon-based material on a layer of a silicon-based material of a substrate of the semiconductor on insulator type. In the microelectronics industry, silicon on insulator substrates (known under the abbreviation SOI for silicon on insulator) are more and more often used as a support for the development of MOS transistors. Silicon germanium substrates on insulator are beginning to appear. A conventional SOI substrate consists of a solid silicon base covered with a layer of insulating material (generally silicon oxide), itself covered with a thin layer of silicon. Such substrates make it possible to produce components with very fine source / drain junctions and to obtain low threshold voltages with low leakage currents in low voltage and low power integrated circuits used for applications of portable electronic devices for example . They also allow, among other things, to reduce the parasitic source / drain capacities for high-performance microwave components that consume more energy and have circuits that can operate at high temperature and are resistant to radiation. In the microelectronics industry, the tendency is to miniaturize the components in all dimensions, which will require in the short term to start from semiconductor substrates on ultra thin insulation of which the layers of semiconductor material and insulation are many thinner than those currently used. In commercial SOI substrates, the thickness of the silicon layer is approximately 200 nanometers and that of the silicon oxide layer is approximately 400 nanometers. In the short term, the thickness of the silicon layer will be less than about 10 nanometers, that of the silicon oxide layer will be less than about 100 nanometers. In certain applications, it is advantageous to thicken the surface layer of the substrate by epitaxy. The material deposited by epitaxy is of the same nature as that of the surface layer. This is the case for locally producing the drain and source zones of an MOS transistor. In other cases, a material of a different nature will be grown (for example Si on SiGe or the reverse).
ÉTAT DE LA TECHNIQUE ANTÉRIEURE On a représenté sur les figures 1A, 1B deux étapes connues de réalisation d'un transistor MOS sur un substrat SOI 10 ultramince. La couche d'isolant (généralement de l'oxyde de silicium) est référencée 1, elle est enterrée sous la couche de silicium superficielle référencée 2 et est souvent dénommée BOX acronyme anglo-saxon de Buried OXide . La couche de silicium massif n'est pas représentée à l'opposé de la couche d' isolant 1 par rapport à la couche de silicium superficielle 2. Dans le substrat SOI 10, on a réalisé une tranchée d' isolation 3 destinée à isoler le transistor MOS d'un composant voisin formé sur le même substrat 10. Cette tranchée d'isolation 3 connue sous l'acronyme anglo-saxon STI de Shallo Trench Isolation soit tranchée d'isolation 3 peu profonde est destinée à être emplie à terme de matériau isolant . Elle atteint la couche d'isolant 1. Le substrat SOI 10 est recouvert pour partie d'une couche d'isolation 5 (oxyde de silicium Si02 d'isolation par exemple), notamment à l'endroit où va se trouver la grille 4 du transistor. Cette grille 4, généralement en silicium polycristallin, est flanquée d'espaceurs latéraux 6 en matériau isolant par exemple en nitrure de silicium Si3N4. L'épaisseur de silicium 2 sous la grille 4 n'est que d'environ 10 nanomètres. Pour réaliser la zone de drain et la zone de source du transistor, on a ouvert, dans la couche d'isolation 5, de part et d'autre de la grille 4, des fenêtres 7 dans lesquelles on va déposer, de manière sélective vis-à-vis de l'oxyde de silicium ou du nitrure de silicium, un matériau semi-conducteur monocristallin, par exemple du silicium ou un mélange silicium-germanium. L' ouverture des fenêtres 7 est réalisée par gravure sélective en voie sèche avec arrêt sur la couche d'isolation 5, puis retrait chimique de cette couche d'isolation 5 d'oxyde de silicium au niveau des fenêtres 7. La couche d'isolation 5 en oxyde de silicium située dans l'empilement de la grille 4 n'est pas attaquée car protégée par le silicium polycristallin de la grille 4. Lors de cette étape, il peut y avoir consommation de quelques angstrδms voire quelques nanomètres (typiquement pas plus de 2 nanomètres) du silicium au niveau des fenêtres 7. Le dépôt par épitaxie se fait en phase vapeur, il est sélectif, c'est-à-dire qu'il ne se fait que sur le matériau semi-conducteur de la couche superficielle 2 qui est à nu, il ne se fait pas sur le matériau isolant des espaceurs 6 ou sur la couche d'isolation 5 par exemple. Sur la figure 1A, les fenêtres 7 ont été ouvertes mais le dépôt n'est pas encore intervenu. Le document [1] dont les références sont précisées à la fin de la description décrit un procédé standard de dépôt par épitaxie en phase gazeuse de silicium sur un substrat SOI. On commence par réaliser un traitement de préparation de la surface de la zone à recouvrir dans une paillasse humide, en dehors du réacteur de dépôtSTATE OF THE PRIOR ART FIGS. 1A, 1B show two known steps for producing an MOS transistor on an ultra-thin SOI 10 substrate. The insulation layer (generally silicon oxide) is referenced 1, it is buried under the surface silicon layer referenced 2 and is often referred to as BOX, the acronym standing for Buried OXide. The solid silicon layer is not shown opposite to the insulating layer 1 with respect to the surface silicon layer 2. In the SOI substrate 10, an insulation trench 3 has been made intended to isolate the MOS transistor of a neighboring component formed on the same substrate 10. This isolation trench 3 known by the English acronym STI of Shallo Trench Isolation or shallow isolation trench 3 is intended to be filled with material insulating. It reaches the insulating layer 1. The SOI substrate 10 is partly covered with an insulating layer 5 (silicon oxide Si0 2 for insulation), in particular at the place where the grid 4 will be located. of the transistor. This grid 4, generally made of polycrystalline silicon, is flanked by lateral spacers 6 made of insulating material, for example made of silicon nitride Si 3 N 4 . The thickness of silicon 2 under the grid 4 is only about 10 nanometers. To make the drain zone and the source zone of the transistor, windows 7 have been opened in the insulation layer 5, on either side of the gate 4, in which we will selectively deposit with respect to silicon oxide or silicon nitride, a monocrystalline semiconductor material, for example silicon or a silicon-germanium mixture. The opening of the windows 7 is carried out by selective dry etching with stopping on the insulation layer 5, then chemical removal of this insulation layer 5 of silicon oxide at the level of the windows 7. The insulation layer 5 in silicon oxide located in the stack of the grid 4 is not attacked because protected by the polycrystalline silicon of the grid 4. During this step, there may be consumption of a few angstroms or even a few nanometers (typically no more 2 nanometers) of silicon at the level of the windows 7. The deposition by epitaxy takes place in the vapor phase, it is selective, that is to say that it takes place only on the semiconductor material of the surface layer 2 which is bare, it is not done on the insulating material of the spacers 6 or on the insulation layer 5 for example. In FIG. 1A, the windows 7 have been opened but the deposition has not yet taken place. Document [1], the references of which are specified at the end of the description, describes a standard process for deposition by epitaxy in the gas phase of silicon on an SOI substrate. We start by carrying out a treatment to prepare the surface of the area to be covered in a wet bench, outside the deposition reactor
(ex-situ) . Les trois dernières étapes de ce traitement de préparation consistent à immerger le substrat dans un bain d'acide fluorhydrique dilué dans de l'eau désionisee à environ 23°C pendant quelques minutes, à le rincer dans de l'eau désionisee et désoxygénée puis à le sécher à l'aide d'alcool isopropylique. Ce traitement est connu sous la dénomination anglo-saxonne « HF-last ». Cette préparation de surface est suivie de l'étape de dépôt par épitaxie en phase gazeuse. Cette étape comporte deux phases. La première phase est une phase de recuit dans le réacteur de dépôt (in-situ) en présence d'hydrogène, à une température d'environ 800 °C pendant environ 2 minutes à une pression de 2,666 103 Pa. La seconde phase est une phase de croissance du silicium dans le réacteur de dépôt (in- situ) en présence d'un mélange de dichlorosilane SiH2Cl2, d'acide chlorhydrique HC1 et d'hydrogène moléculaire H2 en tant que gaz porteur, à des températures typiquement de l'ordre de 800 °C. Avant croissance, la couche de silicium superficielle 2 devant accueillir le dépôt peut avoir une épaisseur inférieure à environ 8 nanomètres alors qu'elle peut avoir une épaisseur supérieure à environ 10 nanomètres sous la grille 4. Le silicium déposé peut atteindre plusieurs dizaines de nanomètres. On peut parler de drain et de source surélevés en silicium. Le résultat obtenu n'est pas du tout satisfaisant. On se réfère à la figure 1B. La couche de silicium globale incluant la couche superficielle 2 de silicium et le silicium qui vient d' être déposé porte la référence 8. Il s'est produit un retrait 11 du silicium 8 au niveau de l'isolant massif 1, c'est-à- dire au bord de la tranchée 3. Ce retrait 11 peut s'étendre sur plusieurs dizaine de nanomètres. Un autre défaut important observé est que la couche de silicium 8 perd sa continuité et il y a apparition d'îlots 9. Ce phénomène d'agglomération du silicium en îlots 9 a été mis en évidence dans les documents [2] et [3] dont les références se trouvent en fin de la présente description. Ce phénomène se produit à une température d' autant plus basse que la couche de silicium superficielle 2 est mince. On peut même se référer aux figures 2A, 2B qui montrent l'effet de l'étape de recuit, pendant environ 2 minutes, à une pression de 2,666.103 Pa et à des températures de 800°C et de 950°C respectivement, sur la couche de silicium superficielle ultrafine (de l'ordre de 8 nanomètres) d'un substrat SOI. On peut observer sur la figure 2A, un retrait 11 de la couche de silicium superficiel 2, en bord de zones délimitées et jouxtant du matériau isolant 21. Sur la figure 2B, en plus du retrait, une agglomération en îlots 9 de la couche de silicium s'est produite.(ex-situ). The last three steps of this preparation treatment consist in immersing the substrate in a hydrofluoric acid bath diluted in deionized water at about 23 ° C for a few minutes, rinsing it in deionized and deoxygenated water and then dry it with isopropyl alcohol. This treatment is known by the Anglo-Saxon name "HF-last". This surface preparation is followed by the deposition step by gas phase epitaxy. This step has two phases. The first phase is an annealing phase in the deposition reactor (in-situ) in the presence of hydrogen, at a temperature of approximately 800 ° C. for approximately 2 minutes at a pressure of 2.666 10 3 Pa. The second phase is a silicon growth phase in the deposition reactor (in situ) in the presence of a mixture of dichlorosilane SiH 2 Cl 2 , hydrochloric acid HC1 and molecular hydrogen H 2 as carrier gas, at temperatures typically of the order of 800 ° C. Before growth, the surface silicon layer 2 intended to receive the deposit may have a thickness of less than approximately 8 nanometers while it may have a thickness of more than approximately 10 nanometers under the grid 4. The deposited silicon may reach several tens of nanometers. We can speak of an elevated silicon drain and source. The result obtained is not at all satisfactory. We refer to Figure 1B. The overall silicon layer including the surface layer 2 of silicon and the silicon which has just been deposited bears the reference 8. There has been a shrinkage 11 of the silicon 8 at the level of the solid insulator 1, that is to say ie at the edge of the trench 3. This withdrawal 11 can extend over several ten nanometers. Another significant defect observed is that the silicon layer 8 loses its continuity and there is the appearance of islands 9. This phenomenon of agglomeration of silicon into islands 9 has been highlighted in documents [2] and [3] whose references are found at the end of this description. This phenomenon occurs at a temperature all the lower the thinner the surface layer of silicon 2. We can even refer to FIGS. 2A, 2B which show the effect of the annealing step, for approximately 2 minutes, at a pressure of 2,666.10 3 Pa and at temperatures of 800 ° C and 950 ° C respectively, on the layer of ultra-fine surface silicon (of the order of 8 nanometers) of an SOI substrate. One can observe in FIG. 2A, a withdrawal 11 from the surface silicon layer 2, at the edge of delimited zones and adjoining the insulating material 21. In FIG. 2B, in addition to the withdrawal, an agglomeration in islands 9 of the layer of silicon has occurred.
EXPOSÉ DE L'INVENTION La présente invention a justement comme but de proposer un procédé de dépôt par épitaxie d'un matériau semi-conducteur à base de silicium sur une couche à base de silicium d'un substrat de type semiconducteur sur isolant ultramince qui ne présente pas les inconvénients mentionnés ci-dessus. Un but est en particulier de proposer un tel procédé qui permette d' obtenir une couche de matériau semi-conducteur continue, homogène, sensiblement sans retrait ni îlots agglomérés. Pour atteindre ces buts l'invention concerne plus précisément un procédé de dépôt par épitaxie d' un matériau à base de silicium sur une couche à base de silicium d'un substrat de type semi- conducteur sur isolant ultramince, comprenant une phase de recuit du substrat suivie d'une phase de croissance du matériau à base de silicium, caractérisé en ce que la phase de recuit a lieu à une température de recuit sensiblement inférieure ou égale à 700 °C si la couche à base de silicium du substrat est délimitée et à une température de recuit sensiblement inférieure ou égale 800°C si la couche à base de silicium du substrat est pleine plaque, la phase de croissance se faisant, au moins au début, à une température de croissance sensiblement inférieure ou égale à 750°C si la couche à base de silicium du substrat est délimitée et à une température de croissance sensiblement inférieure ou égale à 775°C si la couche à base de silicium du substrat est pleine plaque. Le fait que la couche à base silicium du substrat soit délimitée signifie que le matériau à base de silicium couvre une superficie inférieure à celle du substrat . Cela provient du fait soit qu' il est masqué par de l'isolant, soit que localement il a été ôté, laissant éventuellement apparaître l'isolant. La couche à base de silicium devant recevoir le dépôt est pleine plaque lorsque sa superficie correspond à celle du substrat . La phase de recuit peut se faire en présence d'hydrogène et/ou d'azote. Le matériau à base de silicium que l'on dépose est soit du silicium ou soit du silicium- germanium. Le matériau de la couche du substrat est soit du silicium ou soit du silicium-germanium. Lorsque le matériau à base de silicium que l'on dépose est du silicium et que la couche à base de silicium du substrat est délimitée, la température de croissance peut être sensiblement inférieure ou égale à 750°C tant que l'ensemble formé de la couche à base de silicium et du matériau déposé a une épaisseur sensiblement inférieure ou égale à une dizaine de nanomètres. Elle peut être sensiblement inférieure ou égale à 800 °C dès que ladite épaisseur est sensiblement supérieure. On peut ainsi bénéficier de vitesses de croissance compatibles avec les procédés industriels, tout en conservant un budget thermique relativement réduit . Lorsque le matériau à base de silicium que l'on dépose est du silicium-germanium et que la couche à base de silicium du substrat est délimitée, la température de croissance peut être sensiblement constante et sensiblement inférieure ou égale à 700 °C. Lorsque le matériau à base de silicium que l'on dépose est du silicium et que la couche à base de silicium du substrat est pleine plaque, la température de croissance peut être sensiblement inférieure ou égale à 775°C tant que l'ensemble formé de la couche à base de silicium et du matériau déposé a une épaisseur sensiblement inférieure ou égale à une dizaine de nanomètres. Elle peut être sensiblement inférieure ou égale à 800°C dès que ladite épaisseur est sensiblement supérieure . Lorsque le matériau à base de silicium que l'on dépose est du silicium-germanium et que la couche à base de silicium du substrat est pleine plaque, la température de croissance peut être sensiblement constante et sensiblement inférieure ou égale à 750 °C. Le substrat de type semi-conducteur sur isolant peut être un substrat silicium sur isolant, un substrat silicium contraint sur isolant ou un substrat silicium-germanium sur isolant. • La phase de croissance peut utiliser une chimie chlorée par exemple à base de SiH2Cl2 + GeH4 + HCl + H2 si on désire déposer localement du silicium ou du silicium-germanium. En variante elle peut utiliser une chimie hydrogénée à base de SiH4 + GeH4 + H2 si on désire seulement ré-épaissir un substrat pleine plaque.PRESENTATION OF THE INVENTION The object of the present invention is precisely to propose a process for the deposition by epitaxy of a silicon-based semiconductor material on a silicon-based layer of a substrate of semiconductor type on ultrathin insulator which does not not have the disadvantages mentioned above. An object is in particular to propose such a method which makes it possible to obtain a continuous, homogeneous layer of semiconductor material, substantially without shrinkage or agglomerated islands. To achieve these aims, the invention relates more precisely to a method of epitaxy deposition of a silicon-based material on a silicon-based layer of a semiconductor-type substrate on an ultra-thin insulator, comprising an annealing phase of the substrate followed by a phase of growth of the silicon-based material, characterized in that the annealing phase takes place at an annealing temperature substantially lower than or equal to 700 ° C. if the silicon-based layer of the substrate is delimited and at an annealing temperature substantially lower than or equal to 800 ° C. if the silicon-based layer of the substrate is full plate, the growth phase taking place, at least at the start, at a growth temperature substantially lower than or equal to 750 ° C. if the silicon-based layer of the substrate is defined and at a growth temperature substantially lower than or equal to 775 ° C. if the silicon-based layer of the substrate is pl eine plaque. The fact that the silicon-based layer of the substrate is delimited means that the silicon-based material covers an area smaller than that of the substrate. This stems from the fact that either it is masked by insulation, or that locally it has been removed, possibly revealing the insulation. The silicon-based layer to receive the deposit is full plate when its surface area corresponds to that of the substrate. The annealing phase can be carried out in the presence of hydrogen and / or nitrogen. The silicon-based material which is deposited is either silicon or silicon-germanium. The material of the substrate layer is either silicon or silicon-germanium. When the silicon-based material which is deposited is silicon and the silicon-based layer of the substrate is delimited, the growth temperature can be substantially less than or equal to 750 ° C. as long as the assembly formed of the layer based on silicon and the deposited material has a thickness substantially less than or equal to ten nanometers. It can be substantially less than or equal to 800 ° C. as soon as said thickness is substantially greater. We can thus benefit from growth rates compatible with industrial processes, while maintaining a relatively reduced thermal budget. When the silicon-based material which is deposited is silicon-germanium and the silicon-based layer of the substrate is delimited, the growth temperature can be substantially constant and substantially less than or equal to 700 ° C. When the silicon-based material that is deposited is silicon and the silicon-based layer of the substrate is full plate, the growth temperature can be substantially less than or equal to 775 ° C. as long as the assembly formed of the layer based on silicon and on the deposited material has a thickness substantially less than or equal to ten nanometers. It can be significantly lower or equal to 800 ° C. as soon as said thickness is substantially greater. When the silicon-based material which is deposited is silicon-germanium and the silicon-based layer of the substrate is full plate, the growth temperature can be substantially constant and substantially less than or equal to 750 ° C. The substrate of the semiconductor on insulator type may be a silicon on insulator substrate, a strained silicon on insulator substrate or a silicon-germanium on insulator substrate. • The growth phase can use chlorinated chemistry, for example based on SiH 2 Cl 2 + GeH 4 + HCl + H 2 if it is desired to deposit silicon or silicon-germanium locally. As a variant, it can use hydrogenated chemistry based on SiH 4 + GeH 4 + H 2 if it is only desired to re-thicken a full plate substrate.
BRÈVE DESCRIPTION DES DESSINS La présente invention sera mieux comprise à la lecture de la description d' exemples de réalisation donnés, à titre purement indicatif et nullement limitatif, en faisant référence aux dessins annexés sur lesquels : les figures 1A, 1B montrent un substrat de type SOI sur lequel on s'apprête à réaliser un dépôt de matériau semi-conducteur à base de silicium et le substrat obtenu après le dépôt par un procédé de l'art antérieur ; les figures 2A, 2B sont des photos montrant les défauts d'une couche de silicium obtenue après le dépôt par le procédé de l'art antérieur ; les figures 3A, 3B sont des vues montrant une couche de silicium obtenue après le dépôt par le procédé de l'invention, les figures 3C, 3D sont des coupes du substrat obtenu après le dépôt par le procédé de l'invention lorsque la couche superficielle du substrat est délimitée ou pleine plaque ; les figures 4A à 4D sont des vues montrant une couche de silicium obtenue par le procédé selon l'invention en fonction de l'épaisseur de la couche superficielle en silicium du substrat avant le dépôt. Des parties identiques, similaires ou équivalentes des différentes figures décrites ci-après portent les mêmes références numériques de façon à faciliter le passage d'une figure à l'autre. Les différentes parties représentées sur les figures ne le sont pas nécessairement selon une échelle uniforme, pour rendre les figures plus lisibles .BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be better understood on reading the description of examples of embodiments given, purely by way of non-limiting indication, with reference to the appended drawings in which: FIGS. 1A, 1B show a substrate of the type SOI on which we are preparing to deposit a semiconductor material based on silicon and the substrate obtained after the deposition by a process of the prior art; Figures 2A, 2B are photos showing the defects of a silicon layer obtained after deposition by the method of the prior art; Figures 3A, 3B are views showing a silicon layer obtained after deposition by the method of the invention, Figures 3C, 3D are sections of the substrate obtained after deposition by the method of the invention when the surface layer of the substrate is delimited or full plate; FIGS. 4A to 4D are views showing a layer of silicon obtained by the method according to the invention as a function of the thickness of the surface layer of silicon of the substrate before deposition. Identical, similar or equivalent parts of the different figures described below have the same reference numerals so as to facilitate the passage from one figure to another. The different parts shown in the figures are not necessarily shown on a uniform scale, to make the figures more readable.
EXPOSÉ DÉTAILLÉ DE MODES DE RÉALISATION PARTICULIERSDETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
On va décrire le procédé de dépôt selon l'invention dans un exemple visant à épaissir la couche de silicium superficielle d'un substrat SOI ultramince. Par substrat de type semi-conducteur sur isolant ultramince on entend un substrat dont la couche de matériau semi-conducteur a une épaisseur sensiblement inférieure ou égale à 10 nanomètres. On suppose que la couche de silicium superficielle est délimitée et qu'elle est masquée par de l'isolant. Le procédé pourrait également s'appliquer à d'autres types de substrat de type semi-conducteur sur isolant tels que des substrats de silicium contraint sur isolant (connus sous l'acronyme anglo-saxon de sSOI pour strained Silicon On Insulator) , des substrats silicium-germanium sur isolant (SiGe-On-Insulator) qui sont des substrats ayant une couche d' isolant recouverte d'une couche de SiGe quasiment totalement relaxée que l'on cherche à épaissir ou à recouvrir d'une couche de silicium en tension. Au lieu d'être délimitée, la couche de matériau à base de silicium sur laquelle va se faire le dépôt pourrait être pleine plaque. En effet dans certaines applications comme les traénsistors partiellement désertés (Si en tension/SiGe sur isolant) , on cherche à épaissir la couche superficielle du substrat SOI ainsi qu' à diminuer sa rugosité de surface et sa dispersion macroscopique d'épaisseur. Le procédé de dépôt selon l'invention comporte comme dans l' art antérieur, une étape de préparation de surface. Cette préparation de surface peut être conventionnelle de type humide et à ce sujet, on peut se référer à ce qui a été décrit plus haut ou au document [4] qui décrit le procédé connu sous la dénomination « HF-last ». D'autres types de préparation de surface seraient possibles. Cette étape de préparation de surface est suivie de l'étape de dépôt par épitaxie proprement dite in-situ. Cette étape de dépôt se décompose en deux phases comme dans l'art antérieur. On débute par une phase de recuit et on poursuit par une phase de croissance. La phase de recuit se fait sous atmosphère gazeuse, par exemple à base d'hydrogène et/ou d'azote à une pression de l'ordre de 2,666.103 Pa et dure pendant quelques minutes (par exemple 2 minutes) . Cette phase a lieu à une température plus basse que celle utilisée habituellement . La température de recuit est sensiblement inférieure ou égale à 700°C pour un substrat SOI ultramince (ou plus généralement un substrat de type semi-conducteur sur isolant ultramince) dont la couche de silicium superficielle (à base de silicium superficielle) est délimitée que le dépôt soit du silicium ou du silicium-germanium. Les figures 3A, 3B montrent l'effet de ce recuit d'une part à une température de 700°C et d'autre part à une température de 650°C, sur la couche superficielle en silicium, d'un substrat SOI ultramince, délimitée par de l'isolant. Aucun phénomène de retrait n'est visible, il n'y a pas non plus bien sûr d'agglomération en îlots de la couche de silicium. Ce recuit à basse température est garant de la bonne tenue de la couche de silicium superficielle 2 du substrat que l'on cherche à recouvrir. Les figures 3C, 3D montrent à la manière de la figure 1B, l'aspect du dépôt selon l'invention effectué sur un substrat de type semi-conducteur sur isolant ultramince 10, dont la couche à base de silicium est délimitée ou pleine plaque respectivement. Les mêmes références que sur la figure 1B ont été employées . L' idée de réduire la température de recuit lors d'un dépôt par épitaxie va à l' encontre d'un avis largement répandu dans le domaine et expliqué dans le document [1] ainsi que dans les références numérotées 21 à 30 qu'il cite. Une température d'au moins 775°C doit être atteinte lors du recuit pour rendre la surface lisse et pour supprimer toute trace de contamination notamment en carbone, oxygène et fluor de la surface de silicium ayant subi la préparation de surface. Cela permet d'obtenir une très bonne qualité cristalline du matériau à croître et l'obtention de cette très bonne qualité apparaissait comme importante. Or il s'avère que cette parfaite qualité cristalline n'est pas indispensable car elle est remise en cause lors des traitements ultérieurs que va subir le substrat. C'est notamment le cas lorsque l'on réalise des zones de drains et de sources surélevées en Si. Les étapes technologiques mises en œuvre ultérieurement sont l'implantation de dopants (par exemple As, B, Ph) qui rendent la couche déposée amorphe, le recuit de recristallisation et l'activation électrique des dopants . Il est donc préférable de réduire la température lors du recuit de manière à éviter le retrait et l'agglomération lors du dépôt. La phase de croissance du matériau semiconducteur à base de silicium (Si ou SiGe) se fera également à une température plus basse que dans l'art antérieur. Cette croissance peut se faire, en chimie chlorée, c'est-à-dire en présence de chlorosilane (généralement du dichlorosilane SiH2Cl2) et éventuellement d' acide chlorhydrique HCl qui permet d' augmenter la sélectivité du dépôt par rapport aux zones d' oxyde de silicium ou de nitrure de silicium. Lors de la croissance de silicium-germanium, de la germane GeH4 est utilisée en plus. Dans le cas du substrat de type semi¬ conducteur sur isolant ultramince dont la couche superficielle à base de silicium est délimitée, la température de croissance, au moins au début, est sensiblement inférieure ou égale à 750 °C. Dans le cas du dépôt de Si, avec cette chimie chlorée, la vitesse de croissance est très faible de l'ordre du nanomètre à la minute. Il est alors préférable, une fois qu'une épaisseur totale de silicium de l'ordre de la dizaine de nanomètres a été atteinte, d'augmenter la température de croissance pour accélérer la vitesse et la rendre plus compatible avec un procédé industriel. Elle peut alors être sensiblement inférieure ou égale à 800 °C. En travaillant à une température de l'ordre de 750°C, on peut atteindre une vitesse de croissance l'ordre de 2 nanomètres par minute. Si le dépôt est du SiGe, et en particulier pour des fortes concentrations de Ge (typiquement supérieure ou égale à 10%) , on pourra conserver une température de croissance basse sensiblement inférieure ou égale à 700 °C, pendant toute la phase de croissance jusqu'à ce que l'épaisseur souhaitée soit atteinte. Les figures 4A à 4C montrent la morphologie d'une couche de silicium d'épaisseur de 70 à 75 nanomètres déposée sur quatre échantillons de substrats SOI ultraminces. Sur la figure 4A, l'épaisseur du silicium superficiel du substrat SOI avant le dépôt vaut 9 nanomètres, elle vaut 7 nanomètres sur la figure 4B, 6 nanomètres sur la figure 4C et seulement 4,5 nanomètres sur la figure 4D. L'étape de recuit a eu lieu à 650 °C pendant deux minutes en présence d'hydrogène, à une pression de 2,666.103 Pa. L'étape de croissance s'est faite en présence de dichlorosilane et d'acide chlorhydrique. La température valait 700 °C lors du dépôt des 8 premiers nanomètres environ de silicium, puis 750°C lors de la croissance du reste de la couche (environ 60 à 65 nanomètres) . On remarque que pour les échantillons des figures 4A à 4C pour lesquels l'épaisseur de la couche de silicium superficielle du substrat avant dépôt est inférieure ou égale à 6 nanomètres, on n'observe ni retrait, ni agglomération du silicium. En fait la température de recuit et celle de croissance sont fonction de l'épaisseur de la couche à base de silicium du substrat avant dépôt . En microélectronique, lors du dépôt de couches minces, il est habituel de considérer le temps de dépôt et donc le rendement comme étant l'un des paramètres clefs du procédé. On a donc tendance à vouloir réaliser la croissance à des températures plus élevées que celles mentionnées précédemment afin de pouvoir bénéficier de vitesses de croissance plus conséquentes (de l'ordre de quelques dizaines de nanomètres par minute) et de temps d'élaboration de la couche de quelques minutes seulement. Dans le procédé selon l' invention la vitesse de croissance ne vaut que quelques nanomètres par minute et le temps d'élaboration de la couche vaut quelques dizaines de minutes. En procédant ainsi on évite ainsi tout retrait et toute agglomération de la couche ce qui ne serait pas le cas avec des températures de croissance plus élevées. Sur des substrats SOI ultraminces la minimisation du budget thermique a la primeur sur le temps de croissance tant que l'épaisseur de la couche à base de silicium n'a pas dépassé la dizaine de nanomètres . Si la couche à base de silicium sur laquelle doit se faire le dépôt est pleine plaque (c'est-à-dire qu'elle a une superficie égale à celle du substrat), les contraintes en ce qui concerne les températures sont moins drastiques. Le passage d'un substrat de type semi-conducteur sur isolant dont le matériau semi-conducteur superficiel est délimité (et sur lequel la croissance ne peut se faire) à un substrat dont le matériau semi-conducteur superficiel est pleine plaque, augmente fortement, à même épaisseur de semi-conducteur superficiel, la température minimale pour laquelle le matériau semi-conducteur superficiel devient discontinu et s'agglomère en îlots. Le recuit se fera à une température sensiblement inférieure ou égale à 800 °C. En ce qui concerne l'étape de croissance, elle pourra se faire en chimie chlorée en présence ou non de germane selon le matériau à déposer. En variante, elle pourra se faire également en chimie hydrogénée, c'est à dire en présence de silane SiH4 et éventuellement de germane si du SiGe est à déposer. La température de croissance sera sensiblement inférieure ou égale à 750 °C au moins tant que la couche à base de silicium n'aura pas atteint une dizaine de nanomètres environ. En cas de dépôt de Si, pour accélérer la vitesse de croissance, il est alors possible d' augmenter la température de croissance de manière à ce qu'elle soit sensiblement inférieure ou égale à 800°C. Dans le cas de dépôt de SiGe, et en particulier pour des fortes concentrations de Ge (par exemple de l'ordre de 10% et plus), on pourra conserver une température de croissance basse par exemple sensiblement inférieure ou égale à 700 °C, pendant toute la phase de croissance jusqu'à ce que l'épaisseur souhaitée soit atteinte. Bien que plusieurs exemples de procédés selon la présente invention aient été décrits de façon détaillée, on comprendra que différents changements et modifications puissent être apportés sans sortir du cadre de l'invention. Il est bien sûr possible de modifier le contenu de l'étape de préparation de surface du substrat.The deposition process according to the invention will be described in an example aimed at thickening the surface silicon layer of an ultra-thin SOI substrate. By semiconductor type substrate on ultrathin insulation is meant a substrate whose layer of semiconductor material has a thickness substantially less than or equal to 10 nanometers. We assumes that the surface silicon layer is delimited and that it is masked by insulation. The method could also be applied to other types of substrate of semiconductor on insulator type such as substrates of silicon constrained on insulator (known under the acronym of sSOI for strained Silicon On Insulator), substrates silicon-germanium on insulator (SiGe-On-Insulator) which are substrates having a layer of insulator covered with a layer of SiGe almost completely relaxed which one seeks to thicken or cover with a layer of silicon in tension . Instead of being delimited, the layer of silicon-based material on which the deposit will be made could be full plate. In fact, in certain applications such as partially deserted traistoristors (Si in tension / SiGe on insulator), it is sought to thicken the surface layer of the SOI substrate as well as to reduce its surface roughness and its macroscopic thickness dispersion. The deposition process according to the invention comprises, as in the prior art, a surface preparation step. This surface preparation can be conventional wet type and on this subject, we can refer to what has been described above or to document [4] which describes the process known under the name "HF-last". Other types of surface preparation would be possible. This surface preparation step is followed by the deposition step by epitaxy proper in situ. This deposit step breaks down into two phases as in the prior art. We start with an annealing phase and continue with a growth phase. The annealing phase is carried out under a gaseous atmosphere, for example based on hydrogen and / or nitrogen at a pressure of the order of 2,666.10 3 Pa and lasts for a few minutes (for example 2 minutes). This phase takes place at a lower temperature than that usually used. The annealing temperature is substantially less than or equal to 700 ° C. for an ultrathin SOI substrate (or more generally a semiconductor type substrate on ultrathin insulator) whose surface silicon layer (based on surface silicon) is delimited as the deposition of either silicon or silicon-germanium. FIGS. 3A, 3B show the effect of this annealing on the one hand at a temperature of 700 ° C. and on the other hand at a temperature of 650 ° C., on the silicon surface layer, of an ultra-thin SOI substrate, delimited by insulation. No shrinkage phenomenon is visible, nor is there, of course, agglomeration in islands of the silicon layer. This low temperature annealing guarantees the good behavior of the surface silicon layer 2 of the substrate which it is sought to cover. Figures 3C, 3D show in the manner of Figure 1B, the appearance of the deposit according to the invention carried out on a substrate of the semiconductor type on ultrathin insulator 10, the silicon-based layer of which is delimited or full plate respectively . The same references as in Figure 1B have been used. The idea of reducing the annealing temperature during deposition by epitaxy goes against a widely held opinion in the field and explained in document [1] as well as in references numbered 21 to 30 that cites. A temperature of at least 775 ° C must be reached during annealing to make the surface smooth and to remove any trace of contamination, in particular carbon, oxygen and fluorine, from the silicon surface having undergone the surface preparation. This makes it possible to obtain a very good crystalline quality of the material to be grown and obtaining this very good quality appeared to be important. However, it turns out that this perfect crystalline quality is not essential because it is called into question during the subsequent treatments which the substrate will undergo. This is particularly the case when producing areas of drains and elevated sources of Si. The technological steps implemented subsequently are the implantation of dopants (for example As, B, Ph) which make the deposited layer amorphous , recrystallization annealing and electrical activation of dopants. It is therefore preferable to reduce the temperature during annealing so as to avoid shrinkage and agglomeration during deposition. The growth phase of the silicon-based semiconductor material (Si or SiGe) will also take place at a lower temperature than in the prior art. This growth can take place in chlorinated chemistry, that is to say in the presence of chlorosilane (generally dichlorosilane SiH 2 Cl 2 ) and optionally hydrochloric acid HCl which makes it possible to increase the selectivity of the deposit with respect to the zones of silicon oxide or of silicon nitride. During the growth of silicon-germanium, germane GeH 4 is used in addition. In the case of semi ¬ conductive type on ultrathin insulating substrate having a surface layer based on silicon is delimited, the growth temperature, at least initially, is substantially less than or equal to 750 ° C. In the case of the Si deposition, with this chlorinated chemistry, the growth rate is very low, on the order of a nanometer per minute. It is then preferable, once a total thickness of silicon of the order of ten nanometers has been reached, to increase the growth temperature to accelerate the speed and make it more compatible with an industrial process. It can then be substantially less than or equal to 800 ° C. By working at a temperature of the order of 750 ° C., one can reach a growth rate of the order of 2 nanometers per minute. If the deposit is SiGe, and in particular for high concentrations of Ge (typically greater than or equal to 10%), a low growth temperature can be kept substantially less than or equal to 700 ° C., throughout the growth phase until 'until the desired thickness is reached. FIGS. 4A to 4C show the morphology of a silicon layer 70 to 75 nanometers thick deposited on four samples of substrates I am ultra-thin. In FIG. 4A, the thickness of the surface silicon of the SOI substrate before the deposition is worth 9 nanometers, it is worth 7 nanometers in FIG. 4B, 6 nanometers in FIG. 4C and only 4.5 nanometers in FIG. 4D. The annealing step took place at 650 ° C. for two minutes in the presence of hydrogen, at a pressure of 2,666.10 3 Pa. The growth step was carried out in the presence of dichlorosilane and hydrochloric acid. The temperature was worth 700 ° C during the deposition of the first 8 nanometers approximately of silicon, then 750 ° C during the growth of the rest of the layer (approximately 60 to 65 nanometers). It is noted that for the samples of FIGS. 4A to 4C for which the thickness of the surface silicon layer of the substrate before deposition is less than or equal to 6 nanometers, neither shrinkage nor agglomeration of the silicon is observed. In fact the annealing temperature and that of growth are a function of the thickness of the silicon-based layer of the substrate before deposition. In microelectronics, during the deposition of thin layers, it is usual to consider the deposition time and therefore the yield as one of the key parameters of the process. There is therefore a tendency to want to carry out the growth at higher temperatures than those mentioned previously in order to be able to benefit from more substantial growth rates (of the order of a few tens of nanometers per minute) and of time for developing the layer. only a few minutes. In the process according to the invention the growth speed is only worth a few nanometers per minute and the time layer development is worth a few tens of minutes. By doing so, any shrinkage and agglomeration of the layer is avoided, which would not be the case with higher growth temperatures. On ultra-thin SOI substrates, the minimization of the thermal budget takes precedence over the growth time as long as the thickness of the silicon-based layer has not exceeded ten nanometers. If the silicon-based layer on which the deposit is to be made is full plate (that is to say that it has an area equal to that of the substrate), the constraints with regard to temperatures are less drastic. The transition from a substrate of the semiconductor on insulator type whose surface semiconductor material is delimited (and on which growth cannot take place) to a substrate whose surface semiconductor material is full plate, greatly increases, at the same surface semiconductor thickness, the minimum temperature at which the surface semiconductor material becomes discontinuous and agglomerates into islands. Annealing will take place at a temperature substantially lower than or equal to 800 ° C. As regards the growth stage, it can be done in chlorinated chemistry in the presence or not of germane depending on the material to be deposited. As a variant, it can also be done in hydrogenated chemistry, that is to say in the presence of silane SiH 4 and possibly of germane if SiGe is to be deposited. The growth temperature will be substantially less than or equal to 750 ° C at least as long as the silicon-based layer has not reached about ten nanometers. In the event of Si deposition, to accelerate the growth rate, it is then possible to increase the growth temperature so that it is substantially less than or equal to 800 ° C. In the case of deposition of SiGe, and in particular for high concentrations of Ge (for example of the order of 10% and more), it is possible to keep a low growth temperature for example substantially less than or equal to 700 ° C., throughout the growth phase until the desired thickness is reached. Although several examples of methods according to the present invention have been described in detail, it will be understood that various changes and modifications can be made without departing from the scope of the invention. It is of course possible to modify the content of the step of surface preparation of the substrate.
DOCUMENTS CITES [1] Growth kinetics of Si on fullsheet, patterned and silicon-on insulator substrates J.M. Hartmann. A. Abbadie, M. Vinet, L. Clavelier, P. Holliger, D. Lafond, M. N. Séméria, P. Gentile, Journal of Crystal Growth, 257 (2003) pages 19-30. [2] Thermal Agglomération of thin single crystal Si on Si02 in vacuum. Y. Ono, M. Nagase, M.CITED DOCUMENTS [1] Growth kinetics of Si on fullsheet, patterned and silicon-on insulator substrates JM Hartmann. A. Abbadie, M. Vinet, L. Clavelier, P. Holliger, D. Lafond, MN Séméria, P. Gentile, Journal of Crystal Growth, 257 (2003) pages 19-30. [2] Thermal Agglomeration of thin single crystal Si on Si0 2 in vacuum. Y. Ono, M. Nagase, M.
Tabe, Y. Takahashi, Japan Journal of Applied Physics, vol. 34 (1995) pages 1728-1735, part 1, N° 4A, April 1995.Tabe, Y. Takahashi, Japan Journal of Applied Physics, vol. 34 (1995) pages 1728-1735, part 1, N ° 4A, April 1995.
[3] Effect of patterning on thermal agglomération of ultrathin silicon-on-insulator layer. Y. Ishikawa, M. Kumezawa, R. Nuryadi, M. Tabe, Applied Surface Science, 190 (2002) pages 11-15.[3] Effect of patterning on thermal agglomeration of ultrathin silicon-on-insulator layer. Y. Ishikawa, M. Kumezawa, R. Nuryadi, M. Tabe, Applied Surface Science, 190 (2002) pages 11-15.
[4] Low thermal budget surface préparation of Si and SiGe, A. Abbadie, J.M. Hartmann, P. Holliger, M.N Séméria, P. Besson, P. Gentile, Applied Surface Science, 225 (2004), pages 256-266. [4] Low thermal budget surface preparation of Si and SiGe, A. Abbadie, J.M. Hartmann, P. Holliger, M.N Séméria, P. Besson, P. Gentile, Applied Surface Science, 225 (2004), pages 256-266.

Claims

REVENDICATIONS
1. Procédé de dépôt par épitaxie d'un matériau à base de silicium sur une couche (2) à base de silicium d'un substrat (10) de type semi-conducteur sur isolant ultramince, comprenant une phase de recuit du substrat suivie d' une phase de croissance du matériau à base de silicium, caractérisé en ce que la phase de recuit a lieu à une température de recuit sensiblement inférieure ou égale à 700 °C si la couche (2) à base de silicium du substrat est délimitée et à une température de recuit sensiblement inférieure ou égale à 800°C si la couche (2) à base de silicium du substrat est pleine plaque, et en ce que, lorsque le matériau à base de silicium que l'on dépose est du silicium, la phase de croissance se fait, à une température sensiblement inférieure ou égale à 750 °C tant que l'ensemble formé de la couche à base de silicium et du matériau déposé a une épaisseur sensiblement inférieure ou égale à une dizaine de nanomètres et à une température sensiblement inférieure ou égale à 800°C dès que ladite épaisseur est sensiblement supérieure, si la couche (2) à base de silicium du substrat est délimitée et à une température sensiblement inférieure ou égale à 775°C tant que l'ensemble formé de la couche à base de silicium et du matériau déposé a une épaisseur sensiblement inférieure ou égale à une dizaine de nanomètres et à une température sensiblement inférieure ou égale à 800 °C dès que ladite épaisseur est sensiblement supérieure, si la couche (2) à base de silicium du substrat est pleine plaque.1. A method of epitaxy deposition of a silicon-based material on a silicon-based layer (2) of a substrate (10) of semiconductor type on ultrathin insulator, comprising a phase of annealing of the substrate followed by '' a growth phase of the silicon-based material, characterized in that the annealing phase takes place at an annealing temperature substantially lower than or equal to 700 ° C. if the silicon-based layer (2) of the substrate is delimited and at an annealing temperature substantially lower than or equal to 800 ° C. if the silicon-based layer (2) of the substrate is full plate, and in that, when the silicon-based material which is deposited is silicon, the growth phase takes place at a temperature substantially lower than or equal to 750 ° C. as long as the assembly formed by the silicon-based layer and the deposited material has a thickness substantially lower than or equal to ten nanometers and a temp ure substantially less than or equal to 800 ° C as soon as said thickness is substantially greater, if the silicon-based layer (2) of the substrate is delimited and at a temperature substantially less than or equal to 775 ° C as long as the assembly formed of the layer based on silicon and on the deposited material has a thickness substantially less than or equal to ten nanometers and at a temperature substantially less than or equal to 800 ° C. as soon as said thickness is substantially greater, if the silicon-based layer (2) of the substrate is full plate.
2. Procédé de dépôt par épitaxie d'un matériau à base de silicium sur une couche (2) à base de silicium d'un substrat (10) de type semi-conducteur sur isolant ultramince, comprenant une phase de recuit du substrat suivie d'une phase de croissance du matériau à base de silicium, caractérisé en ce que la phase de recuit a lieu à une température de recuit sensiblement inférieure ou égale à 700 °C si la couche (2) à base de silicium du substrat est délimitée et à une température de recuit sensiblement inférieure ou égale à 800°C si la couche (2) à base de silicium du substrat est pleine plaque, et en ce que, lorsque le matériau à base de silicium que l'on dépose est du silicium-germanium, la phase de croissance se fait à température sensiblement constante et sensiblement inférieure ou égale à 700°C, si la couche (2) à base de silicium du substrat (10) est délimitée et à température sensiblement constante et sensiblement inférieure ou égale à 750°C, si la couche (2) à base de silicium du substrat (10) est pleine plaque. 2. Method for the deposition by epitaxy of a silicon-based material on a silicon-based layer (2) of a substrate (10) of semiconductor type on ultrathin insulator, comprising an annealing phase of the substrate followed by '' a growth phase of the silicon-based material, characterized in that the annealing phase takes place at an annealing temperature substantially lower than or equal to 700 ° C. if the silicon-based layer (2) of the substrate is delimited and at an annealing temperature substantially lower than or equal to 800 ° C. if the silicon-based layer (2) of the substrate is full plate, and in that, when the silicon-based material which is deposited is silicon- germanium, the growth phase takes place at a substantially constant temperature and substantially less than or equal to 700 ° C., if the silicon-based layer (2) of the substrate (10) is delimited and at a substantially constant temperature and substantially less than or equal to 750 ° C, if the silicon-based layer (2) of the substrate (10) is full plate.
3. Procédé de dépôt par épitaxie selon l'une des revendications 1 ou 2, caractérisé en ce que la phase de recuit se fait en présence d'hydrogène et/ou d'azote. 3. deposition method by epitaxy according to one of claims 1 or 2, characterized in that the annealing phase is carried out in the presence of hydrogen and / or nitrogen.
4. Procédé de dépôt par épitaxie selon l'une des revendications 1 à 3, caractérisé en ce que le matériau de la couche à base de silicium est du silicium ou du silicium-germanium.4. epitaxy deposition method according to one of claims 1 to 3, characterized in that the material of the silicon-based layer is silicon or silicon-germanium.
5. Procédé de dépôt par épitaxie selon l'une des revendications 1 à 4, caractérisé en ce que le substrat de type semi-conducteur sur isolant est un substrat silicium sur isolant, un substrat silicium contraint sur isolant ou un substrat silicium-germanium sur isolant .5. deposition method by epitaxy according to one of claims 1 to 4, characterized in that the substrate of the semiconductor on insulator type is a silicon on insulator substrate, a constrained silicon substrate on insulator or a silicon-germanium substrate on insulating.
6. Procédé de dépôt par épitaxie selon l'une des revendications 1 à 5, caractérisé en ce que la phase de croissance utilise une chimie chlorée. 6. epitaxy deposition method according to one of claims 1 to 5, characterized in that the growth phase uses chlorine chemistry.
7. Procédé de dépôt par épitaxie selon l'une des revendications 1 à 5, caractérisé en ce que la phase de croissance utilise une chimie hydrogénée. 7. epitaxy deposition method according to one of claims 1 to 5, characterized in that the growth phase uses hydrogenated chemistry.
PCT/FR2005/050183 2004-03-25 2005-03-22 Method for the epitaxial deposition of an si-based material on a layer of si-based material belonging to a semiconductor-on-insulator-type substrate WO2005093822A1 (en)

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Citations (2)

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Publication number Priority date Publication date Assignee Title
EP1018758A1 (en) * 1998-06-30 2000-07-12 Sony Corporation Method for forming monocrystalline silicon layer, method for manufacturing semiconductor device, and semiconductor device
US20030001219A1 (en) * 2001-06-29 2003-01-02 Chau Robert S. Novel transistor structure and method of fabrication

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
EP1018758A1 (en) * 1998-06-30 2000-07-12 Sony Corporation Method for forming monocrystalline silicon layer, method for manufacturing semiconductor device, and semiconductor device
US20030001219A1 (en) * 2001-06-29 2003-01-02 Chau Robert S. Novel transistor structure and method of fabrication

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Title
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