WO2005088890A1 - Eye tracking and expansion using oversampled signals - Google Patents

Abstract

The present invention relates to the reduction of timing uncertainty in high speed communications channel or interface and to a receiver and method using the same. The receiver according to the invention uses an over sampled data stream to detect bits, analyses the sampled stream of bits, determines valid samples and then expand them into a minimal eye required for accurate and reliable data reading. The present invention includes capability to track an eye across sample blocks, correcting for jitter.

Description

EYE TRACKING AND EXPANSION USING OVERSAMPLED SIGNALS

Technical Field The present invention relates to the communication of signals, in particular, to the transmission and reception of digital signals. More specifically, the present invention relates to the dynamic compensation for noise in high speed communications channels or interfaces. The present invention is particularly applicable to interfaces between integrated circuits and for high speed communications, especially where the channels may have small or zero eye openings. Background of the Invention One common form of communication system involves digital signals representing data which is sent over wires or other communication media, called a communication channel. In a communication channel, the integrity of the received data can be observed using an eye diagram, such as in Fig. 2. The eye in the very centre is the region where the data is stable and is strobed. The eye diagram shows time in the X domain, in picoseconds in Fig. 2, and voltage or current in the Y domain, in mV in Fig.2. To receive data securely, it is necessary to sample the data (that is, close a gate in the time domain), with the switching threshold of the gate as close as possible to the centre of the eye. A technique for tracking the centre of the eye in the voltage or current domain is described in US patent application 60/315,907. The communication channel requires a particular bit error rate, which is determined by the application. The bit error rate is proportional to the date rate; the signal swing and the noise (both phase noise which is seen as jitter, and amplitude noise). These noise factors reduce the size of the eye opening in the eye diagram. Date rate and the physical factors that contribute to jitter, determines the eye size. It is highly advantageous to be able to achieve a low bit error rate where there is a small eye size. Such advantage can be used to achieve greater distances of communication, higher data rates, lower power and higher channel reliability. The primary factors that reduce eye size is jitter. In very high speed systems, especially those operating past the -3dB point of the channel response, almost all amplitude noise is at a lower frequency than the bit rate, and hence is transformed into jitter. Generating several signal samples over time (over-sampling) and combining the samples in a majority decision logic to determine the most likely outcome is well-known and used, for example, in US 4,771 ,421 , US 4,241 ,311 , US 4,965,884, US 5,018,142 and EP 0797,326, EP 0575,000. US 4,771 ,421 describes a system comprising sampling means having inputs connected to the outputs of shift registers for giving an indication of a particular binary value when more than a predetermined number of outputs of shift registers show an one-bit value. No BER distribution is taken into consideration. US 4,241 ,311 describes a system comprising means for sampling a signal at the times of clock signal, and apply the stream of sampled signal bits to a digital shift register and on to majority gates. No selection of the best copy is disclosed. In US 4,965,884, a system is described comprising sampling means and means for choosing a data sample representing a majority of the data samples. The use of majority circuits is quite common in electronics as a means of filtering the signal in the time domain. US 5,018,142 describes a system comprising a sampler for sampling incoming signals and employing majority circuits to change the value of any samples that are not part of a plurality of sequential samples of the same value. This is similar to a majority function as used in US 4,965,884. US 6,127,864 describes a system that samples data at three different times and also outputs a majority signal at the forth time. EP 0575,000 describes a system having a majority logic arrangement for estimating data from a noisy data signal, which monitors the data samples entering and leaving a shift register and a transition between "1" state and "0" state. EP 0797,326 describes a method including the steps of receiving a signal, sampling the signal at a predetermined sampling rate, generating a second and third samples by shifting the first sample, whereupon the samples are compared to one another and a majority sample value is obtained, which represents the corrected signal value. Though the above described approaches involves over-sampling of several signals, all of them cause noise in the time domain to be filtered. However, it is not evident that the majority signal would have a better quality than separate signals combined by majority. Due to the higher data rate required in high speed communications, the channel bandwidth is occupied mostly by data that makes it impossible to rely upon majority decisions without the precise estimation of the sampling position with respect to eye window. According to another approach, the Bit Error Rate is measured for a signal decided as having the least BER by majority and compared with each of the repeatedly received patterns. In EP 0193,332 an apparatus for processing a digital signal is described wherein a particular signal pattern with the least error rate is determined by majority logic. The signal pattern is transmitted repeatedly, and processed in a receiver by measuring the Bit Error Rate in a transmission path with the majority signal pattern equivalently used as a reference. Thus, the signal copies are produced by a transmitter, not by a sampling system, therefore the copies may differ in frequency, noise characteristics, etc. In US 4,891 ,812, a method is described comprising the steps of generating a majority signal from at least three signals, determining the BER for each signal by bit-by-bit comparison with the majority signal, and selecting either one of the signals or the majority signal. Again, the signals are coming via separate channels and produced by a transmitter, not by a sampling system, thus, the system does not improve the quality of the signal received, but chooses a signal of better quality among several signals. The BER is estimated between different channels with respect to majority signal and does not reflect the BER distribution within a separate channel as a function of phase of the sampling clock. According to US 4,432,094, a method comprises sampling the signal at different times and deciding by majority the signal with the lowest information error rate. However, the samples are taken at multiple of the information clock frequency that does not allow to use this technique in the high speed interfaces because it is impossible to generate multiple frequencies when the information clock frequency is already near the maximum achievable in this particular technology. According to the above described and other patents, such as US 6,111 ,911 , a high degree of chip code synchronization is used to clock the data bit position. Transmitters transmit a data bit in synchronization with the chip code pattern, therefore allowing chip position to be used as a cue to the associated data bit position. Since the optimal position in which to sample a data bit is known, that portion of the Bit Error Rate loss is eliminated. Empirical results from this technique have shown practical improvements in the error rate versus carrier-to- noise ratio in the minimal detectable signal case. This technique is applicable to any direct sequence spread spectrum system in which a high degree of synchronisation is inherently achieved, provided that the data is transmitted in synchronisation with the chip code clock. However, very often, in particular, in high speed communications, such a synchronisation is not effective, while the Bit Error rate is defined by the current application system requirements. The more strict are these requirements, the lower is the data rate providing the desired Bit Error level. A special case of this applies to where a communication channel uses clock recovery, that is, the clock is recovered from the signal, as in US 4,891 ,812 discussed above, and this is used to latch the received data. This approach does, to a limited degree, reduce the effect of low frequency noise, such as environmental changes. However the problem with this approach is that the entire error in the clock recovery system or the phase detectors is added to the noise in the channel and for very high frequency applications, this inaccuracy becomes a significant problem. Object of the present invention. It is therefore a primary object of the present invention to provide an improved system for extracting the data from a stream of oversampled data. It is another primary object of the present invention to compensate dynamically for the jitter caused by the channel noise, production tolerances and variations in channel length. It is another primary object of the present invention to enlarge the effective eye size in a data stream. It is another object of the invention to provide an improved, economical apparatus for transmitting and receiving data at high bit rates required for chip-to chip and high speed digital communications. It is yet another object of the invention to provide an improved, highly accurate and reliable reading of data at high speeds suitable for the processing of digital signals in communication systems. It is a further object of the invention to provide an improved and highly compact receiving circuit with low timing uncertainty that can be economically implemented in a semiconductor integrated circuit. It is another object of the invention to provide an output interface for a digital receiver that provides the data flow through the receiver with a transmission rate of the signal at a low bit error level. It is a further object of the current invention that the channel reduces the production tolerances needed for its implementation by virtue of the system adapting to the environment in which it operates. It is a further object of the current invention to reduce the timing errors in the clock recovery process in a serial communication link. These and other objects of the present invention are attained by a receiver employing a plurality of samplers coupled to circuitry according to the present invention whereby the effective eye size is enlarged. A particular form of the invention is suitable for transmitting digital data at Rapid IO^®, PCI Express, Infiniband^®, 10GbE, 10GFC, OC192, OC768 and other high speed communications standards. Summary of The Invention The present invention relates to a method and apparatus for processing of oversampled data by analysing the sampled pattern, expanding individual bits in an oversampled data stream to expand the effective eye size, and dynamically tracking the eye, to compensate thereby for the jitter caused by channel noise, production tolerances and other effects, and provide accurate and reliable reading of high speed data. According to a first aspect of the invention, a high speed receiver with eye tracking capabilities is provided, the receiver comprising: - a sampling system producing a series of sampled bit values of the received signal, the system provided with a polyphase clock generator generating clocks for spreading the said samples in time so that each bit interval is covered by several samples; - a pattern analyser which analyses the sampled pattern and expands each set of neighbouring identical samples to a predetermined required pulse width, wherein, if a next set of samples starts with the sample value same to the sample value of the previous set, the two sets of samples are processed as a single bit; - a logic circuit operating on the expanded set of samples to produce a data signal (Q) and a valid sample signal (E) indicative of the number of the valid sample in the set of samples; and - a controller, which calculates the current eye width as the longest string of identical sample values, and, using the said valid sample signal obtained from the logic circuit, defines the current eye centre and its offset with respect to half width of the bit interval; wherein the said offset signal is further applied to said data signal to produce a recovered data; and - a multiplexor which selects which sample of n samples per bit is used to define the recovered data. According to a second aspect of the invention, a method of data processing using the above system is provided. The pattern analyser analyses a sampled pattern by comparing each bit with its neighboring bits, defines identical sampled bits and expands this further to a minimal required bit interval. The minimal bit interval is determined by the process, the speed of the system, BER requirements, and other parameters. One bit interval is covered by the number of samples produced by the sampler in the course of oversampling process. Alternatively, the selected identical bit values can be first expanded to less than the bit interval, to keep the ability to track the eye if in case of limited number of valid samples, so that, if a single sample is selected, then, the selection is further expanded to 2 or 4 neighboring bits. The analysis and expansion can be made by using a pattern based eye expanding program, or using a table or encoded table of possible valid data states or transitions. The table values can be approximated and fixed into the design. To determine the table values, a sequence of a training pulse can be used. The eye can be expanded simply by passing the selected sample value to a register representing the value of the data for the whole symbol period. The output of the register can be the value of the symbol in NRZ binary, which is a binary value for the bit interval. Preferably, the knowledge of the previous sample is used when selecting the next sample from the set of samples for the next symbol interval. Thus, the subsequent set of samples can be re-positioned about the new eye centre. Further details, embodiments and modifications of the invention are presented below with reference to particular embodiments of the invention.

Brief Description of The Drawings For a better understanding of the present invention and the advantages thereof and to show how the same may be carried into effect, reference will now be made, by way of example, without loss of generality to the accompanying drawings in which: Fig. 1 shows a block diagram of a system for processing data from a stream of data according to the present invention. Fig. 2 shows an eye diagram for a channel running at 12.5Gbps with an eye opening amplitude of 20mV and 55ps. Fig. 3 is a block diagram of an example embodiment of a system for processing data from a stream of data according to the present invention. Fig. 4 illustrates a method of data processing according to the present invention. Fig. 5 is a block diagram illustrating in more detail the eye tracking and expansion operation according to the present invention. Detailed Description of the Invention The invention will now be described in detail without limitation to the generality of the present invention with the aid of example embodiments and accompanying drawings, and with reference to example embodiments in Appendices A and B. Fig. 1 shows a block diagram of a system for processing oversampled data from a stream of data. The oversampled data can be obtained as described in WO 02/078228 by the same inventors. As seen in Fig.1 , the system comprises a high speed sampler or a set of samplers 1 , pattern analyser/eye expander 2, processing logic circuit 3, a state machine/controller/skew tracker 7 and data pipeline 8 for latency adjustment. Preferably, samplers 1 are implemented as a set of registers for latching data clocked by a polyphase clock or coupled to a set of delay devices for providing a series of signal copies with each copy being shifted by a predetermined time interval. These registers provide a signal at different points of time as described in detail in the above mentioned WO 02/078228. Samplers can be also implemented in different ways, such as flip-flops, latches, track-and-hold, sample-hold devices, etc. An example embodiment circuit of the system for data processing according to the invention is shown in Fig.3. The outputs of samplers 31 are connected to the inputs of data preprocessing block 32, comprising a pattern based analyser/eye expander. The pre- processed data is fed to logic elements, such as majority elements 33, 33', 33", where the output of each of the majority element is equal to "1" if more than half of the inputs are equal to "1", and "0" if more than half of the inputs are equal to "0". An odd number of samplers shall be used in conjunction with each majority elements with a total quantity 2n+1. In the system shown in Fig. 3, the set of data processing elements 33, 33', 33" provides a value Q (which is called further "data signal") corresponding to the value at the majority of its inputs (DO, D1 , D2), and a number E of inputs having value different from the value at the majority of inputs. The latter defines the number of the valid bit value in a set of bit values and is called further "a bit valid signal", "valid bit" in the specification or "VALIDJN" in Verilog appendices And B). A logic element can be implemented as described in WO 02/078228, or the logic can be synthesized by standard tools, such as those from Synopsis and other EDA vendors, or can be derived by hand without difficulty. The system in Fig. 3 further comprises multiplexer 36 for selecting a valid copy of the signal, controller/state machine 37 for determining the number of this copy, and pipeline 38 for latency adjustment. In operation, a data stream is oversampled by a set of samplers 31 , each triggered at a different point in time. A particularly useful method of spreading samplers in time is to use a polyphase clock. Clock trees can generate a polyphase clock by virtue of their delay, or the clock can be implemented using a ring oscillator with each clock phase being taken from each inverter stage of the oscillator, or by an Array Oscillator. Some extra phase splitters can be used for finer granularity. With the polyphase clock, the sampling point of each of the registers is spread in time by virtue that they are clocked at slightly different instances in time. For the sake of clarity of this description, it is assumed the received signal is oversampled 16 times. Oversampling by 3, 4, 8, 16 or any other amount is possible within the scope of the present invention. It can be seen from the eye diagram in Fig. 2 that the set of samples produced by samplers 31 may include the correct data and various error values. The location of the data depends on the position of the data eye. In Fig. 2, the eye is positive, but in practice, systems may have a negative eye, which means that the jitter distribution over the spectral range less than the Clock Data Recovery response and the amplitude noise is larger than half the symbol interval. For any individual set of samples, the samples will include in this case the data and noise. In some cases, the data may be a minority of the samples. The oversampled data are preprocessed in a pattern analyser 32 which expands the eye window as follows. If a data stream is 16x oversampled, as described, e.g. in WO 02/078228, with the samples falling over 1.5 bit periods, the stream of samples may be: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 There are clearly two bits here, the first being a 0, the second 1. In a bandwidth limited system, short pulses tend to become longer. An extreme example of this is in Multi Mode optical Fibre (MMF), where modal dispersion causes pulses to lengthen. For example, a 1,0,1 pattern may become: 1111111111111011 In case a majority circuit such as in the prior art, is used solely, this will give the wrong result in both the above instances: either 1 or 0 in the first case and a 1 in the second case. In the second case, the data is clearly a 0, because if the data pattern was 111, then no zero would have occurred. Taking another case, 1110000000000001, this is clearly a 0, with the preceding and the succeeding bits being 1. It is useful therefore to consider three bit periods at the same time. Another case, is 1 1 1 1 1 1 1 1 1 101 1 1 1 1. This is the same as the previous case, a 0 preceded by a 1 and followed by a 1. In three bits, it is possible to have only: 000 001 010 011 100 101 110 111 For the possible oversampled bits, it is possible to tabulate the valid results. The case of 000 must be only 0000000000000000, and the case of 111 is similarly trivial. For 010, this must be ~x bO, ~x b1 , ~x bO, where "~x by" is a continuous sequence of x bits of polarity y. If the ~x b1 component is less than the minimum eye width, then ~x b1 must be expanded to the minimum eye size. For example, if

0000000000010000 is received, and a minimum eye size is 4 bits, this must be expanded to at least 0000000011110000. The eye expansion can be performed by using a pattern based algorithm as described above, or a table or encoded table of possible valid data states or transitions. This is a routine work for a specialist in the art. Following this pattern based eye expansion, a dynamic eye tracker 30, which comprises logic circuit 33, 33', 33"; pipeline 38, multiplexor 36 and controller/state machine 37, can then pick out the eye centre and the correct state.

The operation of the eye tracker is explained in detail below with reference to Figs.

4 and 5 and in the Appendices A and B. This then leaves only the case of a transition from a series of 0s to 1 , or 1s to 0, occurring within the set of samples. If there is a sufficient density of transitions, the samples will fall accurately about the symbol interval. This means that in one interval, the signal is moving from one state to another. Jitter can cause both negative and positive shifts in time of any transition. If the previous bit was a 0 and a transition occurs in the set of samples for the present symbol, then the location of the change can be determined by overlaying the raised co-sine stat eye (the term "stat eye" means "statistical eye", see "Signaling Performance Over Various Backplane Configurations" by Brian Seeman of Xilinx, IEEE 802, 01.01.04.) onto the set of symbols: often the eye is elongated and offset. This stat eye may use a higher BER to create an eye opening for this purpose. This then gives a probability curve of the data being 1 or 0 within the interval. This probability weighting can then be applied to the set of samples. For example, if a stat eye at a higher BER occupies 25% of the symbol interval at the threshold of the sampler, to left of the centre of the symbol interval and 75% to the right, then the mask can be biased such if there is a transition in the first 12 bits of the sample, then the symbol is assumed to be the value at the end of the sample, and visa versa. Notice that the center of the eye is often not in the center of the sampled set of bit. This result is different from 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0. There is a shift of the eye center and this information is useful to re-position subsequent sampling to fall about the eye centre. This is preferably accommodated by a circuit according to the invention which both expands the eye further and tracks the eye, such as described in more detail below with reference to Fig.5, or a similar circuit. That is, it is not desirable to replace the pattern 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 with 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0, because the ability to track the eye center will be lost. Eventually the eye could drift across the boundary of the samples and bit would be lost. According to the present invention, a number of example algorithms is proposed that can perform eye expansion at the same time as eye tracking. A basic algorithm according to the simplest embodiment of the invention that performs only eye tracking is presented in Appendix A. This algorithm is written in Verilog. Improved algorithms according to the further embodiments of the invention can operate with a smaller eye size further, that is detecting a small sequence of bits such as three, as being a valid bit, and tracking the eye at the same time.

Such an algorithm will now be described, and the hardware to implement this is described in Verilog in Appendix B. The preferred embodiment of the present invention as described in Appendix B is to place a pattern based eye expander 32 in between the sampler

31 and the dynamic eye tracker 30. The structure of the pattern based eye expander 32 has already been described: namely a table or logic circuit that encodes a table as described herein. Operation In general, a method of data processing according to the present invention is described in Figure 4. The first step 41 of the data processing method according to the invention is producing a set of samples. The incoming data is sampled by a plurality of high speed samplers 31 as shown in Fig.3, or samplers 1 in the circuit of Fig.1. The second step 42 is pre-processing samples by applying the pattern analysis and eye expansion. For example, the samples can be applied to a digital circuitry such as described in Appendix A and processed in a variety of ways including the application of the bit expansion algorithm detailed in this document. The expanded pre-processed samples are further applied to a dynamic eye tracking procedure as explained in more detail with reference to Fig. 5. In step 43, the logic circuit determines which sample of 16 samples per bit is used to define the data. It is done per word basis. Optional, a noise filtering step can be introduced after, but generally, the noise if discarded already at the step of pattern analysis and eye expansion. The logic circuit 44 produces a control signal indicative of the number of the valid sample (VALIDJN, in the Verilog) for a step of eye tracking 47 performed by state machine/controller 37 in Fig.3. In brief, once one or a set of neighbouring samples have been selected as being the valid sample, the eye can be expanded simply by passing that value to a register representing the value of the data for the whole symbol period. The eye width can be either predetermined, or defined by using the current pattern by calculating the longest sting of identical bit values. Once the minimal eye width is calculated, the position of the eye with respect to half width of bit interval is determined and the eye is shifted to the correct position by using the number of the sample in the set of samples as an offset of the eye 46. For example, if the sample number 12 is chosen from a set of 16 samples, then the eye is off-centre. The subsequent set of samples is re- positioned about this new centre. The whole of the symbol interval has the value of the selected sample. For example, if the selected sample has a binary 0 value, then this information means the eye is expanded from this one sample to the whole 16 samples. The knowledge that the previous sample was 0 can then be used in the algorithm selecting the next sample from the set of samples for the next symbol interval. The actual selection can be done by a 16:1 multiplexor 6 driven by the number of the selected sample, such as is shown in Fig. 1. In another embodiment, where there are narrow eyes, such as represented by a single sample, the pattern analyser/expander 2 may expand that one sample into the neighbouring samples, such as neighbouring 2 or neighbouring 4 samples.

This expanded eye will then modify the response of the subsequent eye tracking and selection algorithm, such as is disclosed in the Verilog code in Appendices A and B. Thus, as described above, the main advantage of the invention is that the combination of pattern analyser 2, the logic circuit 3 and controller/eye tracker 7 is able to extract the eye where even a minority of samples are the data to be sampled. The Verilog describing such a circuit is reproduced in Appendix B: a person skilled in the art can use this to synthesise the exact circuitry for any process. Minor changes to the algorithm may be needed in some technologies to achieve timing closure, such as by the addition of additional register or clocking stages. A person skilled in the art will be familiar with how to make such changes, as these are needed in almost all systems operating at the speeds relevant to the present invention. In a preferred embodiment, the samples from the sampler 31 are first applied to a pattern based eye expander 32, then to the dynamic eye tracker 30 detailed in Appendix B, which comprises logic circuit 33, 33', 33", multiplexor 36, pipeline 38 and controller 37. The tables for the pattern based expander 32 depend on the characteristics of the medium. In some cases, these values can be determined by a sequence of training pulse. In other cases, the values can be approximated and fixed into the design. The operation of the pattern based expander 32 has been described already.

Description of basic eve tracking procedure The eye-tracking algorithm operates within a structure shown in Fig.1 where the "data stream" is a stream of bits at a nominal bit rate (BR). This stream is over- sampled at a rate N times higher than the bit rate. The resultant output of the high speed sampler 1 is N * W samples at BR/W rate, where W is the output word size. These output "samples" are processed by pattern analyser 2 in a variety of ways including the application of the bit expansion algorithm detailed in this document. The logic circuit 3 operates on the "processed samples" to produce "valids = valid bits)" which are indicators of stable eye regions, a valid bit usually indicating a sample bounded by two identical samples ("a three sample window"). Valids refers to a group of valid bits passed from the logic circuit to state machine, in this case they are a bit's width of values time averaged over a word.

That is, each valid bit (16) is produced by an "AND" of every 16th value in valid data. For example, a 4 bit word gives 64 samples; this used with the last sample of the preceding and first of the succeeding word gives a 64 "valid bit" "valid data". The "valids" bitO = valid data 0 & 16 & 32 & 48 bitl = valid data 1 & 17 & 33 & 49 etc. For each sample, its preceding and succeeding samples are compared by pattern analyser 2 with the sample and if all three are the same, then the valid set to this value, say, to one, otherwise, it is set to zero. The logic circuit 3 can optionally further process the valid data in a noise filter to reduce the number of eye selections the skew tracker follows. In the case of the behavioral Verilog in Appendix A, the valid samples are aggregated over an entire word (W) to give "valids" as N output bits corresponding to a single eye track. Preferably, to match the data stream rate and the speed of data processing, the data are delayed using a data pipeline 8 so that the output of the state machine 7 signal "select" is applied to the data responsible for that result. This makes the algorithm real time at the cost of increased data latency. Skew (Eve) Tracking A method of eye-tracking in its basic implementation processes data by applying two operations, an eye (window) expanding operation and eye tracking operation. The first operation is applied to the "valids" and expands the three-sample eye window to some larger odd value. The second operation is applying a search region bounding the currently selected phase used to generate data output. The search is applied from the current selection outwards to the second window limits, looking at the first window results for each equidistant phase pair straddling the current selection. The selection is moved away from the invalid first window of the first encountered asymmetric pair. In simulation, this version of a skew tracker (V1) was shown to require a stable eye aperture of approximately 8 phases (1/2 the bit period) in order not to introduce algorithmic bit errors over and above the intrinsic BER of the sampling system. Description of dynamic eve tracking procedure The dynamic eye-tracking procedure operates within the samestructure shown in Fig.1 as described above.

Dynamic Eve Tracking The dynamic eye-tracking procedure is illustrated in Fig. 5, where the "non- critical pipeline" implements the primary operation, and the "data pipeline" the secondary operation that are performed in parallel to each other. The primary operation is a long-term integration function that determines the minimum eye aperture over a prolonged period. This is achieved by finding the longest sequence of ones in the "valids" for each cycle and then noting the shortest sequence found. A timeout allows the function a recovery path, should some instantaneous event collapse the eye aperture. This can be viewed as a filter function removing the 'static' higher frequency components of noise and jitter from influencing the secondary function. The Verilog code as presented in Appendix B has a choice of example embodiments of secondary functions generating data output by applying a search region bounding the currently selected phase. Version AL2 Version AL2 (mode =2'b00) applies the same secondary function as described above with reference to appendix A for the basic eye-tracking algorithm. The logic to implement this is relatively large and deep for the frequencies of operation targeted for this technology. As a result, the duty cycle of this function is unlikely to be 100%, as was also the case for the basic eye-tracking algorithm. Version AL2 improves the eye tracking facility requiring a 4 or 5-phase stable eye aperture to give error free algorithmic execution. With a minimum of 4-5 valid samples, this embodiment provides no errors at a peak slew rate around lOOOppm (with 3.25 valid samples, the BER being already 10^"5 at the same slew rate). Version AL3 Version AL3 (mode =2'b01) is illustrated in Fig.5 and makes the assumption that it is unlikely for invalid regions to suddenly appear in the stable eye aperture, the expectation being that jitter will encroach the stable eye aperture about the currently selected phase in a relatively controlled fashion. This version only monitors the valid status of the two "valids" at either periphery of the stable eye aperture. The difference is that, when only the two samples are selected that define the outer limit of the stable eye to use for tracking, less logic is needed compared to selecting several samples (6-10), as in AL2 described above. The case of several samples did not adapt well to the environment and the importance of the sample/result is indeterminate. Though it may seem dangerous not to monitor the centre of the eye, the peripheral "valids" are effectively a three-phase buffer and any noise injection capable of leaping these buffers will give any algorithm problems although the failure mechanisms may be different to those of AL3. AL3 has its compensations in that the implementation logic is two 16:1 muxes driving up and down selects on a small counter, so realizing a 100% duty cycle is relatively simple. Version AL3 again improves the eye tracking facility though still requiring a 4 or 5-phase stable eye aperture to give error free algorithmic execution. With a minimum of 4-5 valid samples, this embodiment provides no errors at a peak slew rate around 3000ppm (with 3.25 valid samples BER value being around 10^"7). The main advantage over AL2 however is a reduction in the logic required to implement the design. Version AL4 Version AL4 (mode =2'b01) skew tracker is identical to AL3 but with a pipeline that delays the data samples to align with any new sampling selection derived from those data samples. This makes the algorithm real time by delaying data at the output of the logic circuit, for example, for an extra two cycles (~5 ns), so the selected phase for output of data is generated by using valids from the same data. Version AL4 again improves the eye tracking facility requiring a 4-phase stable eye aperture to give error free algorithmic execution. This embodiment requires a minimum of 4 valid samples to give no errors at a peak slew rate around 3000ppm (with 3.01 valid samples giving BER value around 10^"6). The data latency impact is most likely to determine the use of this algorithm. Version AL5 Version AL5 (mode =2'b10) eye tracker is identical to AL4 with an extra logic layer that is only useful when the stable eye aperture approaches 3 sample phases. This addition will increase the secondary function from looking at the two adjacent "valids" if they impart no tracking information to the "valids" +/- 2 from the selection if and only if the selection valid = 0. This will allow the following case to be tracked. "valids" = 0000001 NS0000000, valid bits N and S are both 0. The current sample selection at S is invalid and sampling here will not capture good data. Changing the select point to N (as illustrated by data pipeline in Fig.5) will capture good data, as the valid 1 bit is a 3-sample window function, so the adjacent bit is identical to the centre bit. Version AL5 again improves the eye tracking facility requiring a 4-phase stable eye aperture to give error free algorithmic execution. This embodiment requires a minimum of 4 valid samples to give no errors at a peak slew rate around 3000ppm (with 3.01 valid samples giving BER value around 10^"6). At an eye aperture of 3-phases this version out performed AL4 by a factor of 2. There can be applications where AL4 may be chosen in preference to AL5 where the extra logic negates a 100% duty cycle. Versions AL3 and AL5 are close to the limits for this single phase stepping approach for delayed and real time skew tracking. The limit is obviously a 3-phase stable eye aperture, beyond this point the algorithm will be starved of information, as the "valids" word will be all zero. To improve on this limit for the number of observed samples corresponding to a bit requires the introduction of pre-processing of the raw sample data with algorithms and techniques such as that described in this document. To improve on this limit for tracking a moving eye once the stable region disappears from word to word requires the ability to determine the eye position for a word and make any required selection movement. It shall be appreciated that none of the AL skew trackers ensure tracking of the best selection of sampling phase for the lowest BER. This is because the selected phase is not guaranteed to be the phase closest to the centre of the eye. The overall result however is better because the tracking algorithm is less likely to break down, and any breakdown of the tracking algorithm introduces an associated BER several orders of magnitude greater than the intrinsic BER in the sampling system. An alternative view of these novel skew tracking algorithms is that the combination of the primary and secondary functions is to track the two boundaries between the stable and unstable regions whereas existing systems attempt to track either the region of maximum stability or region of maximum instability. It shall be appreciated that other embodiments and modifications of the present invention are possible within the scope of the present invention.

APPENDIX A

Verilog Description (Behavioral) llll II Design unit : Fast skew tracker II II Filename: SKEW TRACKER.v II II Description: II II This model is an behavioural (in fact almost RTL) representation of the Skew Tracker circuit. II This is a modified AC52 model, with an ability to dinamically size eyes . II II Simulator: Modelsim 5.6 II-

"timescale Ins / lps module SKEW TRACKER (CLK // clock RESET_B // Global Reset (act L) VALID_IN_ // compound valid over SelectorsCount SEL_ // index to which set of samples to use ENJ3UB // skewed off end of register (sub pipe delay) EN ADD ) // skewed off end of register (add pipe delay)

lll PARAMETERS II-

//-

ll-// ll Variable // II- -//

parameter valid_width 16; // number of input valid bits parameter selector_width 16; // selector width parameter sel_out_width 4; parameter lock_len 3 parameter add_sub_pipe 2

parameter first_window_wd 9; parameter secnd_window_wd 7;

parameter skew_tracker_del = 1; // // // derived // / / parameter skew_t_del = valid_width * (skew_tracker_del+l) ; // make behavioural parameter lock_out = lock_len -1; // lockout loop is n+1 cycles // DECLARATIONS // / / // 10 // _{// /}

input CLK, // clock RESET_B; // Global Reset (act L) input [valid width-l:0] VALID IN ; // input valid bits

output [sel_out_width-l : 0] SEL_; // select output (number) output EN_SϋB, // subtract bit EN ADD; // add bit -// // Registers // // -// reg EN_SϋB, // subtract bit EN_ADD; // add bit reg [valid_width-l:0] val_reg; // latch of valid in reg [valid_width-l:0] fi st_window_fn; // top layer of and structure reg [skew_t_del -1:0] first window_d; // top layer of and structure r reg first_window_bit; // top layer of and structure reg sh left; reg sh right; reg look left; reg look_right; reg [valid_width-l: 0] selector; // long form select reg [sel_out_width-l: 0] sel_short; // short form select reg shift left_req, // want to shift sample point left shift right req; // want to shift sample point right reg [lock_out-l:0] sh lock; // lockout while changes take effect reg [add_sub_pipe-l: 0] sub_pipe, // delay pipelines add_pipe; // // // Wires // // / / / // Variasbles // // /

integer i, j , k; // Assignments // // //

assign SEL_ = sel_short; // set output to be selector count / // Initial Setup // / // / // // COMBINATORIAL PROCESSES // // // N always @(sel_short) begin selector = 16'hOOOl « sel_short; // turn count in to individual selects end // // // CLK PROCESSES // // / always @ ( posedge CLK ) begin val_reg <= VALID_IN_; // latch VALID_IN first first_window_d {first_window_d»valid_width} ; // 0 - N pipeline first_window_d [skew_t_del-l : skew_t_del-valid_width] first window fn; // 0 - N pipeline if ( ~RESET_B ) // if reset begin // set defaults sel_short <= 0; sh lock <= 0;

shift left_req <= 0; shift_right_req <= 0; add_pipe <= {add_sub_pipe {l ' bO} } ; sub_pipe <= { add_sub_j?ipe { 1 ' bO } } ; end else // else begin // implement selector shifts for (i=0;i<valid_width;i=i+l) // for each phase valid (3bit window) begin first_window_bit = 1; // set valid for (j = ( (valid_width + i- ( ( (first_window_wd-3) /2) ) ) %valid_width) , // from -rotate l/₂ window left (-3 for

3bit) j != ( (i+( ( (first_window_wd-3)/2) +1) ) %valid_width) ; // to -rotate l/₂ window right (-3 for

3bit) j = ( ( (j + 1 ) %valid_width) ) ) ■ begin //k = (j<0) ? valid_width +j : j; // get round signed integer k = j; // get round signed integer first_window_bit = first_window_bit ss val_reg[k]; // accumulate value over first_window_wd end first_window_fn[i] <= first_window_bit; // first_window_fn, first_window_wd bit valids end sh left = 0; // set search variables sh_right = 0; for (i=(secnd_window_wd-l) / ;i>0;i=i-l) // for reducing pointer either side of selection begin look left = (first_window_d[ (sel_short+i) %valid_width] ) ; // look left at state of first window function look_right = (first_window_d[ (sel_short-i) %valid_width] ) ; // look rignt at state of first window function

//sh left = (look left == look_right) ? sh left : look left; // if different update shift record //sh_right = (look left == look_right) ? sh_right : look_right; // (record shift away from nearest transition) sh left = (look left == look__right) ? sh left : (i==l) && (first window d[sel short]) ? sh left : look left; // if different update shift record sh_right (look left == look__right) ? sh_right : (i==l) SS (first window d[sel short]) ? sh_right : look_right; // (record shift away from nearest transition) end if (sh left == sh_right) // if we have symmetry begin if (first_window_d[sel_short] ) // if centre first_window good α begin shift left_req <= 0; // stay where we are shift_right_req <= 0; end else // else centre first_window not good begin shift left_req <= | (first_window_d[valid_width-l: 0] ) ; shift_right_req <= 0; // go looking for new sync if one exists end end else begin // else asymmetry shift left_req <= sh left; shift_right_req <= sh_right; // shift away form closest transition end

if ( shift left_req S ~sh_lock [lock_out-l] ) // if shift left begin sel_short <= ( sel_short + 1 ) % 16; // move sample point sh_lock <= ~0; // wait on pipe to update end else // else begin if ( shift_right_req & ~sh_lock [lock_out-l] ) // if shift right begin sel_short <= ( sel_short - 1 ) % 16; // move sample point sh_lock <= ~0; // wait on pipe to update end else // else begin sh_lock <= { sh_lock [lock_out-2 : 0] , 1 'bO } ; // shift down lockout for pipe update end end end // generate EN_ADD, EN_SDB signs sub_pipe [0] <= shift left_req & selector [selector_width-l] s~sh_lock[lock_out-l] ; // if shift left at end of register add_jpipe [0] <= shift_right_req & selector [0] s ~sh_lock [lock_out-l] ; // if shift right at end of register add_pipe [ add_sub_pipe-l : 1 ] <= add_pipe [ add_sub_pipe-2 : 0 ] ; // shift pipe delay sub_pipe [add_subj>ipe-l : l] <= sub_pipe [add_sub_pipe-2 : 0] ; // shift pipe delay

EN_ADD <= add_pipe [add_sub_pipe-l] // add pipe output - end of shift add bit EN SUB <= sub_pipe[add_sub_pipe-l] , // sub pipe output - end of shift sub bit end

//

// SELF CHECKING PROCESSES

// // // // Command Heartbeat // / / endmodule

-

APPENDIX B

Description of adaptive eve tracking algorithm

Verilog Description (Behavioural)

The following is an amalgamation of three existing Verilog files and has not been verified. llll II Design unit : Fast skew tracker II II Filename: ΞKEW_TRACKER_AL2. II II Description: II II This model is an behavioural (in fact almost RTL) representation of the Skew Tracker circuit. II This is a modified AC5 model, with an ability to dinamically size eyes. II This model is based on a new algorithm which "runs" from the approaching noise II This model only looks at two Valids . II II Limitations : II II 1) architecture is hard coded needs to be changed as soon as we can II II Author: Gordon Faulds II Acuid Corporation Ltd. II Computer House, Dalkeith Palace, II Dalkeith, Edinburgh, EH22 2NA DK

//

// Simulator: Modelsim 5.6d

//

// Version 0.0 by GJF 06 Jun 2003, original release / working version mix of RTL and Behavioural

//

//

"timescale Ins / lps

module SKEWJTRACKER (CLK , // clock RESET_B , // Global Reset (act L) VALID_IN_ , // compound valid over

SelectorsCount SEL_ , // index to which set of samples to use EN_SDB , // skewed off end of register (sub pipe delay) C EN_ADD ) ; // skewed off end of register (add pipe delay)

//

//

//

//

// PARAMETERS

//

//

ll-// ll Variable // II- -//

parameter valid_width 16; // number of input valid bits parameter selector_width 16; // selector width parameter sel_out_width 4; parameter lock_len 3 parameter add_sub_pipe 2

parameter first_window_wd 9; parameter secnd_window_wd 7;

parameter skew_tracker_del 1;

parameter sk_hist 4 parameter lim_t_out 10000 ;

//parameter mode = 2 bOO ; // VERSION AL2 sh_lock works with this version

//parameter mode = 2 bOl; // VERSION AL3

//parameter mode = 2 bOl; // VERSION AL4 with matched RX_DF parameter mode 2 blO; // VERSION AL5 with matched RX DF ll-// ll derived // II- -//

parameter skew_t_del = valid_width * (skew_tracker_del+l) ; // make behavioural parameter skew hist = valid_width * (sk_hist+l) ; // make behavioural

parameter lock_out = lock len -1; // lockout loop is n+1 cycles

//

// DECLARATIONS _/ ll-// ll 10 // II- -//

input CLK, // clock RESET_B; // Global Reset (act L) C input [valid_width-l : 0] VALID_IN_; // input valid bits

output [sel_out_width-l:0] SEL_; // select output (number) output EN_SϋB, // subtract bit EN ADD; // add bit ll-// ll Registers // II- -//

reg EN 30B, // subtract bit EN ADD; // add bit

reg [valid_width-l:0] val_reg; // latch of valid in reg [valid_width-l:0] clc_reg; reg [valid_width-l:0] clc_com; reg [valid_width-l:0] tmp; reg [sel_out_width-l:0] clc_lim; reg [sel_out_width-l:0] phase__lim;

reg [valid_width-l : :0] first_window_fn; // top layer of and structure reg [skew t del -1: :0] first_window_d; // top layer of and structure reg first_window_bit; // top layer of and structure C reg sh left; reg sh_right;

reg look left; reg look_right;

reg [valid width-1 : :0] selector; // long form select reg [sel_out_width- -1: sel short; // short form select

reg shift left_req, // want to shift sample point left shift_right_req; // want to shift sample point right

reg [lock_out-l: 0] sh lock; // lockout while changes take effect

reg [add_sub_pipe-l: 0] sub_pipe, // delay pipelines add_j?ipe;

// // // Wires // // // // // Variasbles // // //

integer lim_timeout; c C integer i,j,k,l,m,n;

//

// MODULE CALLS / /

//

// PROCESSES

//

/

/ // // Assignments // / //

assign ΞEL_ = sel short; // set output to be selector count

// // // Initial Setup // // //

// // // COMBINATORIAL PROCESSES // // // C always @ (sel_short) begin selector = 16'hOOOl « sel_short; // turn count in to individual selects end

// — // // Find biggest eye // // — //

always @ (val_reg) // on new input begin clc_com = {valid_width{l'bO}}; // clear result word for (l=0;l<valid_width; 1=1+1) // look for begin

tmp = {valid_width{l'bO}}; // clear working word tmp[0] = val_reg[l]; // set to start bit for (j=l; j<valid_width; j=j+1) // check each bit begin tmp[j] = val_reg[ (1+j ) %valid_width] SS tmp[ (j-1) %valid_width] ; // count each contiguous one end clc_com = clc_com | tmp; // note the maximum end end

always @ (clc_reg) begin co clc_lim = { sel_out_width{ 1 ' bO } } ; // turn count in to individual n selects for ( =0 ; k<valid_width; k=k+l ) begin clc_lim = clc_lim + clc_reg[k]; end end ll-// ll CLK PROCESSES // II- -//

always @ ( posedge CLK ) begin val_reg <= VALID IN // latch VALID IN first

clc_reg clc com;

//first_window_d {first_window_d»valid_width} ; // 0 - N pipeline //first window d[skew t del-l:skew t del-valid width] first window fn; // 0 - N pipeline if ( ~RESET_B ) // if reset begin // set defaults sel_short <= 0; sh lock <= 0 ; shift left req <= 0; shift_right_req <= 0; c add_j?ipe <= { add_sub_pipe { 1 ' bO } } ; C sub_j?ipe <= { add_sub_pipe { 1 ' bO } } ; phase lim <= {sel_out_width{ l 'bl} } ; lim_timeout <= lim t out; EN_ADD <= 0; EN_SUB <= 0 ; end else // else begin if (phase_lim>=clc_ _lim) // if eye is smaller or same begin lim_timeout <= lim t out; // reset long integral of eye size phase lim <= (clc_lim >2) ? clc_liιr // reduce eye monitor to size or minimum end else // else eye size bigger

begin if (~ I lim_timeout) // if integral timeout begin lim_timeout <= lim_t_out; // reset integral phase_lim <= phase_lim +1; // increase eye monitor size end else // else begin lim_timeout <= lim timeout-1; // downcount integral end end O ^■^1 case (mode) 2 'b00 : begin // VERSION AL2 sh left 0 ; // set search variables sh_right 0 ; m = 0; // set not found for(i=l; ( (m==0) && (i<=phase_lim/2) ) ;i=i+l) // look in eye monitor region till found begin if(val_reg[ (sel_short+i) %valid_width] != val_reg[ (sel_short-i) %valid_width] ) // check valids right vs left begin // if difference m =1; // set found sh left = val_reg[ (sel_short+i) %valid_width] ; // setup phase move sh_right = val_reg[ (sel_short-i) %valid_width] ; end

end

shift left_req <= sh left; shift_right_req <= sh_right; if ( shift left_req & ~sh_lock[lock_out-l] ) // if shift left begin sel_short <= ( sel_short + 1 ) % 16; // move sample point sh_lock <= ~0; // wait on pipe to update end else // else co begin 00 if ( shift_right_req & ~sh_lock[lock_out-l] ) // if shift right begin sel_short <= ( sel_short - 1 ) % 16; // move sample point sh_lock <= ~0; // wait on pipe to update end else // else begin sh_lock <= { sh_lock[lock_out-2:0] , I'bO }; // shift down lockout for pipe update end end

// generate EN_ADD, EN_ΞUB signs sub_pipe [0] <= shift left_req &

selector [selector_width-l] &~sh__lock[lock_out-l] ; // if shift left at end of register add_j?ipe [0] <= shift_right_req & selector[0] & ~sh lock[lock out-1] ; // if shift right at end of register add_pipe [add_sub_pipe-l : l] <= add_pipe [add_sub_j?ipe-2 : 0] ; // shift pipe delay sub_jpipe [ add_sub_pipe-l : 1 ] <= sub_pipe [ add_sub_pipe-2 : 0 ] ; // shift pipe delay

EN ADD <= add_pipe [add_sub_pipe-l] ; // add pipe output - end of shift add bit EN SUB <= sub_pipe [add_sub_pipe-l] , // sub pipe output - end of shift sub bit end

2 *b01 : begin // VERSION AL3 shift left_req = 0 ; // set search variables shift_right_req = 0; if (val_reg [ (sel_short+phase_lim/2 ) %valid_width] ! = val_reg[ (sel_short-phase_lim/2) %valid_width] ) // check valids right vs left begin // if difference shift left_req = val_reg[ (sel_short+phase_lim/2) %valid_width] ; // setup phase move shift_right_req = val_reg[ (sel_short-phase_lim/2) %valid_width] ; end

//shift left_req <= sh left; //shift_right_req <= sh_right;

if ( shift left_req & ~sh_lock[lock_out-l] ) // if shift left begin sel_short <= ( sel_short + 1 ) % 16; // move sample point //sh_lock <= ~0; // wait on pipe to update end else // else begin if ( shift_right_req & ~sh_lock[lock_out-l] ) // if shift right begin sel_short <= ( sel_short - 1 ) % 16; // move sample point //sh_lock <= ~0; // wait on pipe to update end else // else begin sh_lock <= { sh_lock[lock_out-2:0] , I'bO }; // shift down lockout for pipe update end end

// generate EN_ADD, EN_ΞUB signs sub_pipe[0] <= shift left_req & selector [selector_width-l] &~sh_lock[lock_out-l] ; // if shift left at end of register add_pipe [0] <= shift_right_req & selectorfO] S ~sh lock[lock out-1]; // if shift right at end of register

add_pipe[add_sub_pipe-l:l] <= add_pipe [add_sub_pipe-2 : 0] // shift pipe delay sub_pipe [add_sub_pipe-l:l] <= sub_pipe [add_sub_pipe-2 : 0] // shift pipe delay

EN_ADD <= add_pipe[add_sub_pipe-l] ; // add pipe output - end of shift add bit EN_SUB <= sub_pipe [add_sub_pipe-l] ; // sub pipe output - end of shift sub bit end

2 'blO : begin // VERSION AL5 shift left_req = 0; // set search variables shift_right_req = 0 ; if (val_reg [ ( sel_short+phase_lim/2 ) %valid_width] ! = val_reg [ (sel_short-phase_lim/2) %valid_width] ) // check valids right vs left begin // if difference shift left_req = val_reg [ (sel_short+phase_lim/2) %valid_width] ; // setup phase move shift_right_req = val_reg [ ( sel_short-phase_lim/2) %valid_width] ; end else begin if (~val_reg [sel_short] ) begin shift left_req = val_reg[ (sel_short+l+phase_lim/2) %valid_width] ; // setup phase move shift_right_req = val_reg[ (sel_short-l-phase_lim/2) %valid_width] , end end

//shift left_req <= sh left; //shift_right_req <= sh_right; if ( shift left_req & ~sh_lock[lock_out-l] ) // if shift left begin sel_short <= ( sel_short + 1 ) % 16; // move sample point EN ADD <= I'bO; // add pipe output - end of shift add bit EN SUB <= selector [selector width-1] , // sub pipe output - end of shift sub bit end else // else begin if ( shift_right_req & ~sh_lock[lock_out-l] ) // if shift right begin sel_short <= ( sel_short - 1 ) % 16; // move sample point EN_ADD <= selector[0]; // add pipe output - end of shift add bit EN_SUB <= I'bO; // sub pipe output - end of shift sub bit end else // else begin EN_ADD I'bO; // add pipe output - end of shift add bit EN_ΞUB <= I'bO; // sub pipe output - end of shift sub bit end end

end

2'bll: begin $display("sorry this skew tracker version does not exist ") ; // let folks know your waiting $stop; end default:begin $display ("sorry undefined skew tracker version '); // let folks know your waiting $stop; end O endcase end // else reset b // generate EN_ADD, EN_SUB signs end

//

// SELF CHECKING PROCESSES

//

//

// / // Command Heartbeat // // //

II- II-

// SPECIFY DECLARATIONS //

II-

II- II-

endmodule

//

// ^

Verilog Description (Behavioural) ALX The following Verilog code is the tested and perfected code we now use to implement any of the adaptive trackers AL3/AL4/AL5.

//

// Design unit : Fast skew tracker

//

// Filename: SKEW_TRACKER_ALX.v

//

// Description:

// ^

// This model is an behavioural (m fact almost RTL) representation of the Skew Tracker circuit.

// This is a modified AC52 model, with an ability to dinamically size eyes.

// This model is based on a new algorithm which "runs" from the approaching noise

// This model only looks at two Valids.

// This model combines AL3/4/5 versions in one

//

// Limitations:

"

II 1) architecture is hard coded needs to be changed as soon as we can

II

II Author: Gordon Faulds

// Acuid Corporation Ltd. // Computer House, Dalkeith Palace,

// Dalkeith, Edinburgh, EH22 2NA UK

//

// Simulator: Modelsim 5.6d

//

// Version 0.0 by GJF 06 Jun 2003, original release / working version mix of RTL and Behavioural

//

//

//

'timescale Ins / lps

module SKEW TRACKER (CLK // clock RESET_B // Global Reset (act L) VALID_IN_ // compound valid over SelectorsCount SEL_ // index to which set of samples to use EN_SUB // skewed off end of register (sub pipe delay) EN ADD // skewed off end of register (add pipe 4^ delay) CD

ll¬

ll

II-

II-

II PARAMETERS

II-

II-

ll-// ll Variable // II- -//

parameter valid_width 16; // number of input valid bits parameter selector_width 16; // selector width parameter sel_out_width 4; para eter lock_len 3 parameter add_sub_pipe 1

parameter first_window_wd 9; parameter secnd_window_wd 7; 4^ parameter skew_tracker 3el 1; parameter skew__tracker_al5 0; // if real time 1 = add panic algorithm

parameter sk_hist 4; parameter lim_t_out 10000; ll-// ll derived // II- -//

parameter skew_t_del = valid_width * (skew_tracker_del+l) // make behavioural parameter skew hist = valid_width * (sk_hist+l) ; // make behavioural

parameter lock_out = lock len -1; // lockout loop is n+1 cycles

//

/

// DECLARATIONS

/

_// ll-// ll 10 // II- -//

input CLK, // clock RESET_B; // Global Reset (act L) input [valid_width-l: 0] VALID_IN_ // input valid bits output [ sel_out_width-l : 0 ] SEL_; // select output (number) 4^ 00 output EN_SUB, // subtract bit EN ADD; // add bit

II -// II Registers // II -//

reg [valid_width-l: 0] val reg; // latch of valid in reg [valid_width-l: 0] clc_reg; reg [valid_width-l:0] clc_com; reg [valid_width-l:0] tmp; reg [sel_out_width-l:0] clc_lim; reg [sel out width-l:0] phase_lim;

reg [valid_width-l:0] selector; // long form select reg [sel_out_width-l:0] sel_short; // short form select

reg shift left_req; // want to shift sample point left reg shift_right_req; // want to shift sample point right

reg [ add_sub_pipe-l : 0 ] sub pipe; // delay pipelines reg [add_sub_pipe-l : 0] add__jpipe ; ll-// ll Wires // II -// C wire EN_SUB; // subtract bit wire EN ADD; // add bit ll-// ll Variasbles // II- -//

integer lim_timeout; integer i, j,k,l,m,n;

II- II- II MODULE CALLS

II- II- _/

// PROCESSES

/ <-

// -.

/ // // Assignments // / // Ol O assign SEL_ sel_short; // set output to be selector count assign EN_ADD add_pipe[add_sub_ )ipe-l] ; // add pipe output - end of shift add bit assign EN_SUB sub_pipe[add_sub_pipe-l] ; // sub pipe output - end of shift sub bit

// // // Initial Setup // // //

/ // // COMBINATORIAL PROCESSES // // //

always §(sel_short) begin selector = 16'h0001 « sel_short; // turn count in to individual selects end

// — // // Find biggest eye // // — //

always @ (val_reg) // on new input begin clc_com = {valid_width{l'bO}}; // clear result word Ui for (l=0;l<valid_width; 1=1+1) // look for begin tmp = {valid_width{l'bO}}; // clear working word tmp[0] = val_reg[l]; // set to start bit for (j=l; j<valid_width; j=j+l) // check each bit begin tmp[j] = val_reg[ (1+j) %valid_width] && tmp[ (j-1) %valid_width] ; // count each contiguous one end clc_com = clc_com | tmp; // note the maximum end end

always @(clc_reg) begin

clc_lim = {sel_out_width{l'bO}}; // turn count in to individual selects for (k=0; k<valid_width; k=k+l) begin clc_lim = clc_lim + clc_reg[k]; end end ll-// ll CLK PROCESSES // II- -//

always @ ( posedge CLK ) begin val_reg <= VALID_IN_ // latch VALID IN first Oi clc_reg <= clc_com; if ( ~RESET_B ) // if reset begin // set defaults sel_short <= 0; shift left_req <= 0; shift_right_req <= 0; add_pipe <= {add_sub_pipe { 1 'bO} } ; sub_pipe <= {add_sub_pipe{l'bO}}; phase_lim <= {sel_out_width{l'bl}}; lim_timeout <= lim t out; end else // else

begin if (phase_lim>=clc_lim) // if eye is smaller or same begin lim_timeout <= lim_t_out; // reset long integral of eye size phase_lim <= (clc lim >2) ? clc lim {{sel out width-2{l'bO}},2'blO}; // reduce eye monitor to size or minimum end else // else eye size bigger begin if(~ I lim_timeou ) // if integral timeout begin lim_timeout <= lim_t_out; // reset integral phase_lim <= phase_lim +1; // increase eye monitor size end Oi CO else // else begin lim_timeout <= lim timeout-1; // downcount integral end end

// implement selector shifts shift left_req = 0; // set search variables shift_right_req = 0; if (val_reg[ (sel_short+phase_lim/2) %valid_width] != val_reg[ (sel_short-phase_lim/2) %valid_width] ) // check valids right vs left begin // if difference shift left_req = val_reg[ (sel_short+phase_lim/2) %valid_width] ; // setup phase move shift_right_req = val_reg[ (sel_short-phase_lim/2) %valid_width] ;

end else begin if(~val_reg[sel_short] && skew_tracker_al5) // if going to sample rubbish & feature on begin if (val_reg[ (sel_short+l+phase_lim/2) %valid_width] != val_reg[ (sel_short-l-phase_lim/2) %valid_width] ) begin shift left_req = val_reg[ (sel_short+l+phase_lim/2) %valid_width] ; // setup phase move if there is one shift_right_req = val_reg[ (sel_short-l-phase_lim/2) %valid_width] ; end end end 4^ if ( shift left_req) // if shift left begin sel_short ( sel short + 1 ) % 16; // move sample point end else // else begin if { shift_right_req) // if shift right begin sel_short <= ( sel short - 1 ) % 16; // move sample point end else // else begin sel_short <= sel_short; end

end end // generate EN_ADD, EN_SUB signs sub_pipe <= {sub_pipe, shift left_req & selector[selector_width-l] } ; // if shift left at end of register add_pipe <= {addjpipe, shift_right_req & selector [0] } ; // if shift right at end of register

end /

//

// SELF CHECKING PROCESSES

//

// // // Command Heartbeat // // /

//

/

// SPECIFY DECLARATIONS

//

/ endmodule

// /

Claims

WHAT IS CLAIMED IS: 1. A high speed receiver for receiving an input signal, comprising - a sampling system producing a series of sampled values of the received signal, so that each bit interval is covered by several samples; - a pattern analyser which analyses the sampled pattern and expands each set of neighbouring identical samples to a predetermined required pulse width; - a logic circuit operating on the expanded set of samples to produce a data signal (Q) and a valid sample signal (E) indicative of the number of the valid sample in the set of samples; - a controller, which calculates the current eye width, and, using the said valid sample signal obtained from the logic circuit, defines the current eye centre and its offset with respect to half width of the bit interval; wherein the said offset signal is further applied to said data signal to produce a recovered data.

2. A receiver according to claim 1 , wherein the system is provided with a polyphase clock generator generating clocks for spreading said samples in time.

3. A receiver according to claim 1 or 2, wherein, if a next set of samples starts with the sample bit value, same to the last bit value of the previous set, the two sets of samples are processed as a single bit.

4. A receiver according to any one of claims 1 to 3, wherein the data signal (Q) and a valid sample signal (E) are produced by majority logic.

5. A receiver according to any one of claims 1 to 4, wherein the controller calculates the eye width as the longest string of identical samples.

6. A receiver according to any one of claims 1 to 5, wherein the offset signal is applied to a multiplexor which selects which sample of n samples per bit is used to define the data.

7. A receiver according to any one of claims 1 to 6, wherein the eye is expanded by passing the valid sample value to a register representing the value of the data for the whole symbol period.

8. A receiver according to any one of claims 1 to 7, wherein the controller integrates data to determine the minimum eye aperture over a prolonged period.

9. A receiver according to any one of claims 1 to 8, wherein the controller finds the longest sequence of identical sample values in the valid samples for each cycle and then determines the shortest sequence.

10. A receiver according to claim any one of claims 1 to 9, wherein the data samples are delayed to align with the offset signal derived from those data samples.

11.A method of data processing, comprising the steps of: - oversampling data to provide a set of sampled bit values of the received signal, which are spaced in time so that each bit interval is covered by several samples; - analysing the sampled pattern and selecting at least one signal sample or a set of identical neighbouring samples, - expanding the set of identical neighbouring samples to a predetermined required pulse width; - processing the expanded sets of samples to produce a data signal and a valid sample signal indicative of the number of the valid sample in the set of samples; - calculating the current eye width and detecting the centre of the eye by using the number of the valid sample in the set of samples and defining its offset with respect to half width of the bit interval; - applying the obtained offset to said data signal to produce a recovered data.

12. A method of data processing according to claim 11 , wherein the pattern analysis is performed by comparing each bit with its neighboring bits.

13. A method of data processing according to claim 11 or 12, wherein, if a next set of samples starts with the sample bit value, same to the last bit value of the previous set, the two sets of samples are processed as a single bit.

14. A method of data processing according to any one of claims 11 to 13, wherein the set of samples is expanded by assigning the value of the selected sample to the whole symbol interval.

15. A method of data processing according to any one of claims 11 to 14, wherein the centre of the eye is detected by applying a search from the current selection outwards to the second window limits.

16. A method of data processing according to any one of claims 11 to 15, wherein the selection is moved away from the invalid first window of the first encountered asymmetric pair.

17. A method of data processing according to any one of claims 11 to 16, wherein the knowledge of the previous sample is used when selecting the next sample from the set of samples for the next symbol interval.

18. A method of data processing according to any one of claims 11 to 17, wherein the analysis and selection is performed by using a pattern based eye expanding program.

19. A method of data processing according to any one of claims 11 to 18, wherein the analysis and selection is performed by using a table or encoded table of possible valid data states or transitions.

20. A method of data processing according to any one of claims 11 to 19, wherein the table values are approximated and fixed into the design.

21. A method of data processing according to any one of claims 11 to 20, wherein the table values are determined by a sequence of a training pulse.

22. A method of data processing according to any one of claims 11 to 21 , wherein the two samples are selected that define the outer limit of the stable eye to use for eye tracking.

23. A method of data processing according to any one of claims 11 to 22, wherein the eye width is calculated as the longest string of identical samples.

24. A method of data processing according to any one of claims 11 to 23, wherein the subsequent set of samples is repositioned using the above defined offset of the eye.

25. A method of data processing according to any one of claims 11 to 24, wherein the valid data is a minority of the sampled bits values.