WO2005088424A3 - Calibration of clock generators in system-on-chip integrated circuits - Google Patents

Calibration of clock generators in system-on-chip integrated circuits Download PDF

Info

Publication number
WO2005088424A3
WO2005088424A3 PCT/IB2005/050726 IB2005050726W WO2005088424A3 WO 2005088424 A3 WO2005088424 A3 WO 2005088424A3 IB 2005050726 W IB2005050726 W IB 2005050726W WO 2005088424 A3 WO2005088424 A3 WO 2005088424A3
Authority
WO
WIPO (PCT)
Prior art keywords
signature
calibration
resultant
integrated circuits
flops
Prior art date
Application number
PCT/IB2005/050726
Other languages
French (fr)
Other versions
WO2005088424A2 (en
Inventor
Vishal S Choudhary
Atul Katoch
Original Assignee
Koninkl Philips Electronics Nv
Vishal S Choudhary
Atul Katoch
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Vishal S Choudhary, Atul Katoch filed Critical Koninkl Philips Electronics Nv
Publication of WO2005088424A2 publication Critical patent/WO2005088424A2/en
Publication of WO2005088424A3 publication Critical patent/WO2005088424A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Abstract

In a GALS based integrated circuit, the ring oscillator (400) with a programmable delay line (500), which can be configured for different delays using a control word (600). Scan patterns are loaded into the N modules at the respective launching flip-flops (100) and the resultant signal value captured by the capture flip-flops is output to a register (700). The resultant signature of values is compared with a valid signature (800). If it does not match, the delay of the ring oscillator (400) is changed by the control word (600), and the path delay test is carried out again. This process is repeated until the resultant signature (700) matches the valid signature (800) at which time, the calibration process is complete.
PCT/IB2005/050726 2004-03-10 2005-02-28 Calibration of clock generators in system-on-chip integrated circuits WO2005088424A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04100981 2004-03-10
EP04100981.2 2004-03-10

Publications (2)

Publication Number Publication Date
WO2005088424A2 WO2005088424A2 (en) 2005-09-22
WO2005088424A3 true WO2005088424A3 (en) 2006-03-02

Family

ID=34960836

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2005/050726 WO2005088424A2 (en) 2004-03-10 2005-02-28 Calibration of clock generators in system-on-chip integrated circuits

Country Status (1)

Country Link
WO (1) WO2005088424A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7765382B2 (en) 2007-04-04 2010-07-27 Harris Corporation Propagating reconfiguration command over asynchronous self-synchronous global and inter-cluster local buses coupling wrappers of clusters of processing module matrix
US8558626B2 (en) 2008-11-24 2013-10-15 Freescale Semiconductor, Inc. Method and apparatus for generating a clock signal
EP2369438B1 (en) 2010-02-24 2014-02-26 Fujitsu Semiconductor Limited Calibration method of a real time clock signal
US8472278B2 (en) 2010-04-09 2013-06-25 Qualcomm Incorporated Circuits, systems and methods for adjusting clock signals based on measured performance characteristics
US8954017B2 (en) * 2011-08-17 2015-02-10 Broadcom Corporation Clock signal multiplication to reduce noise coupled onto a transmission communication signal of a communications device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5870404A (en) * 1996-08-08 1999-02-09 International Business Machines Corporation Self-timed circuit having critical path timing detection
US6058252A (en) * 1995-01-19 2000-05-02 Synopsys, Inc. System and method for generating effective layout constraints for a circuit design or the like
US6404233B1 (en) * 1997-12-11 2002-06-11 Intrinsity, Inc. Method and apparatus for logic circuit transition detection
US6625788B1 (en) * 1998-06-26 2003-09-23 Xilinx, Inc. Method for verifying timing in a hard-wired IC device modeled from an FPGA

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6058252A (en) * 1995-01-19 2000-05-02 Synopsys, Inc. System and method for generating effective layout constraints for a circuit design or the like
US5870404A (en) * 1996-08-08 1999-02-09 International Business Machines Corporation Self-timed circuit having critical path timing detection
US6404233B1 (en) * 1997-12-11 2002-06-11 Intrinsity, Inc. Method and apparatus for logic circuit transition detection
US6625788B1 (en) * 1998-06-26 2003-09-23 Xilinx, Inc. Method for verifying timing in a hard-wired IC device modeled from an FPGA

Also Published As

Publication number Publication date
WO2005088424A2 (en) 2005-09-22

Similar Documents

Publication Publication Date Title
TW200717239A (en) Semiconductor integrated circuit device
WO2007117745A3 (en) Apparatus and method for adjusting an operating parameter of an integrated circuit
TW200728747A (en) Semiconductor integrated circuit, and designing method and testing method thereof
US9547043B2 (en) Test control point insertion and X-bounding for logic built-in self-test (LBIST) using observation circuitry
WO2005088424A3 (en) Calibration of clock generators in system-on-chip integrated circuits
TW200732686A (en) IC testing methods and apparatus
ATE362177T1 (en) METHOD AND CIRCUIT FOR THE TIME ADJUSTMENT OF THE CONTROL SIGNALS IN A MEMORY MODULE
TW200703176A (en) Shift register circuit and drive control apparatus
WO2008112207A3 (en) Software programmable timing architecture
TW200721673A (en) Semiconductor integrated circuit
JP4272515B2 (en) Phase correction circuit
WO2007102872A3 (en) Compositions and methods related to controlled gene expression using viral vectors
JP2007108172A (en) Apparatus for measuring on-chip characteristics of semiconductor circuit, and method therefor
WO2008024659A3 (en) Circuits to delay a signal from a memory device
ATE443268T1 (en) TESTING A CIRCUIT WITH ASYNCHRONOUS TIMER
TW200641568A (en) A digital time constant tracking technique and apparatus
GB9809762D0 (en) Test chip circuit for on-chip timing characterization
ATE476670T1 (en) TIMING GENERATOR AND SEMICONDUCTOR TESTING DEVICE
WO2001073457A3 (en) Controllable and testable oscillator apparatus for an integrated circuit
TW200631025A (en) Method and system for timing measurement of embedded macro module
US6650162B2 (en) Digital clock generator circuit with built-in frequency and duty cycle control
WO2004042786A3 (en) High-frequency scan testability with low-speed testers
US8432181B2 (en) Method and apparatus for reconfigurable at-speed test clock generator
DE602005014264D1 (en) ADAPTIVE MEMORY CALIBRATION USING BINS
DE10318603B4 (en) Input reception circuit for weak high speed signal for generating several output signals, which can be processed at lower detecting speed

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

WWW Wipo information: withdrawn in national office

Country of ref document: DE

122 Ep: pct application non-entry in european phase