WO2005078690A3 - Power optimised display architecture and driving method - Google Patents

Power optimised display architecture and driving method Download PDF

Info

Publication number
WO2005078690A3
WO2005078690A3 PCT/BE2005/000021 BE2005000021W WO2005078690A3 WO 2005078690 A3 WO2005078690 A3 WO 2005078690A3 BE 2005000021 W BE2005000021 W BE 2005000021W WO 2005078690 A3 WO2005078690 A3 WO 2005078690A3
Authority
WO
WIPO (PCT)
Prior art keywords
display panel
display
driving method
maximally
processing means
Prior art date
Application number
PCT/BE2005/000021
Other languages
French (fr)
Other versions
WO2005078690A2 (en
Inventor
Francky Catthoor
Andy Dewilde
Lieven Hollevoet
Original Assignee
Imec Inter Uni Micro Electr
Francky Catthoor
Andy Dewilde
Lieven Hollevoet
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imec Inter Uni Micro Electr, Francky Catthoor, Andy Dewilde, Lieven Hollevoet filed Critical Imec Inter Uni Micro Electr
Priority to EP05706372A priority Critical patent/EP1714208A2/en
Publication of WO2005078690A2 publication Critical patent/WO2005078690A2/en
Publication of WO2005078690A3 publication Critical patent/WO2005078690A3/en
Priority to US11/504,824 priority patent/US20070188506A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/04—Partial updating of the display screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Graphics (AREA)
  • Computer Hardware Design (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

The invention relates to a display system for displaying information and a method for displaying. The system comprises a processing means and a display unit with a display panel. On the image data processing path for transferring information to the display panel the number of writable memory components external to the display panel is limited to maximally one. The maximally one writable memory component is adapted to comprise at least a single image frame. The systems and methods allow to reduce the power consumption based on reduction of the number of memory accesses. Furthermore, a method and system is provided wherein updating of pixel information is performed content dependent. Moreover, a system is provided wherein the display panel is connected to the processing means using a separate, dedicated display bus.
PCT/BE2005/000021 2004-02-13 2005-02-14 Power optimised display architecture and driving method WO2005078690A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP05706372A EP1714208A2 (en) 2004-02-13 2005-02-14 Power optimised display architecture and driving method
US11/504,824 US20070188506A1 (en) 2005-02-14 2006-08-11 Methods and systems for power optimized display

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0403233.0 2004-02-13
GB0403233A GB0403233D0 (en) 2004-02-13 2004-02-13 A power optimized display system

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/504,824 Continuation US20070188506A1 (en) 2005-02-14 2006-08-11 Methods and systems for power optimized display

Publications (2)

Publication Number Publication Date
WO2005078690A2 WO2005078690A2 (en) 2005-08-25
WO2005078690A3 true WO2005078690A3 (en) 2005-10-06

Family

ID=32011870

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/BE2005/000021 WO2005078690A2 (en) 2004-02-13 2005-02-14 Power optimised display architecture and driving method

Country Status (3)

Country Link
EP (1) EP1714208A2 (en)
GB (1) GB0403233D0 (en)
WO (1) WO2005078690A2 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0884715A1 (en) * 1997-06-12 1998-12-16 Hewlett-Packard Company Single-chip chipset with integrated graphics controller
US20010011988A1 (en) * 1993-08-30 2001-08-09 Makiko Ikeda Liquid crystal display with liquid crystal driver having display memory
EP1207511A1 (en) * 2000-03-30 2002-05-22 Seiko Epson Corporation Display
US20020140642A1 (en) * 2001-01-18 2002-10-03 Shigetsugu Okamoto Memory-integrated display element
EP1253578A1 (en) * 2000-10-26 2002-10-30 Matsushita Electric Industrial Co., Ltd. Image display apparatus
US6597329B1 (en) * 1999-01-08 2003-07-22 Intel Corporation Readable matrix addressable display system

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010011988A1 (en) * 1993-08-30 2001-08-09 Makiko Ikeda Liquid crystal display with liquid crystal driver having display memory
EP0884715A1 (en) * 1997-06-12 1998-12-16 Hewlett-Packard Company Single-chip chipset with integrated graphics controller
US6597329B1 (en) * 1999-01-08 2003-07-22 Intel Corporation Readable matrix addressable display system
EP1207511A1 (en) * 2000-03-30 2002-05-22 Seiko Epson Corporation Display
EP1253578A1 (en) * 2000-10-26 2002-10-30 Matsushita Electric Industrial Co., Ltd. Image display apparatus
US20020140642A1 (en) * 2001-01-18 2002-10-03 Shigetsugu Okamoto Memory-integrated display element

Also Published As

Publication number Publication date
EP1714208A2 (en) 2006-10-25
WO2005078690A2 (en) 2005-08-25
GB0403233D0 (en) 2004-03-17

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