WO2005074134A1

WO2005074134A1 - A delay circuit

Info

Publication number: WO2005074134A1
Application number: PCT/IB2005/050227
Authority: WO
Inventors: Francesco Pessolano
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2004-01-28
Filing date: 2005-01-19
Publication date: 2005-08-11

Abstract

A delay circuit comprising first and second transistors (Ml, M2), the gate of each of which being coupled to the input (or 'PRE') signal. The drain of the second transistor (M2) is connected to the supply voltage VDD and its source is coupling to the drain of the first transistor (M1). A third transistor (MO) is provided, the input signal (PRE) being coupled to its gate via an inverter (10). The drain of transistor (MO) is connected at a point between the source of transistor (M2) and the drain of transistor (M I), and the source of transistor (MO) is connected to ground. A capacitor (CO) is connected between the source of transistor (M1) and ground, and a buffer (20) is provided at the output (TIMER). The function of this arrangement is to propagate with delay the transitions from the PRE signal to the TIMER signal. The rising transition is propagated very fast, the speed of propagation being equal to the charging time of capacitor (CO) through the two conducting transistors (M1, M2). The falling transition, on the other hand, is propagated with a large delay as it is equal to the charging time of the capacitor through a conducting transistor (MO) and a transistor in sub-threshold (Ml).

Description

A DELAY CIRCUIT

This invention relates to a delay circuit for use in an integrated circuit to delay output of an input signal, the delay circuit comprising a capacitive element arranged to be charged and discharged in response to the respective rising and falling edges of the input signal.

There are many circumstances in which it is required to employ a delay element in a digital integrated circuit. For example, such an element may be used to slow down a signal that is used as a reference for periodic operations, or to enable two signals to be synchronized. In the past, a delay element may have been implemented by means of cascaded logic gates for small delays or counters for very large delays. However, these techniques result in a very large overhead, especially where large delays are required to be achieved. We have now devised an improved arrangement.

In accordance with the present invention, there is provided a delay circuit for use in an integrated circuit to delay output of an input signal, the delay circuit comprising a capacitive element arranged to be charged and discharged in response to the respective rising and falling edges of the input signal, wherein said input signal is coupled to said capacitive element via a component which has a relatively low impedance during charging of said capacitive element and a relatively high impedance during discharging of said capacitive element. In a preferred embodiment, charging of said capacitive element is effected by the rising edge of said input signal and discharging of said capacitive element is effected by the falling edge of said input signal. Thus, the function of the delay circuit defined above is to propagate with delay the transition from the input (or 'pre') signal to the output (timer) signal. The propagation is asymmetric, in the sense that the rising transition is propagated relatively quickly, whereas the falling transition is propagated with a large delay, thereby enabling very large delays to be generated with a relatively small circuit area overhead. Furthermore, the scheme is also sensitive to process and working conditions just like the rest of the system, such that the delay is able to adapt in the same manner as the rest of the system. Preferably, the component comprises a transistor arranged and configured to be conducting during charging of the capacitive element, and in sub-threshold during discharging of the capacitive element. In a preferred embodiment, a buffer is provided, preferably with a relatively steep functional characteristic, at the output of the delay circuit so as to create an output (or timer) signal as close as possible to the original input ('pre') signal in the falling transition. A symmetric delay element (with substantially equal delay in both the falling and rising transitions) can be provided by including first and second delay circuits as defined above, the input signal being connected to the second delay circuit via a first inverter, and the output of the capacitive element of the second delay circuit being connected to the output via a second inverter. Thus, depending on the value of the input signal (i.e. either rising or falling), either the first or second delay circuit is connected to the output. Beneficially, a buffer is provided between the input signal and the inputs of the delay circuits, so as to allow the output multiplexer to switch before the circuits themselves receive a new input. This is preferable so as to avoid any possible glitch on the output signal. The invention further extends to an integrated circuit including at least one delay circuit as defined above, and to a method of manufacturing such an integrated circuit. These and other aspects of the present invention will be apparent from, and elucidated with reference to, the embodiments described hereinafter.

Embodiments of the present invention will now be described by way of examples only and with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram illustrating a delay circuit according to a first exemplary embodiment of the present invention; and Fig. 2 is a schematic block diagram illustrating a delay circuit according to a second exemplary embodiment of the present invention. There are many circumstances in which it is required to employ a delay element in a digital integrated circuit. For example, such an element may be used to slow down a signal that is used as a reference for periodic operations, or to enable two signals to be synchronized. In the past, a delay element may have been implemented by means of cascaded logic gates for small delays or counters for very large delays. However, these techniques result in a very large overhead, especially where large delays are required to be achieved. US Patent No. 5,051,630 describes a delay generator circuit for delaying the rising and falling edges of an input signal. The described arrangement includes a current switch having two inputs with respective transistors coupled thereto, and an output. A voltage generator is coupled to the gate of each transistor to provide constant voltages independent of V_DD and ground from the gate to the source of each transistor. The output of the current switch is coupled to a capacitor which is caused to charge in response to the rising edge of the signal and discharge in response to the falling edge of the signal, and an output inverter stage is coupled to the output of the current switch to provide the delayed signal. The constant gate to source voltages of the transistors provide relatively constant charge and discharge currents to the capacitor, that in turn produce a relatively constant delay for both the rising and the falling edge of the input signal. European Patent Application No. 0735453 describes a similar arrangement in which a constant current source is provided when the input to the circuit is high, and is applied to a capacitor. The constant current causes the capacitor to be charged when the input voltage is high, and the capacitor discharges when the input voltage is low. Referring to Fig. 1 of the drawings, a delay circuit according to a first exemplary embodiment of the present invention comprises first and second transistors Ml, M2, the gate of each of which being coupled to the input (or 'PRE') signal. The drain of the second transistor M2 is connected to the supply voltage VD_D and its source is coupled to the drain of the first transistor Ml. A third transistor M0 is also provided, the input signal PRE being coupled to its gate via an inverter 10. The drain of transistor M0 is connected at a point between the source of transistor M2 and the drain of transistor Ml, and the source of transistor M0 is connected to ground. A capacitor CO is connected between the source of transistor Ml and ground, and a buffer 20 is provided at the output (TIMER). The embodiment illustrated in Fig. 1 of the drawings implements an asymmetric delay element. The function of this arrangement is to propagate with delay the transitions from the PRE signal to the TIMER signal. The propagation delay is asymmetric. The rising transition is propagated very fast, the speed of propagation being equal to the charging time of capacitor CO through the two conducting transistors Ml and M2. The falling transition, on the other hand, is propagated with a large delay as it is equal to the charging time of the capacitor through a conducting transistor MO and a transistor in sub-threshold Ml. Thus, the present invention as described with reference to the exemplary embodiment illustrated in Fig. 1 is based on the idea of generating a delay by means of a charged capacitor discharging through a transistor in sub-threshold condition. Since such a discharging time is significantly longer than in known arrangements, this mechanism permits the generation relatively very large delays with a relatively small circuit area overhead. A buffer 20 is provided at the output, the buffer being designed to have a very steep functional characteristic so as to provide a TIMER signal in the falling transition which is substantially the same as the input (PRE) signal. The embodiment described above employs the inventive concept of the invention in the falling transition. However, referring to Fig. 2 of the drawings, a symmetric delay element (with equal delay on both rising and falling transitions) can be provided by combining two of the asymmetric delay elements as described with reference to Fig. 1. These two elements are labeled in Fig. 2 as A and B. Element A is the same as that described with reference to Fig. 1. Element B is also the same, but includes an inverter 30 at its input, and another inverter 40 at its output. Thus, depending upon the value of the input signal IN, either element A or element B is connected to the output signal OUT. In the example shown, element A is connected to propagate a delayed falling transition, whereas element B is connected to propagate a delayed rising transition. The inverters 30, 40 are used to ensure that the output of element B has the correct polarity. A buffer 50 connected between the signal IN and the input to the elements A and B is provided so as to allow the output multiplexer to switch before the elements themselves receive a new input and avoid any possible glitch on the OUT signal. As explained above, the present invention enables the generation of relatively very large delays with a very small circuit area overhead. In addition, the scheme is also sensitive to process and working conditions, just like the rest of the system, so the delay mechanism can adapt in the same manner as the rest of the system. It should be noted that the above-mentioned embodiment illustrates rather than limits the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims. In the claims, any reference signs placed in parentheses shall not be construed as limiting the claims. The word "comprising" and "comprises", and the like, does not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole. The singular reference of an element does not exclude the plural reference of such elements and vice-versa. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:

1. A delay circuit for use in an integrated circuit to delay output of an input signal (PRE), the delay circuit comprising a capacitive element (C0) arranged to be charged and discharged in response to the respective rising and falling edges of the input signal, wherein said input signal is coupled to said capacitive element (C0) via a component (Ml) which has a relatively low impedance during charging of said capacitive element (C0) and a relatively high impedance during discharging of said capacitive element (C0).

2. A delay circuit according to claim 1, wherein charging of said capacitive element (C0) is effected by the rising edge of said input signal, and discharging of said capacitive element (C0) is effected by the falling edge of said signal.

3. A delay circuit according to claim 1 or claim 2, wherein said component (Ml) comprises a transistor arranged and configured to be conductive during charging of said capacitive element (C0), and in sub-threshold during discharging of said capacitive element (C0).

4. A delay circuit according to any one of claims 1 to 3, wherein a buffer (20) is provided at the output of said delay circuit.

5. A delay circuit according to claim 4, wherein said buffer (20) has a relatively steep functional characteristic.

6. A delay module, comprising first and second delay elements (A, B) according to any one of claims 1 to 5, the module being arranged and configured such that either said first (A) or said second (B) delay circuit is connected to an output of said module, depending upon the value of said input signal.

7. A delay module according to claim 6, wherein said input signal is coupled to said second delay circuit (B) via an inverter (30).

8. A delay module according to claim 7, wherein an output of said second delay circuit (B) is connected to an output of said module via an inverter (40).

9. A delay module according to any one of claims 6 to 8, wherein said input signal is coupled to the inputs of the delay circuits (A, B) via a buffer (50).

10. An integrated circuit including at least one delay circuit according to any one of claims 1 to 5 or a delay module according to any one of claims 6 to 9.

11. A method of manufacturing an integrated circuit according to claim 10, including the step of providing a delay circuit according to any one of claims 1 to 5, or a delay module according to any one of claims 6 to 9.