WO2005072058A3 - A method and apparatus for addressing in mass storage non-volatile memory devices - Google Patents

A method and apparatus for addressing in mass storage non-volatile memory devices Download PDF

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Publication number
WO2005072058A3
WO2005072058A3 PCT/IL2005/000110 IL2005000110W WO2005072058A3 WO 2005072058 A3 WO2005072058 A3 WO 2005072058A3 IL 2005000110 W IL2005000110 W IL 2005000110W WO 2005072058 A3 WO2005072058 A3 WO 2005072058A3
Authority
WO
WIPO (PCT)
Prior art keywords
addressing
volatile memory
memory devices
mass storage
storage non
Prior art date
Application number
PCT/IL2005/000110
Other languages
French (fr)
Other versions
WO2005072058A2 (en
Inventor
Marcelo Krygier
Original Assignee
Infineon Technologies Flash
Marcelo Krygier
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Flash, Marcelo Krygier filed Critical Infineon Technologies Flash
Publication of WO2005072058A2 publication Critical patent/WO2005072058A2/en
Publication of WO2005072058A3 publication Critical patent/WO2005072058A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration

Abstract

An apparatus and method to determine an addressing mode is disclosed. The method uses one or more unused bits of an address argument of a command as an addressing mode field to determine whether the address argument is a byte address argument or a block address argument.
PCT/IL2005/000110 2004-01-29 2005-01-30 A method and apparatus for addressing in mass storage non-volatile memory devices WO2005072058A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/766,320 2004-01-29
US10/766,320 US20050172064A1 (en) 2004-01-29 2004-01-29 Method and apparatus for addressing in mass storage non-volatile memory devices

Publications (2)

Publication Number Publication Date
WO2005072058A2 WO2005072058A2 (en) 2005-08-11
WO2005072058A3 true WO2005072058A3 (en) 2006-06-22

Family

ID=34807584

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IL2005/000110 WO2005072058A2 (en) 2004-01-29 2005-01-30 A method and apparatus for addressing in mass storage non-volatile memory devices

Country Status (2)

Country Link
US (1) US20050172064A1 (en)
WO (1) WO2005072058A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7231467B2 (en) * 2003-11-17 2007-06-12 Agere Systems Inc. Method and apparatus for providing an inter integrated circuit interface with an expanded address range and efficient priority-based data throughput
US7502908B2 (en) * 2006-05-04 2009-03-10 International Business Machines Corporation Method for providing an address format compatible with different addressing formats used for addressing different sized address spaces
US11003376B2 (en) * 2019-09-13 2021-05-11 Toshiba Memory Corporation Reconfigurable SSD storage pool

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6647428B1 (en) * 2000-05-05 2003-11-11 Luminous Networks, Inc. Architecture for transport of multiple services in connectionless packet-based communication networks
US20050073884A1 (en) * 2003-10-03 2005-04-07 Gonzalez Carlos J. Flash memory data correction and scrub techniques

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3652836A (en) * 1968-03-22 1972-03-28 Hughes Aircraft Co Navigation director system
US4131881A (en) * 1977-09-12 1978-12-26 Robinson Paul B Communication system including addressing apparatus for use in remotely controllable devices
JPH06500655A (en) * 1990-10-03 1994-01-20 スィンキング　マシンズ　コーポレーション parallel computer system
US5388233A (en) * 1993-04-30 1995-02-07 Intel Corporation Method and apparatus for counting instruction types using bit masks and a programmable bit map
US6047352A (en) * 1996-10-29 2000-04-04 Micron Technology, Inc. Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure
US6192463B1 (en) * 1997-10-07 2001-02-20 Microchip Technology, Inc. Processor architecture scheme which uses virtual address registers to implement different addressing modes and method therefor
JP2002043427A (en) * 2000-07-21 2002-02-08 Mitsubishi Electric Corp Trimming method of semiconductor device, trimming system of semiconductor device and method for creating trimming table of semiconductor device
US20050055479A1 (en) * 2002-11-21 2005-03-10 Aviad Zer Multi-module circuit card with inter-module direct memory access

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6647428B1 (en) * 2000-05-05 2003-11-11 Luminous Networks, Inc. Architecture for transport of multiple services in connectionless packet-based communication networks
US20050073884A1 (en) * 2003-10-03 2005-04-07 Gonzalez Carlos J. Flash memory data correction and scrub techniques

Also Published As

Publication number Publication date
WO2005072058A2 (en) 2005-08-11
US20050172064A1 (en) 2005-08-04

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