WO2005071722B1 - Selective etch of films with high dielectric constant - Google Patents

Selective etch of films with high dielectric constant

Info

Publication number
WO2005071722B1
WO2005071722B1 PCT/US2005/001073 US2005001073W WO2005071722B1 WO 2005071722 B1 WO2005071722 B1 WO 2005071722B1 US 2005001073 W US2005001073 W US 2005001073W WO 2005071722 B1 WO2005071722 B1 WO 2005071722B1
Authority
WO
WIPO (PCT)
Prior art keywords
dielectric constant
high dielectric
etching
etchant gas
constant layer
Prior art date
Application number
PCT/US2005/001073
Other languages
French (fr)
Other versions
WO2005071722A1 (en
Inventor
Shyam Ramalingam
Gowri Kota
Chris Lee
Original Assignee
Lam Res Corp
Shyam Ramalingam
Gowri Kota
Chris Lee
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Res Corp, Shyam Ramalingam, Gowri Kota, Chris Lee filed Critical Lam Res Corp
Publication of WO2005071722A1 publication Critical patent/WO2005071722A1/en
Publication of WO2005071722B1 publication Critical patent/WO2005071722B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3

Abstract

A method for selectively etching a high dielectric constant layer over a silicon substrate is provided. The silicon substrate is placed into an etch chamber. An etchant gas is provided into the etch chamber, where the etchant gas comprises BCl3, an inert diluent, and Cl2, where the flow ratio of the inert diluent to BCl3 is between 2:1 and 1:2, and where the flow ratio of BCl3 to Cl2 is between 2:1 and 20:1. A plasma is generated from the etchant gas to selectively etch the high dielectric constant layer.

Claims

AMENDED CLAIMS
[received by the International Bureau on 31 August 2005 (31.08.2005); original claim 14 amended]
forming a patterned mask over the poly-silicon layer; etching a feature into the poly-silicon layer through the patterned mask; etching the high dielectric constant layer to expose the substrate not under the patterned mask, comprising the steps of; providing an etchant gas, wherein trie etchant gas comprises BCtø, an inert diluent, and Cl2. wherein the flow ratio of the inert diluent to BCI3 is between 2:1 and 1:2, and wherein the flow ratio of BC13 to O2 is between 2:1 and 20:1; and generating a plasma fϊαm the etchant gas to selectively etch the high dielectric constant layer; and performing an ion implantation into the exposed substrate.
12. The method, as recited in claim 11, further comprising maintaining the wafer temperature below 150° C during the etching. 13. The method- as recited in any of claims 11 to 12, further comprising providing a DC bias with an absolute value of less than 5 volts.
14. The method, as recited in any of claims 1-10, wherein the high dielectric constant layer is formed from at least one of Hf silicate, Hf02, Zr silicate, Zrθ2, I2O3. La303, SrTiOs, SrZτ03- Ti02, and Y2O3 and wherein the selectively etching selectively etches the high dielectric constant layer with respect to the silicon substrate with a selectivity greater than 4:1.
PCT/US2005/001073 2004-01-14 2005-01-12 Selective etch of films with high dielectric constant WO2005071722A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/758,637 US20050153563A1 (en) 2004-01-14 2004-01-14 Selective etch of films with high dielectric constant
US10/758,637 2004-01-14

Publications (2)

Publication Number Publication Date
WO2005071722A1 WO2005071722A1 (en) 2005-08-04
WO2005071722B1 true WO2005071722B1 (en) 2005-11-17

Family

ID=34740142

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/001073 WO2005071722A1 (en) 2004-01-14 2005-01-12 Selective etch of films with high dielectric constant

Country Status (3)

Country Link
US (1) US20050153563A1 (en)
TW (1) TW200527537A (en)
WO (1) WO2005071722A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7780862B2 (en) * 2006-03-21 2010-08-24 Applied Materials, Inc. Device and method for etching flash memory gate stacks comprising high-k dielectric
US8722547B2 (en) * 2006-04-20 2014-05-13 Applied Materials, Inc. Etching high K dielectrics with high selectivity to oxide containing layers at elevated temperatures with BC13 based etch chemistries
CN102315115A (en) * 2010-06-30 2012-01-11 中国科学院微电子研究所 Dry-process etching method for HfSiAlON high-K dielectric
EP2988322B1 (en) 2014-08-18 2020-06-24 IMEC vzw Method for selective oxide removal

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3398033A (en) * 1965-02-26 1968-08-20 Dow Corning Method of etching silicon carbide
GB1548520A (en) * 1976-08-27 1979-07-18 Tokyo Shibaura Electric Co Method of manufacturing a semiconductor device
JPS6066823A (en) * 1983-09-22 1985-04-17 Semiconductor Energy Lab Co Ltd Etching method of semiconductor
US4865685A (en) * 1987-11-03 1989-09-12 North Carolina State University Dry etching of silicon carbide
US4981551A (en) * 1987-11-03 1991-01-01 North Carolina State University Dry etching of silicon carbide
JPH1065002A (en) * 1996-08-23 1998-03-06 Oki Electric Ind Co Ltd Contact hole forming method
US6090304A (en) * 1997-08-28 2000-07-18 Lam Research Corporation Methods for selective plasma etch
TW383427B (en) * 1998-04-03 2000-03-01 United Microelectronics Corp Method for etching tantalum oxide
US6309927B1 (en) * 1999-03-05 2001-10-30 Advanced Micro Devices, Inc. Method of forming high K tantalum pentoxide Ta2O5 instead of ONO stacked films to increase coupling ratio and improve reliability for flash memory devices
US6436838B1 (en) * 2000-04-21 2002-08-20 Applied Materials, Inc. Method of patterning lead zirconium titanate and barium strontium titanate
US6432779B1 (en) * 2000-05-18 2002-08-13 Motorola, Inc. Selective removal of a metal oxide dielectric
WO2002090615A1 (en) * 2001-05-04 2002-11-14 Lam Research Corporation Duo-step plasma cleaning of chamber residues
US6511872B1 (en) * 2001-07-10 2003-01-28 Agere Systems Inc. Device having a high dielectric constant material and a method of manufacture thereof
US6806095B2 (en) * 2002-03-06 2004-10-19 Padmapani C. Nallan Method of plasma etching of high-K dielectric materials with high selectivity to underlying layers
US6451647B1 (en) * 2002-03-18 2002-09-17 Advanced Micro Devices, Inc. Integrated plasma etch of gate and gate dielectric and low power plasma post gate etch removal of high-K residual
US7357138B2 (en) * 2002-07-18 2008-04-15 Air Products And Chemicals, Inc. Method for etching high dielectric constant materials and for cleaning deposition chambers for high dielectric constant materials
US20040209468A1 (en) * 2003-04-17 2004-10-21 Applied Materials Inc. Method for fabricating a gate structure of a field effect transistor
US7037849B2 (en) * 2003-06-27 2006-05-02 Taiwan Semiconductor Manufacturing Company, Ltd. Process for patterning high-k dielectric material
US20050081781A1 (en) * 2003-10-17 2005-04-21 Taiwan Semiconductor Manufacturing Co. Fully dry, Si recess free process for removing high k dielectric layer

Also Published As

Publication number Publication date
US20050153563A1 (en) 2005-07-14
WO2005071722A1 (en) 2005-08-04
TW200527537A (en) 2005-08-16

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