WO2005041047A3 - Method and apparatus for efficient ordered stores over an interconnection network - Google Patents
Method and apparatus for efficient ordered stores over an interconnection network Download PDFInfo
- Publication number
- WO2005041047A3 WO2005041047A3 PCT/US2004/034147 US2004034147W WO2005041047A3 WO 2005041047 A3 WO2005041047 A3 WO 2005041047A3 US 2004034147 W US2004034147 W US 2004034147W WO 2005041047 A3 WO2005041047 A3 WO 2005041047A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- cache memory
- interconnection network
- level cache
- store requests
- stores over
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0837—Cache consistency protocols with software control, e.g. non-cacheable data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE112004001984T DE112004001984T5 (en) | 2003-10-22 | 2004-10-15 | Method and apparatus for efficiently ordered memory in a connection network |
JP2006536679A JP4658064B2 (en) | 2003-10-22 | 2004-10-15 | Method and apparatus for efficient sequence preservation in interconnected networks |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/691,716 US7338424B2 (en) | 2002-10-25 | 2003-10-22 | Packaging machine |
US10/691,716 | 2003-10-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2005041047A2 WO2005041047A2 (en) | 2005-05-06 |
WO2005041047A3 true WO2005041047A3 (en) | 2005-08-18 |
Family
ID=34521922
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2004/034147 WO2005041047A2 (en) | 2003-10-22 | 2004-10-15 | Method and apparatus for efficient ordered stores over an interconnection network |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP4658064B2 (en) |
KR (1) | KR100841130B1 (en) |
DE (1) | DE112004001984T5 (en) |
WO (1) | WO2005041047A2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8433851B2 (en) * | 2007-08-16 | 2013-04-30 | International Business Machines Corporation | Reducing wiring congestion in a cache subsystem utilizing sectored caches with discontiguous addressing |
US8190820B2 (en) | 2008-06-13 | 2012-05-29 | Intel Corporation | Optimizing concurrent accesses in a directory-based coherency protocol |
JP4703738B2 (en) * | 2009-03-18 | 2011-06-15 | 富士通株式会社 | Storage device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5930822A (en) * | 1996-09-27 | 1999-07-27 | Hewlett-Packard Co. | Method and system for maintaining strong ordering in a coherent memory system |
US20020087815A1 (en) * | 2000-12-30 | 2002-07-04 | Arimilli Ravi Kumar | Microprocessor reservation mechanism for a hashed address system |
US6529999B1 (en) * | 1999-10-27 | 2003-03-04 | Advanced Micro Devices, Inc. | Computer system implementing system and method for ordering write operations and maintaining memory coherency |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05143373A (en) * | 1991-11-18 | 1993-06-11 | Nec Corp | Shared data control system |
US5467473A (en) * | 1993-01-08 | 1995-11-14 | International Business Machines Corporation | Out of order instruction load and store comparison |
JP3505728B2 (en) * | 1993-01-13 | 2004-03-15 | 株式会社日立製作所 | Storage controller |
JPH07114515A (en) * | 1993-10-19 | 1995-05-02 | Hitachi Chem Co Ltd | Decentralized memory computer with network for synchronous communication |
US5893165A (en) * | 1996-07-01 | 1999-04-06 | Sun Microsystems, Inc. | System and method for parallel execution of memory transactions using multiple memory models, including SSO, TSO, PSO and RMO |
-
2004
- 2004-10-15 KR KR1020067007706A patent/KR100841130B1/en not_active IP Right Cessation
- 2004-10-15 JP JP2006536679A patent/JP4658064B2/en not_active Expired - Fee Related
- 2004-10-15 WO PCT/US2004/034147 patent/WO2005041047A2/en active Application Filing
- 2004-10-15 DE DE112004001984T patent/DE112004001984T5/en not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5930822A (en) * | 1996-09-27 | 1999-07-27 | Hewlett-Packard Co. | Method and system for maintaining strong ordering in a coherent memory system |
US6529999B1 (en) * | 1999-10-27 | 2003-03-04 | Advanced Micro Devices, Inc. | Computer system implementing system and method for ordering write operations and maintaining memory coherency |
US20020087815A1 (en) * | 2000-12-30 | 2002-07-04 | Arimilli Ravi Kumar | Microprocessor reservation mechanism for a hashed address system |
Non-Patent Citations (3)
Title |
---|
GHARACHORLOO K ET AL: "Memory consistency and event ordering in scalable shared-memory multiprocessors", PROCEEDINGS OF THE ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE. SEATTLE, MAY 28 - 31, 1990, LOS ALAMITOS, IEEE COMP. SOC. PRESS, US, vol. SYMP. 17, 28 May 1990 (1990-05-28), pages 15 - 26, XP010019261, ISBN: 0-8186-2047-1 * |
H. CHEONG AND A. VEIDENBAUM: "A Version Control Approach to Cache Coherence", PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON SUPERCOMPUTING 89, June 1989 (1989-06-01), pages 322 - 330, XP002330253 * |
TARTALJA I ET AL: "A survey of software solutions for maintenance of cache consistency in shared memory multiprocessors", SYSTEM SCIENCES. VOL. II., PROCEEDINGS OF THE TWENTY-EIGHTH HAWAII INTERNATIONAL CONFERENCE ON WAILEA, HI, USA 3-6 JAN. 1995, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, 3 January 1995 (1995-01-03), pages 272 - 282, XP010128193, ISBN: 0-8186-6930-6 * |
Also Published As
Publication number | Publication date |
---|---|
KR20060063994A (en) | 2006-06-12 |
JP2007509439A (en) | 2007-04-12 |
WO2005041047A2 (en) | 2005-05-06 |
JP4658064B2 (en) | 2011-03-23 |
KR100841130B1 (en) | 2008-06-24 |
DE112004001984T5 (en) | 2006-08-17 |
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