WO2005034191A3 - Template layer formation - Google Patents

Template layer formation Download PDF

Info

Publication number
WO2005034191A3
WO2005034191A3 PCT/US2004/030088 US2004030088W WO2005034191A3 WO 2005034191 A3 WO2005034191 A3 WO 2005034191A3 US 2004030088 W US2004030088 W US 2004030088W WO 2005034191 A3 WO2005034191 A3 WO 2005034191A3
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
chlorine
bearing gas
template layer
layer formation
Prior art date
Application number
PCT/US2004/030088
Other languages
French (fr)
Other versions
WO2005034191A2 (en
Inventor
Chun-Li Liu
Mariam G Sadaka
Alexander L Barr
Bich-Yen Nguyen
Voon-Yew Thean
Shawn G Thomas
Ted R White
Qianghua Xie
Original Assignee
Freescale Semiconductor Inc
Chun-Li Liu
Mariam G Sadaka
Alexander L Barr
Bich-Yen Nguyen
Voon-Yew Thean
Shawn G Thomas
Ted R White
Qianghua Xie
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/670,928 external-priority patent/US7029980B2/en
Application filed by Freescale Semiconductor Inc, Chun-Li Liu, Mariam G Sadaka, Alexander L Barr, Bich-Yen Nguyen, Voon-Yew Thean, Shawn G Thomas, Ted R White, Qianghua Xie filed Critical Freescale Semiconductor Inc
Priority to KR1020067005914A priority Critical patent/KR101132603B1/en
Priority to CN200480024106XA priority patent/CN1926660B/en
Priority to JP2006528055A priority patent/JP4690326B2/en
Publication of WO2005034191A2 publication Critical patent/WO2005034191A2/en
Publication of WO2005034191A3 publication Critical patent/WO2005034191A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)

Abstract

A process for forming strained semiconductor layers. The process include flowing a chlorine bearing gas (e.g. hydrogen chloride, chlorine, carbon tetrachloride, and trichloroethane) over the wafer while heating the wafer. In one example, the chorine bearing gas is flowed during a condensation process on a semiconductor layer that is used as a template layer for forming a strain semiconductor layer (e.g. strain silicon). In other examples, the chlorine bearing gas is flowed during a post bake of the wafer after the condensation operation.
PCT/US2004/030088 2003-09-25 2004-09-14 Template layer formation WO2005034191A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020067005914A KR101132603B1 (en) 2003-09-25 2004-09-14 Template layer formation
CN200480024106XA CN1926660B (en) 2003-09-25 2004-09-14 Template layer formation
JP2006528055A JP4690326B2 (en) 2003-09-25 2004-09-14 Template layer structure

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US10/670,928 US7029980B2 (en) 2003-09-25 2003-09-25 Method of manufacturing SOI template layer
US10/670,928 2003-09-25
US10/919,784 2004-08-17
US10/919,784 US7056778B2 (en) 2003-09-25 2004-08-17 Semiconductor layer formation

Publications (2)

Publication Number Publication Date
WO2005034191A2 WO2005034191A2 (en) 2005-04-14
WO2005034191A3 true WO2005034191A3 (en) 2006-03-09

Family

ID=34426368

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/030088 WO2005034191A2 (en) 2003-09-25 2004-09-14 Template layer formation

Country Status (2)

Country Link
KR (1) KR101132603B1 (en)
WO (1) WO2005034191A2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6259138B1 (en) * 1998-12-18 2001-07-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having multilayered gate electrode and impurity regions overlapping therewith
US6465316B2 (en) * 1999-07-19 2002-10-15 Mitsubishi Denki Kabushiki Kaisha SOI substrate and semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4827324B2 (en) * 2000-06-12 2011-11-30 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP3647777B2 (en) * 2001-07-06 2005-05-18 株式会社東芝 Method of manufacturing field effect transistor and integrated circuit element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6259138B1 (en) * 1998-12-18 2001-07-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having multilayered gate electrode and impurity regions overlapping therewith
US6465316B2 (en) * 1999-07-19 2002-10-15 Mitsubishi Denki Kabushiki Kaisha SOI substrate and semiconductor device

Also Published As

Publication number Publication date
KR101132603B1 (en) 2012-04-06
KR20060090814A (en) 2006-08-16
WO2005034191A2 (en) 2005-04-14

Similar Documents

Publication Publication Date Title
TW200513791A (en) Template layer formation
JP2007507109A5 (en)
TW533489B (en) Semiconductor device and production method thereof
WO2004070776A3 (en) Methods for transferring supercritical fluids in microelectronic and other industrial processes
TW200509251A (en) Semiconductor device and method for manufacturing the same
WO2004105084A3 (en) Method of room temperature covalent bonding
TW344858B (en) Highly integrated and reliable DRAM and its manufacture
TW200503054A (en) Substrate processing method and substrate processing apparatus
WO2003044851A3 (en) Method and apparatus for utilizing integrated metrology data as feed-forward data
WO2005074449A3 (en) Structure comprising amorphous carbon film and method of forming thereof
TW200712757A (en) Method for plasma etching a chromium layer through a carbon hardmask suitable for photomask fabrication
ATE414993T1 (en) ULTRAVIOLET DETECTION SENSOR AND METHOD FOR PRODUCING SAME
WO2005043603A3 (en) Integrated ashing and implant annealing method
EP0984483A3 (en) Semiconductor substrate and method for producing the same
TW200746456A (en) Nitride-based semiconductor device and production method thereof
EP0814500A3 (en) Method for etching polycide structures
WO2004042802A3 (en) A method of rapidly thermally annealing multilayer wafers with an edge
WO2008076092A3 (en) Semiconductor device and method for forming the same
TW344863B (en) Method for etching metal silicide with high selectivity to polysilicon
WO2003030238A1 (en) Processing method
TW200707550A (en) Film formation method and apparatus for semiconductor process
JP2012004273A5 (en)
TW200516700A (en) Metho for forming intermetal dielectric
TW200504937A (en) Method for fabricating semiconductor device and semiconductor substrate
WO2005034191A3 (en) Template layer formation

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200480024106.X

Country of ref document: CN

AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2006528055

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 1020067005914

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 1020067005914

Country of ref document: KR

122 Ep: pct application non-entry in european phase