WO2005027390A2

WO2005027390A2 - Strictly nonblocking multicast multi-split linear-time multi-stage networks

Info

Publication number: WO2005027390A2
Application number: PCT/US2004/029027
Authority: WO
Inventors: Venkat Konda
Original assignee: Teak Technologies, Inc.
Priority date: 2003-09-06
Filing date: 2004-09-05
Publication date: 2005-03-24
Also published as: EP1665821A2; JP2007504772A; CA2537975A1; IL174113A0; EP1665821A4; WO2005027390A3

Abstract

A three-stage network is operated in strictly nonblocking manner in accordance with the invention includes an input stage having r1 switches and n1 inlet links for each of r1 switches, an output stage having r2 switches and n2 outlet links for each of r2 switches. The network also has a middle stage of m switches, and each middle switch has at least one link connected to each input switch for a total of at least r1 first internal links and at least one link connected to each output switch for a total of at least r2 second internal links, if m ≥ s * MIN(n1, n2) where s = 2 when r2 = [9,11], s = 3 when r2 = [25,48], s = 4 when r2 = [49,99], s = 5 when r2 =[1 00,154], s = 6 when r2 =[155,224], and s = 7 when r2 = [225,278]. In one embodiment, each multicast connection is set up through such a three-stage network by use of at most s middle stage switches. When the number of input stage r1 switches is equal to the number of output stage r2 switches, and r1 = r2 = r, and also when the number of inlet links in each input switch n1 is equal to the number of outlet links in each output switch n2, and n1 = n2 = n, a three-stage network is operated in strictly nonblocking manner in accordance with the invention if m ≥ s * n where s = 2 when r = [9,11]; s = 3 when r = [25,48]; s = 4 when r = [49,99]; s = 5 when r = [100,154]; s = 6 when r = [155,224]; and s = 7 when r = [225,278]. In one embodiment, each multicast connection is set up through such a three-stage network by use of at most s middle stage switches.

Description

STRICTLY NONBLOCKING MULTICAST MULTI-SPLIT

LINEAR-TIME MULTI-STAGE NETWORKS

Venkat Konda

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to and claims priority of U.S. Provisional Patent Application Serial No. 60/500,789, filed on 6, September 2003. This application is PCT Application to and incorporates by reference in its entirety the related U.S. Patent Application Docket No. V-0004 entitled "STRICTLY NON-BLOCKING MULTICAST MULTI-SPLIT LINEAR-TIME MULTI-STAGE NETWORKS" by Venkat Konda assigned to the same assignee as the current application, and filed concurrently.

This application is related to and incorporates by reference in its entirety the related U.S. Patent Application Serial No. 09/967,815, filed on 27, September 2001 and its Continuation In Part PCT Application Serial No. PCT/US 03/27971 filed 6, September 2003. This application is related to and incorporates by reference in its entirety the related U.S. Patent Application Serial No. 09/967,106, filed on 27, September 2001 and its Continuation In Part PCT Application Serial No. PCT/US 03/27972, filed 6, September 2003.

This application is related to and incorporates by reference in its entirety the related U.S. Provisional Patent Application Serial No. 60/500,790, filed 6, September 2003 and its U.S. Patent Application Docket No. V-0003 as well as its PCT Application Docket No. S-0003 filed concurrently.

BACKGROUND OF INVENTION

As is well known in the art, a Clos switching network is a network of switches configured as a multi-stage network so that fewer switching points are necessary to implement connections between its inlet links (also called "inputs") and outlet links (also called "outputs") than would be required by a single stage (e.g. crossbar) switch naving the same number of inputs and outputs. Clos networks are very popularly used in digital crossconnects, optical crossconnects, switch fabrics and parallel computer systems. However Clos networks may block some of the connection requests.

There are generally three types of nonblocking networks: strictly nonblocking; wide sense nonblocking; and rearrangeably nonblocking (See V.E. Benes, "Mathematical Theory of Connecting Networks and Telephone Traffic" Academic Press, 1965 that is incorporated by reference, as background). In a rearrangeably nonblocking network, a connection path is guaranteed as a result of the network's ability to rearrange prior connections as new incoming calls are received. In strictly nonblocking network, for any connection request from an inlet link to some set of outlet links, it is always possible to provide a connection path through the network to satisfy the request without disturbing other existing connections, and if more than one such path is available, any path can be selected without being concerned about realization of future potential connection requests. In wide-sense nonblocking networks, it is also always possible to provide a connection path through the network to satisfy the request without disturbing other existing connections, but. in this case the path used to satisfy the connection request must be carefully selected so as to maintain the nonblocking connecting capability for future potential connection requests.

U.S. Patent 5,451,936 entitled "Non-blocking Broadcast Network" granted to Yang et al. is incorporated by reference herein as background of the invention. This patent describes a number of well known nonblocking multi-stage switching network designs in the background section at column 1, line 22 to column 3, 59.

An article by Y. Yang, and G.M., Masson entitled, "Non-blocking Broadcast Switching Networks" IEEE Transactions on Computers, Vol. 40, No. 9, September 1991 that is incorporated by reference as background indicates that if the number of switches in the middle stage, m, of a three-stage network satisfies the relation m ≥ min((« - 1)(J + r^ilx )) where 1 < x ≤ min(« - 1, r) , the resulting network is nonblocking for multicast assignments. In the relation, r is the number of switches in the input stage, and n is the number of inlet links in each input switch. Kim and Du (See D.S. Kim, and D. Du, "Performance of Split Routing Algorithm for three-stage multicast networks", IEEE/ACM Transactions on Networking, Vol. 8, No. 4, August 2000 incorporated herein by reference) studied the blocking probability for multicast connections for different scheduling algorithms.

SUMMARY OF INVENTION

A three-stage network is operated in strictly nonblocking manner in accordance with the invention includes an input stage having switches and «, inlet links for each of r, switches, an output stage having r₂ switches and n₂ outlet links for each of r₂ switches.

The network also has a middle stage of m switches, and each middle switch has at least one link connected to each input switch for a total of at least r_x first internal links and at least one link connected to each output switch for a total of at least r₂ second internal links, if m ≥ s * MIN(n ,n₂ ) where 5 = 2 when r₂ = [9,11], 5 = 3 when r₂ = [25,48], 5 = 4 when r₂ = [49,99], 5 = 5 when r₂ = [100,154], 5 = 6 when r₂ = [l 55,224], and s = 7 when r₂ = [225,278].

In one embodiment, each multicast connection is set up through such a three-stage network by use of at most s middle stage switches. When the number of input stage r, switches is equal to the number of output stage r₂ switches, and = r₂ = r , and also when the number of inlet links in each input switch «, is equal to the number of outlet links in each output switch n₂ , and n_x = n₂ = n , a three-stage network is operated in strictly nonblocking manner in accordance with the invention if m > s * n when 5 = 2 when r = [9,l l], 5 = 3 when r = [25,48], 5 = 4 when r = [49,99], 5 = 5 when r = [l00,154], 5 = 6 when r = [l 55,224], and 5 = 7 when r = [225,278]. In one embodiment, each multicast connection is set up through such a three-stage network by use of at most s middle stage switches.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A is a diagram of an exemplary three-stage symmetrical network with exemplary multicast connections in accordance with the invention; FIG. IB is high-level flowchart of a scheduling method according to the invention, used to set up the multicast connections in the network 100 of FIG. 1A; and FIG. IC is a diagram of a graph illustrating different section of ranges of fan-out of a multicast connection where it is fan- out-split differently according to the invention.

FIG. 2A is a diagram of a general symmetrical three-stage strictly nonblocking network with n inlet links in each of r input stage switches and s * n middle stage switches {Where 5 = 2 when r = [9,11]; 5 = 3 when r = [25,48]; 5 = 4 when r = [49,99]; 5 = 5 when r = [l 00,154 j; 5 = 6 when r = [l 55,224], and 5 = 7 when r = [225,278]} that are used with the method of FIG. IB in one embodiment; and FIG. 2B is a diagram of a general non-symmetrical three-stage strictly nonblocking network with H_j inlet links in each of r input stage switches, n₂ outlet links in each of r₂ output stage switches, and 5 * «„ middle stage switches {Where 5 = 2 when r₂ = [9,1 lj; 5 = 3 when r₂ = [25,48];5 = 4 when r₂ = [49,99];5 = 5 when r₂ = [100,154]; 5 = 6 when r₂ = [155,224], and 5 = 7 when r₂ = [225,278]} that are used with the method of FIG. IB in one embodiment.

FIG. 3 A shows the network of FIG. 1A after a new connection is set up by selecting two middle switches in the network, using the method of FIG. IB in one implementation.

FIG. 4A is intermediate level flowchart of one implementation of the act 142 of FIG. IB; FIG. 4B implements, in one embodiment, the data structures used to store and retrieve data from memory of a controller that implements the method of FIG. 4A. FIG. 5 A is a diagram of an exemplary three-stage network where the middle stage switches are each three-stage networks; FIG. 5B is high-level flowchart, in one embodiment, of a recursively scheduling method in a recursively large multi-stage network such as the network in FIG. 5A.

FIG. 6A is a diagram of an exemplary P^"(6,3,4) three-stage network, with m = s*n middle stage switches, where 5 = 2 , implemented in space-space-space configuration, with certain existing multicast connections setup using the method 140 of FIG. IB; FIG. 6B is the first time step of the TST implementation of the network in FIG. 6A; FIG. 6C is the second time step of the TST implementation of the network in FIG. 6A; and FIG. 6D is the third time step of the TST implementation of the network in FIG. 6A

DETAILED DESCRIPTION OF THE INVENTION

The present invention is concerned with the design and operation of multi-stage switching networks for broadcast, unicast and multicast connections. When a transmitting device simultaneously sends information to more than one receiving device, the one-to-many connection required between the transmitting device and the receiving devices is called a multicast connection. A set of multicast connections is referred to as a multicast assignment. When a transmitting device sends information to one receiving device, the one-to-one connection required between the transmitting device and the receiving device is called unicast connection. When a transmitting device simultaneously sends information to all the available receiving devices, the one-to-all connection required between the transmitting device and the receiving devices is called a broadcast connection.

In general, a multicast connection is meant to be one-to-many connection, which includes unicast and broadcast connections. A multicast assignment in a switching network is nonblocking if any of the available inlet links can always be connected to any of the available outlet links. In certain multi-stage networks of the type described herein, any connection request of arbitrary fan-out (denoted as /), i.e. from an inlet link to an outlet link or to a set of outlet links of the network, can be satisfied without blocking with never needing to rearrange any of the previous connection requests. Depending on the number of switches in a middle stage of such a network, such connection requests may be satisfied without blocking if necessary by rearranging some of the previous connection requests as described in detail in U.S. Patent Application Serial No. 09/967,815 that is incorporated by reference above. Depending on the number of switches in a middle stage of such a network and a scheduling method of time complexity 0(m²), such connection requests may be satisfied even without rearranging as described in detail in U.S. Patent Application Serial No.09/967,106 that is incorporated by reference above. Depending on the number of switches in a middle stage of such a network and a scheduling method of time complexity θ(m), such connection requests may be satisfied even without rearranging as described in detail in U.S. Patent Application Docket No. V-0003 US that is incorporated by reference above.

Referring to FIG. 1 A, an exemplary symmetrical three-stage Clos network of twenty four switches for satisfying communication requests, such as setting up a telephone call or a data packet connection, between an input stage 110 and output stage 120 via a middle stage 130 is shown where input stage 110 consists of nine, three by six switches IS1-IS9 and output stage 120 consists of nine, six by three switches OS1-OS9, and middle stage 130 consists of six, nine by nine switches MS1-MS6. Such a network can be operated in strictly non-blocking manner, because the number of switches in the middle stage 130 (i.e. six switches) is equal to s* n , where the n is the number of links (i.e. three inlet links) of each of the switches in the input stage 110 and output stage 120, and = 2 in FIG. 1A. The specific method used in implementing the strictly non- blocking connectivity can be any of a number of different methods that will be apparent to a skilled person in view of the disclosure. One such method is described below in reference to FIG. IB.

In one embodiment of this network each of the input switches IS1-IS9 and output switches OS1-OS9 are single-stage switches. When the number of stages of the network is one, the switching network is called single-stage switching network, crossbar switching network or more simply crossbar switch. A (N * M) crossbar switching network with Ν inlet links and M outlet links is composed of NM cross points. As the values of Ν and M get larger, the cost of making such a crossbar switching network becomes prohibitively expensive. In another embodiment of the network in FIG. 1A each of the input switches IS1-IS9 and output switches OS1-OS9 are shared memory switches.

The number of switches of input stage 110 and of output stage 120 can be denoted in general with the variable r for each stage. The number of middle switches is denoted by m . The size of each input switch IS1-IS9 can be denoted in general with the notation n * m and of each output switch OS1-OS9 can be denoted in general with the notation m*n. Likewise, the size of each middle switch MS1-MS6 can be denoted as r*r . A switch as used herein can be either a crossbar switch, or a network of switches each of which in turn may be a crossbar switch or a network of switches. A three-stage network can be represented with the notation V(m,n,r), where n represents the number of inlet links to each input switch (for example the links IL1-IL3 for the input switch ISl) and m represents the number of middle switches MS1-MS6. Although it is not necessary that there be the same number of inlet links IL1-IL27 as there are outlet links OL1-OL27, in a symmetrical network they are the same. Each of the m middle switches MS1-MS6 are connected to each of the r input switches through r links (hereinafter "first internal" links, for example the links FL1-FL9 connected to the middle switch MSI from each of the input switch IS1-IS9), and connected to each of the output switches through r second internal links (hereinafter "second internal" links, for example the links SL1-SL9 connected from the middle switch MSI to each of the output switch OS1-OS9).

Each of the first internal links FL1-FL54 and second internal links SL1-SL54 are either available for use by a new connection or not available if currently used by an existing connection. The input switches IS1-IS9 are also referred to as the network input ports. The input stage 110 is often referred to as the first stage. The output switches OS1-OS9 are also referred to as the network output ports. The output stage 120 is often referred to as the last stage. In a three-stage network, the second stage 130 is referred to as the middle stage. The middle stage switches MS1-MS6 are referred to as middle switches or middle ports.

In one embodiment, the network also includes a controller coupled with each of the input stage 110, output stage 120 and middle stage 130 to form connections between an inlet link IL1-IL27 and an arbitrary number of outlet links OL1-OL27. In this embodiment the controller maintains in memory a list of available destinations for the connection through a middle switch (e.g. MSI in FIG 1 A). In a similar manner a set ol n lists are maintained in an embodiment of the controller that uses a fan-out of n.

A multicast connection may be set up to all its designated destinations through one or more middle switches. When the multicast connection is routed through more than one middle switch it is called the multicast connection is fan-out-split to set up the connection.

FIG. IB shows a high-level flowchart of a scheduling method 140, in one embodiment executed by the controller of FIG. 1A. According to this embodiment, a multicast connection request is received in act 141. Then in act 142, the connection request is fan-out-split if the fan-out of the connection is > s and < p, (For the network γ

1 0 of FIG. 1 A, p = - , the determination of the value of p for a V(m,n,r) network is 5 discussed later) according to the current invention. Finally the request is set up in act 143 by fanning out into only one switch in middle stage 130 from its input switch if it is not fan-out-split. Otherwise the connection request is set up through at most s middle switches by fanning out at most s times in the input switch, i.e., at most one middle switch for each fan-out-split connection.

In the example illustrated in FIG. 1A, different fan-out in the input switch is used to satisfy each multicast connection request based on the fan-out of the request. The specific middle switch that is chosen when selecting the fan-out is irrelevant to the method of FIG. IB so long as the required number of middle switch is selected to ensure that the connection request is satisfied, i.e. the destination switches identified by the connection request can be reached from the middle switches that is part of the selected fan-out. In essence, limiting the fan-out from input switch to at most s middle switches permits the network 100 to be operated in strictly nonblocking manner in accordance with the invention.

After act 143, the control is returned to act 141 so that acts 141, 142 and 143 are executed in a loop for each multicast connection request. According to one embodiment as shown further below it is not necessary to have more than 2 * n middle stage switches in network 100 of the FIG. 1A, where the number of inlet links IL1-IL3 equals the number of outlet links OL1-OL3, both represented by the variable n and where the number of switches IS1-IS9 in the input stage 110 equals the number of switches OS1- OS9 in the output stage 120, both represented by the variable r for the network to be a strictly nonblocking symmetrical switching network, when the scheduling method of FIG. IB is used.

The connection request of the type described above in reference to method 140 of FIG. IB can be unicast connection request, a multicast connection request or a broadcast connection request, depending on the example. In all the three cases of connection requests, a fan-out of not more than in the input switch is used. Moreover, although in the above-described embodiment a limit of s has been placed on the fan-out into the middle stage switches, the limit can be greater depending on the number of middle stage switches in a network, as discussed below in reference to FIG. 2A (while maintaining the strictly nonblocking nature of operation of the network). Moreover, in method 140 described above in reference to FIG. IB any arbitrary fan-out may be used between each middle stage switch and the output stage switches, and also any arbitrary fan-out may be used within each output stage switch, to satisfy the connection request. Moreover, although method 140 of FIG. IB has been illustrated with examples in a twenty-four switch network 100 of FIG. 1A, the method 140 can be used with any general network, of the type illustrated in FIG. 2A and FIG.2B.

Network of FIG. 1 A is an example of general symmetrical three-stage network shown in FIG. 2A. The general symmetrical three-stage network can be operated in strictly nonblocking manner if m ≥ s * n where

5 = 2 when r = [9,ll], 5 = 3 when r = [25,48], 5 = 4 when r = [49,99], 5 = 5 when r = [l00,154], 5 = 6 when r = [l 55,224], and 5 = 7 when r = [225,278], wherein network FIG. 2A has n inlet links for each of r input switches ISl-lSr (lor example the links ILI i-ILln to the input switch ISl) and n outlet links for each of r output switches OSl-OSr (for example OL11-OLln to the output switch OS1). Each of the m switches MSI -MSm are connected to each of the input switches through r first internal links (for example the links FL11-FLrl connected to the middle switch MSI from each of the input switch ISl-ISr), and connected to each of the output switches through r second internal links (for example the links SL11-SLrl connected from the middle switch MSI to each of the output switch OSl-OSr). In such a general symmetrical network no more than s * n middle stage switches {where 5 = 2 when r = [9,11]; 5 = 3 when r = [25,48]; 5 = 4 when r = [49,99]; 5 = 5 when r = [100,154]; s ^ 6 when r = [l 55,224], and 5 = 7 when r = [225,278]} MS1-MS( 5 * n ) are necessary for the network to be operable in strictly nonblocking manner, when using a scheduling method of the type illustrated in FIG. IB. Although FIG. 2A shows an equal number of first internal links and second internal links, as is the case for a symmetrical three-stage network, the present invention, however, applies even to non-symmetrical networks of the type illustrated in FIG 2B (described next).

In general, an (N, *N₂) asymmetric network of three stages can be operated in strictly nonblocking manner if m ≥ s * MIN(n_x , n ) where 5 = 2 when r₂ = [9,l l], 5 = 3 when r₂ = [25,48], 5 = 4 when r₂ = [49,99], 5 = 5 when r₂ = [l00,154], 5 = 6 when r₂ = [155,224], and 5 = 7 when r₂ = [225,278], wherein network (FIG. 2B) has r, («, * m) switches ISl-ISri in the first stage, m

(rι * r₂ ) switches MS 1 -MSm in the middle stage, and r₂ (m *n₂) switches OS 1 -OSr₂ in the last stage where N, = «, * r_x is the total number of inlet links and N₂ = n₂ * r₂ is the total number of outlet links of the network. Each of the m switches MS1-

MS( 5 * MIN(n ,n₂)) are connected to each of the input switches through r, first internal links (for example the links FLl l-FLf_! 1 connected to the middle switch MSI from each of the input switch ISl-ISr , and connected to each of the output switches through r₂ second internal links (for example the links SL1 l-SLr₂l connected from the middle switch MSI to each of the output switch OSl-OSr₂). Such a multi-stage switching network is denoted as a V(m, n_x,r_x,n₂,r₂) network. For the special symmetrical case where «, = «₂ = n and r, = r₂ = r , the three-stage network is denoted as a V(m,n,r) network. In general, the set of inlet links is denoted as {l,2,...,r_In₁}and the set of output switches are denoted as O = {l,2,...,r₂}. In an asymmetrical three-stage network, as shown in FIG. 2B with n, inlet links for each of r, input switches, n₂ outlet links for each of r₂ output switches, no more than m ≥ s*MIN(n_l,n₂) where

5 = 2 when r₂ = [9,l l], 5 = 3 when r₂ = [25,48], 5 = 4 when r₂ = [49,99], 5 = 5 when r₂ = [100,154], 5 = 6 when r₂ = [l 55,224], and 5 = 7 when r₂ = [225,278]. middle stage switches are necessary for the network to be strictly nonblocking, again when using the scheduling method of FIG. IB. The network has all connections set up such that each connection passes through at most s middle switches to be connected to all destination outlet links.

In one embodiment every switch in the multi-stage networks discussed herein has multicast capability. In a V(m,n_x,r_x,n₂,r₂) network, if a network inlet link is to be connected to more than one outlet link on the same output switch, then it is only necessary for the corresponding input switch to have one path to that output switch. This follows because that path can be multicast within the output switch to as many outlet links as necessary. Multicast assignments can therefore be described in terms of connections between input switches and output switches. An existing connection or a new connection from an input switch to r' output switches is said to have fan-out r' . If all multicast assignments of a first type, wherein any inlet link of an input switch is to be connected in an output switch to at most one outlet link are realizable, then multicast assignments of a second type, wherein any inlet link of each input switch is to be connected to more than one outlet link in the same output switch, can also be realized. For this reason, the following discussion is limited to general multicast connections of the first type (with fan-out r' , 1 < r'≤ r₂ ) although the same discussion is applicable to the second type.

To characterize a multicast assignment, for each inlet link / e {l,2,...,r_]n, }, let /, = O, where O c {l,2,...,r₂}, denote the subset of output switches to which inlet link i is to be connected in the multicast assignment. For example, the network of Fig. 1 A shows an exemplary three-stage network, namely (6,3,9) , with the multicast assignment shown in Table 1. This network has a total of twenty-seven inlet links and twenty-seven outlet links. The multicast assignment in Table 1 shows six multicast connections. Each of the six connections has different fan-out. For example, the connection request Ij has the destinations as the output switches OSl, OS2, S3, OS4, and OS5 (referred to as 1, 2, 3, 4, 5 in Table 1). Request l_\ only shows the output switches and does not show which outlet links are the destinations. However it can be observed that none of the output switches is used more than three times in the multicast assignment of Table 1. for example, output switch 1 is used in requests Ii, I₂, Lj, so that all three outlet links of output switch 1 are in use, and a specific identification of each outlet link is irrelevant.

In FIG. 1A, it should be noted that the connection /, fans out in the first stage 9 switch ISl into the middle stage switch MSI since the fan-out of the connection is 5 > — ; 1_* and fans out in middle switch MSI into output switches OSl, OS2, OS3, OS4, and OS5.

The connection /, also fans out in the last stage switches OSl, OS2, OS3, OS4, and OS5 into one of the outlet link of the three outlet links in each of the output switches. The connection I₂ fans out twice in the input switch ISl into middle switches MS2 and MS5 9 since the fan-out of the connection is 4 > 2 and 4 < — ; and fans out in the middle stage 2 switches MS2 and MS5 into the last stage switch {OS4, OS5} and {OS6, OSl} respectively. The connection I₂ fans out once in the output switches OS4, OS5, OS6, and OSl into one of the outlet links in each of the output switches. The connection I₃ fans out twice in the input switch ISl into middle switches MS3 and MS4 since the fan-out of 9 the connection is 3 > 2 and 3 < — ; and fans out in the middle stage switches MS3 and 2

MS4 into the last stage switch {OS7, OS8} and {OS9} respectively. The connection I₃ fans out once in the output switches OS7, OS8, and OS9 into one of the outlet links in each of the output switches.

In FIG.1A, the connection 7₄ fans out once in the input switch IS2 into middle 9 switch MS4 since the fan-out of the connection is 6 > — ; and fans out in the middle stage 2 switch MS4 into the last stage switch OSl, OS2, OS3, OS4, OS7, and OS8 respectively. The connection 7₄ fans out once in the output switches OSl, OS2, OS3, OS4, OS7, and OS8 into one of the outlet links in each of the output switches. The connection I₅ fans out once in the input switch IS2 into middle switch MS5 since the fan-out of the 9 connection is 5 > — ; and fans out in the middle stage switch MS5 into the last stage

switch OS2, OS5, OS7, OS8, and OS9 respectively. The connection I₅ fans out once in the output switches OS2, OS5, OS7, OS8, and OS9 into one of the outlet links in each ot the output switches. The connection I_η fans out once in the input switch IS3 into middle switch MSI since it is unicast connection; and fans out in the middle stage switch MSI into the last stage switch OS6. The connection I₇ fans out once in the output switch OS6 into one of the outlet links in each of the output switches. In accordance with the invention, each connection can fan out in the first stage switch into s middle stage switches, and in the middle switches and last stage switches it can fan out any arbitrary number of times as required by the connection request.

Two multicast connection requests / = 0, and I = 0 for ≠ j are said to be compatible if and only if O, (1 O = φ . It means when the requests 7, and l_} are compatible, and if the inlet links and j do not belong to the same input switch, they can be set up through the same middle switch.

FIG. 3B shows the state of the (6,3,9) network of FIG. 1A after the connection request I₆ = {3,6,9} is set up. Method 140 of FIG. IB next sets up a connection I₆ from input switch IS2 to output switches OS3, OS6 and OS9 as follows. In act 142 the scheduling method of FIG. IB finds that, since the fan-out of the connection request I₆ is

3, it is fan-out-split arbitrarily into two fan-out-split connections, the first with destinations switches as OS3 and OS6, and the second with destination switch as OS9. Then the control transfers to act 143, where each of these two fan-out-split connections is independently set up. As shown in FIG.3A the connection I₆ is fanned out in the input switch IS2 twice to middle switches MS6 and MSI. In the middle switch MS6 it is fanned out twice into the output switches OS3 and OS6 and in the middle switch MSI it is fanned out once into the output switch OS9. In the output switches OS3, OS6 and OS9, the connection I₆ is fanned out into the destined outlet link.

FIG. 4A is an intermediate-level flowchart of one variant of act 140 of FIG. IB. Act 142 of FIG. IB fan-out-splits the connection arbitrarily s times, if the fan-out of the connection is > s and < p . Act 143 of FIG. IB is implemented in one embodiment by acts 143A-143E as illustrated in FIG. 4A. Act 143A checks if a middle switch has an available link to the input switch, and also has available links to all the required destination switches. In act 143B, the method of FIG. 4A checks if all middle switches has been checked in 143A. As illustrated in FIG. 4B, act 143B is reached when the decision in act 143A is "no". If act 143B results in "no", the control goes to act 143C where the next middle switch is selected and the control transfers to act 143 A. But act 143B never results in "yes" which means the method of FIG. 4A always finds one middle switch to set up the connection. When act 143 A results in "yes" the connection is set up or the fan-out-split connection is set up. Then control transfers to act 143E, where it is checked if all the fan-out-split connections are set up. If act 143E results in "no", the control transfers to act 143 A to set up the next fan-out-split connection. If act 143E results in "yes", i.e., all the fan-out-split connections are set up, the control transfers to act 141.

In a three-stage network of FIG. 2B with «, inlet links for each of r, input switches, n₂ outlet links for each of r output switches, no more than m ≥ s * MIN(n_x , n₂ ) where

5 = 2 when r₂ = [9,l l], 5 = 3 when r₂ = [25,48], 5 = 4 when r, = [49,99], 5 = 5 when r₂ = [100,154], s = 6 when r₂ = [l 55,224], and 5 = 7 when r₂ = [225,278], middle stage switches are necessary for the network to be strictly nonblocking and hence also for the method of FIG. 4A to always find one middle switch to set up the connection.

And the following method illustrates the psuedo code for one implementation of the scheduling method of FIG. 4A to always set up a new multicast connection request through the network of FIG. 2B, when there are as many middle switches in the network as discussed in the invention. Pseudo code of the scheduling method: Step 1 : c = current connection request; L = Set of all destination switches of c;

Step 2: f = Number of destination switches of c;

Step 3 : if ((f > s) and (f < p)) {

Step 4: for i = 1 to s do {

Step 5: 0[i = Set of any unmarked destination switches of c;

Step 6: Mark the used destination switches of c; Step 7: } else 0[\] = L ;

Step 8: forj = 1 to s do { Step 9: if 0[j] ≠ NULL ) { Step 10 for i = mid_switch_l to mid_switch_m do { Step 11 if (c has no available link to i) continue;

Step 12 A_t = Set of all destination switches having available links from i ;

Step 13 if(C[y] c 4 ) { Set up fan-out-split connection j of connection c through i for all the destination switches in Set 0J] ; Mark all the used links to and from i as unavailable; }

Step 14: return ("SUCCESS");

Step 1 above labels the current connection request as "c" and also labels the set of the destination switches of c as "L". Step 2 assigns the fan-out of "c" to f. Step 3 checks if fan-out-splitting of "c" is required; i.e., if (f > s) and (f < p) then "c" is fan-out-split. (The determination of the values of s and p, which is discussed next, is fed in as input constants to the method). Step 4 starts a loop to create s number of fan-out-split connections of "c". Step 5 arbitrarily assigns destination switches of "c" to each

constituent fan-out-split connections into 0[i] for i = 1 to s. Step 6 marks the already assigned destination switches so that they are not assigned to another fan-out-split connection. When the fan-out-split is not performed for a connection, 0[1] is set to all the destination switches of "c". Step 8 starts a loop to set up each connection or fan-out-split connections of the connection. Step 9 checks if the corresponding set 0[i] is not NULL then Step 10 starts a loop and steps through all the middle switches.

If the input switch of c has no available link to the middle switch i, Step 11 continues so that next middle switch is selected as i. Step 12 determines the set of destination switches of fan-out-split connection j having available links from middle switch i. In Step 13 if middle switch i has available links to all the destination switches of fan-out-split connection j, connection j is set up through middle switch i. And all the used links of middle switch i to output switches are marked as unavailable for future requests. These steps are repeated for all the middle switches. One middle switch can always be found for each fan-out-split connection j to be set up, according to the current invention. So Step 14 always returns the control with "SUCCESS". It is easy to observe that the number of steps performed by the scheduling method is proportional to s x m , where m is the number of middle switches in the network. Since is a constant, the scheduling method is of time complexity θ(m).

FIG. 4B illustrates, in one embodiment, the data structures used to store and retrieve data from memory of a controller that implements the method of FIG. 4A. In this embodiment, a fan-out of one or more in the input switch of each connection is implemented by use of two data structures (such as arrays or linked lists) to indicate the destinations that can be reached from one middle switch. Each connection request 510, when it is not fan-out-split, is specified by an array 520 of destination switch identifiers (and also an inlet link of an input switch identifier). When connection request 510 is fan- out-split, s number of arrays 525 represent with one array denoting the destination switches for each fan-out-split connection. Another array 530 of middle switches contains m elements one each for all the middle switches of the network. Each element of array 530 has a pointer to one of m arrays, 540-1 to 540-m, containing bits that indicate availability status (hereinafter availability status bit) for each output switch OSl-OSr as shown in FIG. 4B. If second internal link to an output switch is available from a middle switch, the corresponding bit in the availability status array is set to 'A' (to denote available, i.e. unused link) as shown in FIG.4B. Otherwise the corresponding bit is set to 'U' (to denote unavailable, i.e. used link).

For each connection 510, depending on if it is fan-out-split or not, each middle switch MSi is checked to see if the destinations of each fan-out-split connection of the connection 510 are reachable from MSi. Specifically this condition is checked by using the availability status arrays 540-i of middle switch MSi, to determine the available destinations of the fan-out-split connection from MSi. In one implementation, each destination is checked if it is available from the middle switch MSi, and if the middle switch MSi does not have availability for a particular destination, the middle switch MSi cannot be used to set up the connection. The embodiment of FIG. 4B can be implemented to set up connections in a controller 550 and memory 500 (described above in reference to FIG. 1A, FIG. 2A, and FIG. 2B etc.).

In rearrangeably nonblocking networks, the switch hardware cost is reduced at the expense of increasing the time required to set up connection a connection. The set up time is increased in a rearrangeably nonblocking network because existing connections that are disrupted to implement rearrangement need to be themselves set up, in addition to the new connection. For this reason, it is desirable to minimize or even eliminate the need for rearrangements to existing connections when setting up a new connection. When the need for rearrangement is eliminated, that network is either wide-sense nonblocking or strictly nonblocking, depending on the number of middle switches and the scheduling method. Embodiments of rearrangeably nonblocking networks using 2 * n or more middle switches are described in the related U.S. Patent application Serial No. 09/967,815 that is incorporated by reference above.

In strictly nonblocking multicast networks, for any request to form a multicast connection from an inlet link to some set of outlet links, it is always possible to find a path through the network to satisfy the request without disturbing any existing multicast connections, and if more than one such path is available, any of them can be selected without being concerned about realization of future potential multicast connection requests. In wide-sense nonblocking multicast networks, it is again always possible to provide a connection path through the network to satisfy the request without disturbing other existing multicast connections, but in this case the path used to satisfy the connection request must be selected to maintain nonblocking connecting capability lor future multicast connection requests. In strictly nonblocking networks and in wide-sense nonblocking networks, the switch hardware cost is increased but the time required to set up connections is reduced compared to rearrangeably nonblocking networks. Embodiments of strictly nonblocking networks using 3 * «-l or more middle switches, which use a scheduling method of time complexity Oψt² ), are described in the related U.S. Patent application Serial No. 09/967,106 that is incorporated by reference above. Embodiments of strictly nonblocking networks using

is > 1 and odd, or when

2 ,

CV(«,,»₂)when i ] is > 2 and even, and

or more middle switches, which use a scheduling method of time complexity θ(m), and a multicast connection is set up by fanning out not more than once in the input switch, are described in the related U.S. Patent application, docket No. V-0003 US that is incorporated by reference above.

As discussed above, since in V(m,n_x,r ,n₂,r₂) network, if an inlet link is to be connected to more than one outlet link on the same output switch, then it is only necessary for the corresponding input switch to have one path to that output switch. So the connection will be fanned out to the desired output links within the output stage switches. Hence applicant notes the multicasting problem can be solved in three different approaches:

1) Fan-out only once in the second stage and arbitrary fan-out in the first stage.

2) Fan-out only once in the first stage and arbitrary fan-out in the second stage.

3) Optimal and arbitrary fan-out in both first and second stages.

Masson and Jordan (G.M. Masson and B.W. Jordan, "Generalized Multi-stage Connection Networks", Networks, 2: pp. 191-209, 1972 by John Wiley and Sons, Inc.) presented the rearrangeably nonblocking networks and strictly nonblocking networks by following the approach 1, of fanning-out only once in the second stage and arbitrarily fanning out in the first stage. U.S. Patent application Serial No. 09/967,815 that is incorporated by reference above, and U.S. Patent application Serial No. 09/967,106 that is incorporated by reference above presented the rearrangeably nonblocking networks and strictly nonblocking networks, respectively, by following the approach 3, of anning-out optimally and arbitrarily in both first and second stages. U.S. Patent application, docket No. V-0003 US that is incorporated by reference above presented the strictly nonblocking networks by following the approach 2 of fanning out only once in the first stage and arbitrary fan-out in the second stage.

The foregoing discussion relates to embodiments of strictly nonblocking networks, by combining the techniques of the two approaches 2 and 3. Specifically the current invention presents V(m,n_x,r_x,n₂,r₂) strictly nonblocking networks, hereinafter "multi-split linear-time V(m,n_x,r_x,n₂,r₂) strictly nonblocking networks", by combining the methods of a) Fan-out only once in the first stage and arbitrary fan-out in the second stage, b) Optimal and arbitrary fan-out in both first and second stages. Compared to the strictly nonblocking networks of a), i.e. the networks presented in U.S. Patent application, Docket No. V-0003 US that is incorporated by reference above, the multi-split linear-time V(m, n_x,r_x,n₂,r₂) strictly nonblocking networks employ fewer middle stage switches m , but still use linear-time scheduling method for the strictly nonblocking operation. And compared to the strictly nonblocking networks presented in U.S. Patent application Serial No. 09/967,106 that is incorporated by reference above, the multi-split linear-time V(m, n_x,r_x,n₂,r₂) strictly nonblocking networks employ more number of middle stage switches m but they are faster in scheduling time.

To provide the proof for the current invention, the strictly nonblocking operation of both the symmetric networks V(m,n,r) and the asymmetric networks

V(m,n_x,r_x,n₂,r₂) are considered. U.S. Patent application, docket No. V-0003 US that is incorporated by reference above presented that the minimum number of middle stage switches m required for V(m,n,r) network to be operable in strictly nonblocking manner, for a few exemplary values of r as enumerated in Table 3.

γfl In Table 3 as r increases, — also increases, and the V(m,n,r) network is n operable in strictly nonblocking manner where each multicast connection is fanned out only once in the input switch using the linear scheduling method. Applicant makes a fundamental observation that by arbitrarily splitting the multicast connections in the input switch, when the fan-out of the connection is in a specified range (to be discussed next), the V(m,n,r) network is operable in strictly nonblocking manner for a smaller m than as shown in Table 3. Applicant emphasizes that arbitrary splitting of multicast connections in input switch provides the opportunity to schedule each of the constituent fan-out-spilt connections independent of other and hence scheduling method is linear in time complexity.

Referring to FIG. IC, it shows the maximum number of middle switches needed for V(m, n ,r_x,n₂,r₂) network to be operable in strictly nonblocking manner when a multicast connection is fanned out only once in the input switch, as presented in U.S. Patent application, Docket No. V-0003 that is incorporated by reference above, requires a maximum of

LVrTJ* MIN(n_x,n₂) when

is > 1 and odd, or when L 'TJ" 2 _>

is > 2 and even, and n + n₂ - 1 when L-_\T- J⁼ 1 >

middle switches (m - x in FIG. IC). The current invention presents methods to reduce the number of middle switches by fan-out-splitting the_, connections only for a range of fan-outs of a multicast connection as shown in FIG. IC; The number of middle switches is chosen as sx n for a certain values of s and p , the calculation of which is discussed next, so that the following general steps are performed:

1) When/ < 5 : The multicast connection is fanned out through only one middle switch. 2) When f > s and / < p : The multicast connection is arbitrarily fan-out-split times so that each fan-out-split connection will have a fan-out of either — or / and the connection is fanned out through not more than 5 middle switches 5 _ 3) W enf ≥ p : The multicast connection is fanned out through only one middle switch.

The value of s is derived from the following two conditions: 1) 5 < Jϊζj ^and P is chosen as the biggest integer and p such

2) p is further adjusted to be larger than the value computed condition 1, such that

(where b = and the condition 2 should be satisfied for all odd integers

^≤LV^J ⁾ p - \ p -\ p -\ a. b x ≤ sx r^~_ when is odd; and p-\ p- \ p-\ b. b x + 1 + 1 ≤ s x when is even.

These conditions are applied to V(m,n_x,r_x,n₂,r₂) networks to derive s for different values of r₂ and the proof is as follows:

Applicant provides the proof that this network is operable in strictly nonblocking manner when m ≥ 2x MLN(n_x ,n₂) :

1) When the fan-out of multicast connection is / > s and

/ > 2 and / < 5 ), the connection is arbitrarily fan-out-split twice, and is fanned out twice in the input switch, and

2)

is / < 2 or / > 5 ), it is fanned out only once in the input switch. Since each multicast connection is fanned out at most twice, m ≥ lx MIN(n_x ,«₂) middle switches are necessary for strictly nonblocking operation. To prove the sufficient condition, it is recalled that V(m,n_x,r_x,n₂,r₂) network operates in strictly nonblocking manner, when the multicast connections are fanned out only once in the first stage, if m ≥ I ^ Jx MM(n_x ,n₂) . The worst case m is required when the fan-out of connections is / = 3. So the proof when n_x = n₂ = [Jϊζ J= 3 is sufficient, to prove for the most general case of «, and n₂. The following cases are considered:

1) / ≤ 2 : It is clear that m ≥ lx MIN(n_x ,n₂) is sufficient.

1) f = 3,4 : Since the multicast connection is arbitrarily split into two, each of the two fan-out-spilt connections will have a fan-out of at most only 2. Hence m ≥ lx MIN(n_x ,n₂) is sufficient.

3) / 5 : There cannot be more than 6 fan-out-spilt connections of fan-out 3, and so m ≥ lx MIN (n_x,n₂) are sufficient.

Hence the proof, and in accordance with the current invention, the three-stage network V(m, n_x,r_x,n₂,r₂) is operable in strictly nonblocking manner when m ≥ lx MIN(n_x , n₂ ) where r₂ e [9,11] , by arbitrarily splitting multicast connections twice and fanning out twice from the input switch when the fan-out of multicast connection is / e [3,4] ; and otherwise by fanning out the connection only once in the input switch.

2) Based on this proof the following two observations are made:

1) The V(m, n_x,r_x,n₂,r₂) network is operable in strictly nonblocking manner when m ≥ 2.3 x MIN(n_x , n₂ ) when r₂ e [12,13] , by arbitrarily fan-out-splitting multicast connections twice and fanning out twice from the input switch when the fan-out of multicast connection is / e [3,4] ; and otherwise by fanning out the connection only once in the input switch.

2) The V(m, n_x,r_x,n₂,r₂) network is operable in strictly nonblocking manner when m ≥ l.βx MIN(n , n₂ ) when r₂ e [14] , by arbitrarily fan-out-splitting multicast connections twice and fanning out twice from the input switch when the fan-out of multicast connection is / e [3,4] ; and otherwise by fanning out the connection only once in the input switch.

Table 3 summarizes the results for V(m, n, r) network when r e [9 - 14] , considered so far, to be operable in nonblocking manner according to the current invention.

Applicant notes that when r₂ e [15] , by arbitrarily fan-out-splitting multicast connections twice and fanning out twice from the input switch when the fan-out of multicast connection is / e [3,4] ; and otherwise by fanning out the connection only once in the input switch with m ≥ lx MIN(n_x , n₂ ) does not make V(m, n_x,r ,n₂,r₂) operable in

strictly nonblocking manner because ι i^'s not satisfied where

P = And so m ≥ 3 x MIN(n ,n₂) is required for this network to be

operable in strictly nonblocking manner. However from Table 2, it is easily observed that when r₂ e [15,24], V(m,n_x,r_x,n₂,r₂) network is operable in strictly nonblocking manner when m ≥ 3 x MIN(n_x ,n₂); and splitting the multicast connections does not reduce the number of required middle switches. It is the same case when r₂ e [16,24] .

The proofs given so far can be extended to the following V(m, n_x,r_x,n₂,r₂) networks as well:

The multicast connections with fan-out / e [5,12] are arbitrarily fan-out-split into three

so that all three fan-out-spilt connections have fan-out of either or and

otherwise the multicast connection is fanned out only once in the input switch. Then the three-stage network V(m,n_x,r_x,n₂,r₂) is operable in strictly nonblocking manner when

The multicast connections with fan-out / e [5,16] are arbitrarily fan-out-split into three

so that all three fan-out-spilt connections have fan-out of either or and

otherwise the multicast connection is fanned out only once in the input switch. Then the three-stage network V(m, n_x,r_x,n₂,r₂) is operable in strictly nonblocking manner when m ≥ 3 MIN(n_x,n₂).

Applicant notes that when r₂ G [49], by arbitrarily fan-out-splitting multicast connections three times and fanning out three times from the input switch when the fan-out of multicast connection is / e [5,18] ; and otherwise by fanning out the connection only once in the input switch with m > 3 MIN(n_x , n₂ ) does not make V(m, n_x,r ,n₂,r₂)

operable in strictly nonblocking manner because ^x frJl < 5 X &. is not satisfied where

be operable in strictly nonblocking manner.

Table 4 summarizes the results for V(m, n, r) network when e [15- 48] , considered so far, to be operable in nonblocking manner according to the current invention.

6) Vim. n_x,r .n₂,r₂) network with r₂ e [49.63] where -/>Tje 7 :

The multicast connections with fan-out / e [5,24] are arbitrarily fan-out-split into four so

that all four fan-out-spilt connections have fan-out of either or and otherwise

the multicast connection is fanned out only once in the input switch. Then the three-stage network V(m, n_x,r ,n₂,r₂) is operable in strictly nonblocking manner when m > 4x N(«,,«₂).

The multicast connections with fan-out / e [5,24] are arbitrarily fan-out-split into tour so

that all four fan-out-spilt connections have fan-out of either or and otherwise

the multicast connection is fanned out only once in the input switch. Then the three-stage network V(m, n_x,r_x,n₂,r₂) is operable in strictly nonblocking manner when

The multicast connections with fan-out / e [5,20] are arbitrarily fan-out-split into four so

that all four fan-out-spilt connections have fan-out of either or and otherwise

the multicast connection is fanned out only once in the input switch. Then the three-stage network V(m, n ,r_x,n₂,r₂) is operable in strictly nonblocking manner when

Applicant notes that when r₂ e [100] , by arbitrarily fan-out-splitting multicast connections four times and fanning out four times from the input switch when the fan-out of multicast connection is / e [5,25] ; and otherwise by fanning out the connection only once in the input switch with m ≥ 4 x MIN(n_x , n₂ ) does not make V(m, n_x,r ,n₂,r₂)

operable in strictly nonblocking manner because 2 * is not

satisfied i.e., 2 * > 4 x 10. And so m ≥ 5 x MIN(n_x ,n₂) is required for this

network to be operable in strictly nonblocking manner.

Table 5 summarizes the results for V(m, n, r) network when r e [49 - 99] , considered so far, to be operable in nonblocking manner according to the current invention.

The multicast connections with fan-out / e [7,31] are arbitrarily fan-out-split into five so

that all five fan-out-spilt connections have fan-out of either or and otherwise the

multicast connection is fanned out only once in the input switch. Then the three-stage network V(m, _x,r_x,n₂,r₂) is operable in strictly nonblocking manner when m ≥ 5 x MM(n_x,n₂) .

The multicast connections with fan-out / e [7,30] are arbitrarily fan-out-split into five so

multicast connection is fanned out only once in the input switch. Then the three-stage network V(m,n_x,r_x,n₂,r₂)is operable in strictly nonblocking manner when m ≥ 5 x MLN(n_x , n₂ ) .

11 ) Vim. n_x , r_x ,n₂.r₂) network with r₂ e [144.154] where \_fc\= ll: The multicast connections with fan-out / e [7,30] are arbitrarily fan-out-split into five so that all five fan-out-spilt connections have fan-out of either or and otherwise the multicast connection is fanned out only once in the input switch. Then the three-stage network V(m, n_x,r_x,n₂,r₂) is operable in strictly nonblocking manner when m ≥ 5xMIN(n_x,n₂) .

Applicant notes that when r₂ e [155] , by arbitrarily fan-out-splitting multicast connections five times and fanning out five times from the input switch when the fan-out of multicast connection is / e [7,31]; and otherwise by fanning out the connection only once in the input switch with m ≥ 5 MIN(n , n₂ ) does not make V(m, n_x,r_x,n₂,r₂)

operable in strictly nonblocking manner because 2 * < sx[fc] is not

satisfied i.e., > 5 x 12. And so m ≥ 6 MIN(n_x ,n₂) is required for this

network to be operable in sfrictly nonblocking manner.

Table 7 summarizes the results for V(m, n, r) network when r e [100 - 154] , considered so far, to be operable in nonblocking manner according to the current invention.

12) Vim.n_x.r_x.n₂.r₂) network with r₂ e [155.168] where [fc^ ll:

The multicast connections with fan-out / ≡ [7,36] are arbitrarily fan-out-split into six so

that all six fan-out-spilt connections have fan-out of either or and otherwise the

multicast connection is fanned out only once in the input switch. Then the three-stage network V(m, n_x,r ,n₂,r₂) is operable in strictly nonblocking manner when m ≥ 6x MIN(n_x,n₂) .

The multicast connections with fan-out / e [7,36] are arbitrarily fan-out-split into six so

multicast connection is fanned out only once in the input switch. Then the three-stage network V(m, n_x,r_x,n₂,r₂) is operable in strictly nonblocking manner when m ≥ 6xMIN(n_x,n₂) .

multicast connection is fanned out only once in the input switch. Then the three-stage network V(m, n_x,r_x,n₂,r₂) is operable in strictly nonblocking manner when m > 6x ZN(n,,«₂) .

Applicant notes that when r₂ e [225] , by arbitrarily fan-out-splitting multicast connections five times and fanning out five times from the input switch when the fan-out of multicast connection is / e [7,32] ; and otherwise by fanning out the connection only once in the input switch with m ≥ 6 x MIN(n_x , n₂ ) does not make V(m, n ,r_x,n₂,r₂)

operable in strictly nonblocking manner because ^{s not} satisfied

i.e., > 6 x 15. And so m ≥ l MIN(n_x ,n₂) is required for this network to be

operable in strictly nonblocking manner.

Table 7 summarizes the results for V(m, n, r) network when r e [155 - 224] , considered so far, to be operable in nonblocking manner according to the current invention.

The multicast connections with fan-out / e [9,56] are arbitrarily fan-out-split into seven

so that all seven fan-out-spilt connections have fan-out of either or and

otherwise the multicast connection is fanned out only once in the input switch. Then the three-stage network V(m, n ,r_x,n₂,r₂) is operable in strictly nonblocking manner when m ≥ 7xMIN(n_x,n₂).

The multicast connections with fan-out / e [9,56] are arbitrarily fan-out-split into seven so that all seven fan-out-spilt connections have fan-out of either or and otherwise the multicast connection is fanned out only once in the input switch. Then the three-stage network V(m, n ,r_x,n₂,r₂) is operable in strictly nonblocking manner when

Table 8 summarizes the results for V(m, n, r) network when r e [225 - 278] , considered so far, to be operable in nonblocking manner according to the current invention.

Referring to FIG. 5A a five stage strictly nonblocking network is shown according to an embodiment of the present invention that uses recursion as follows. The five stage network comprises input stage 110 and output stage 120, with inlet links IL1-IL12 and outlet links OL1-OL12 respectively, where input stage 110 consist of six, two by four switches IS1-IS6, and output stage 120 consist of six, four by two switches OS1-OS6. However, unlike the single switches of middle stage 130 of the three-stage network of FIG. 1A, the middle stage 130 of FIG. 5A consists of four, six by six three-stage subnetworks MS1-MS4 (wherein the term "subnetwork" has the same meaning as the term "network"). Each of the four middle switches MS1-MS4 are connected to each of the input switches through six first internal links (for example the links FL1-FL6 connected to the middle switch MSI from each of the input switch IS1-IS6), and connected to each of the output switches through six second internal links (tor example the links SL1-SL6 connected from the middle switch MSI to each of the output switch OS 1-OS6). In one embodiment, the network also includes a controller coupled with the input stage 110, output stage 120 and middle stage subnetworks 130 to form connections between inlet links ILl-ιL12 and an arbitrary number of outlet links OL1-OL12.

Each of middle switches MS1-MS4 is a V (4,1,3) three-stage subnetwork. For example, the three-stage subnetwork MSI comprises input stage of three, two by four switches MIS1-MIS3 with inlet links FL1-FL6, and an output stage of three, four by two switches MOS1-MOS3 with outlet links SL1-SL6. The middle stage of MSI consists of four, three by three switches MMS1-MMS4. Each of the middle switches MMS1-MMS4 are connected to each of the input switches MIS1-MIS3 through three first internal links (for example the links MFL1-MFL3 connected to the middle switch MMSl from each of the input switch MIS1-MIS3), and connected to each of the output switches MOS1- MOS3 through three second internal links (for example the links MSL1-MSL3 connected from the middle switch MMSl to each of the output switch MOS1-MOS3). In similar fashion the number of stages can increase to 7, 9, etc.

According to the present invention, the three-stage network of FIG. 5 A requires no more than m ≥ s * n where

5 = 2 when r = [9,l l], 5 = 3 when r = [25,48], 5 = 4 when r = [49,99], 5 = 5 when r = [l00,154], 5 = 6 when r = [155,224], and 5 = 7 when r = [225,278]. middle stage three-stage subnetworks to be operable in strictly nonblocking manner. Thus in FIG. 5 A where n equals 2 and r equals 6, middle stage 130 has 5χ nequals four middle stage three-stage networks MS1-MS4. Furthermore, according to the present invention, each of the middle stage networks MS1-MS4, in turn, are three-stage networks and require no more than m ≥ s*n where

5 = 2 when q = [9,11] , 5 = 3 when q = [25,48], 5 = 4 when q = [49,99], 5 = 5 when # = [100,154], 5 = 6 when q = [155,224], and 5 = 7 when q = [225,278]. middle switches MMS1-MMS4, where p is the number of inlet links for each middle input switch MIS1-MIS3 with q being the number of switches in the input stage (equals to 3 in FIG. 5 A) and p is the number of outlet links for each middle output switch MOS1-MOS3 with q being the number of switches in the output stage (equals to 3 in FIG. 5A).

In general, according to certain embodiments, one or more of the switches, in any of the first, middle and last stages can be recursively replaced by a three-stage subnetwork with no more than m ≥ s * MLN(n_x , n₂ ) where

5 = 2 when r₂ = [9,l l], 5 = 3 when r₂ = [25,48], 5 = 4 when r₂ = [49,99], 5 = 5 when r₂ = [100,154], s = 6 when r₂ = [l 55,224], and 5 = 7 when r₂ = [225,278].

middle stage switches where «, is the number of inlet links to the first stage switch in the subnetwork with r_x being the number of switches in the first stage of the subnetwork and «, is the number of outlet links to the last stage switch of the subnetwork with r₂ being the number of switches in the last stage of the subnetwork, for strictly nonblocking operation for multicast connections of arbitrary fan-out. Note that because the term "subnetwork" has the same meaning as "network", the just described replacement can be repeated recursively, as often as desired, depending on the embodiment. Also each subnetwork may have a separate controller and memory to schedule the multicast connections of corresponding network.

It should be understood that the methods, discussed so far, are applicable to k- stage networks for k>3 by recursively using the design criteria developed on any of the switches in the network. The presentation of the methods in terms of three-stage networks is only for notational convenience. That is, these methods can be generalized by recursively replacing each of a subset of switches (at least 1) in the network with a smaller three-stage network, which has the same number of total inlet links and total outlet links as the switch being replaced. For instance, in a three-stage network, one or more switches in either the input, middle or output stages can be replaced with a three- stage network to expand the network. If, for example, a five-stage network is desired, then all middle switches (or all input switches or all output switches) are replaced with a three-stage network

In accordance with the invention, in any of the recursive three-stage networks each connection can fan out in the first stage switch into only one middle stage subnetwork, and in the middle switches and last stage switches it can fan out any arbitrary number of times as required by the connection request. For example as shown in the network of FIG. 5 A, connection Ii fans out in the first stage switch ISl once into middle stage subnetwork MSI. In middle stage subnetwork MSI it fans out three times into output switches OSl, OS2, and OS3. In output switches OSl and OS3 it fans out twice. Specifically in output switch OSl into outlet links OL1, OL2, and in output switch OS3 into outlet links OL5, OL6. In output switch OS2 it fans out once into outlet link OS4. However in the three-stage network MSI, it can fan out only once in the first stage, for example connection Ij fans out once in the input switch MISl into middle switch MMS2 of the three-stage subnetwork MSI. Similarly a connection can fan out arbitrary number of times in the middle and last stages of any three-stage subnetwork. For example connection Ii fans out twice in middle switch MMS2 into output switches MOS1 and MOS2 of three-stage subnetwork MSI. In the output switch MOS1 of three-stage subnetwork MSI it fans out twice into output switches OSl and OS2. And in the sutput switch MOS2 of three-stage subnetwork MSI it fans out once into output switch OS3.

The connection I₃ fans out once into three-stage subnetwork MS2 where it is fanned out three times into output switches OS2, OS4, and OS6. In output switches OS2, OS4, and OS6 it fans out once into outlet links OL3, OL8, and OL12 respectively. The connection I₃ fans out once in the input switch MIS4 of three-stage subnetwork MS2 into middle switch MMS6 of three-stage subnetwork MS2 where it fans out three times into output switches MOS4, MOS5, and MOS6 of the three-stage subnetwork MS2. In each of the three output switches MOS4, MOS5 and MOS6 of the three-stage subnetwork MS2 it fans out once into output switches OS2, OS4, and OS6 respectively.

FIG. 5B shows a high-level flowchart of a strictly scheduling method, in one embodiment executed by the controller of FIG. 5A. The method of FIG. 5B is used only for networks that have three stages each of which may be in turn composed of three-stage subnetworks, in a recursive manner as described above in reference to FIG. 5A. According to this embodiment, a multicast connection request is received in act 250 (FIG. 5B). Then a connection to satisfy the request is set up in act 260 by fanning out, one or more times when fan-out-split, into middle stage subnetwork from its input switch. Then, in one embodiment, the control goes to act 270. Act 270 recursively goes through each subnetwork contained in the network. For each subnetwork found in act 270 the control goes to act 280 and each subnetwork is treated as a network and the scheduling is performed similarly. Once all the recursive subnetworks are scheduled the control transfers from act 270 to act 250 so that each multicast connection will be scheduled in the same manner in a loop.

A V(m, n ,r_x,n₂,r₂) network can be further generalized, in an embodiment, by having an input stage comprising r_x input switches and n_Xw inlet links in input switch w, for each of said r, input switches such that w e [l,r,] and n_x = MAX(n_Xw); an output stage comprising r₂ output switches and n_2v outlet links in output switch v, for each of said r₂ output switches such that v e [l,r₂] and n₂ = MAX(n_2v); and a middle stage comprising m middle switches, and each middle switch comprising at least one link connected to each input switch for a total of at least r, first internal links; each middle switch further comprising at least one link connected to at most d said output switches for a total ot at least d second internal links, wherein \ < d ≤ r₂ , and applicant notes that such an embodiment can be operated in strictly nonblocking manner, according to the current invention, for multicast connections by fanning out only once in the input switch if m ≥ s* MIN(n_x , n₂ ) where

5 = 2 when r₂ = [9,l l], 5 = 3 when r₂ = [25,48], 5 = 4 when r₂ = [49,99], 5 = 5 when r₂ = [100,154], 5 = 6 when r₂ = [155,224], and 5 = 7 when r₂ = [225,278].

The V(m,n_x,r_x,n₂,r₂) network embodiments described so far, in the current invention, are implemented in space-space-space, also known as SSS configuration. In this configuration all the input switches, output switches and middle switches are implemented as separate switches, for example in one embodiment as crossbar switches. The three-stage networks V(m,n ,r_x,n₂,r₂) can also be implemented in a time-space- time, also known as TST configuration. In TST configuration, in the first stage and the last stage all the input switches and all the output switches are implemented as separate switches. However the middle stage, in accordance with the current invention, uses s number of switches if m ≥ s * MIN(n_x , n₂ ) where

5 = 2 when r₂ = [9,11], 5 = 3 when r₂ = [25,48], 5 = 4 when r₂ = [49,99], 5 = 5 when r₂ = [100,154], 5 = 6 when r₂ = [l 55,224], and 5 = 7 when r₂ ~ [225,278], with each middle switch having r, first internal links connected to all input switches and also having r₂ second internal links connected to all output switches. The TST configuration implements the switching mechanism, in accordance with the current invention, in MIN(n_x,n₂) steps in a circular fashion. So in TST configuration, the middle stage physically implements only s middle switches; and they are shared in time in, MN(n_x,n₂) steps, to switch packets or timeslots from input ports to the output ports.

The three-stage networks V(m, n_x,r_x,n₂,r₂) implemented in TST configuration play a key role in communication switching systems. In one embodiment a crossconnect in a TDM based switching system such as SONET/SDH system, each communication link is time-division multiplexed - as an example an OC-12 SONET link consists of 336 VT1.5 channels time-division multiplexed. In another embodiment a switch fabric in packet based switching system switching such as IP packets, each communication link is statistically time division multiplexed. When a V(m,n_x,r_x,n₂,r₂) network is switching TDM or packet based links, each of the r_x input switches receive time division multiplexed signals - for example if each input switch is receiving an OC-12 SONET stream and if the switching granularity is VT1.5 then n_x (= 336) inlet links with each inlet link receiving a different VT1.5 channel in a OC-12 frame. A crossconnect, using a V(m,n_x,r_x,n₂,r₂) network, to switch implements a TST configuration, so that switching is also performed in time division multiplexed fashion just the same way communication in the links is performed in time division multiplexed fashion.

For example, the network of FIG. 6 A shows an exemplary three-stage network, namely F (6,3,4) in space-space-space configuration, with the following multicast assignment /, = {l}, I₂ = {l,3,4}, I₆ = {3}, I₉ = {2}, I _x = {4} and l_n = {3,4}. According to the current invention, the multicast assignment is setup by fanning out each connection not more than once in the first stage. The connection I_x fans out in the first stage switch ISl into the middle stage switch MSI, and fans out in middle switch MSI into output switch OSl. The connection I_x also fans out in the last stage switch OSl into the outlet links OL2 and OL3. The connection I₂ fans out in the first stage switch ISl into the middle stage switch MS3, and fans out in middle switch MS3 into output switches OSl, OS3, and OS4. The connection I₂ also fans out in the last stage switches OSl, OS3, and OS4 into the outlet links OL1, OL7 and OL12 respectively. The connection I₆ fans out once in the input switch IS2 into middle switch MS2 and fans out in the middle stage switch MS2 into the last stage switch OS3. The connection I₆ fans out once in the output switch OS3 into outlet link OL9.

The connection I₉ fans out once in the input switch IS3 into middle switch MS4, fans out in the middle switch MS4 once into output switch OS2. The connection I₉ fans out in the output switch OS2 into outlet links OL4, OL5, and OL6. The connection /,, fans out once in the input switch IS4 into middle switch MS6, fans out in the middle switch MS6 once into output switch OS4. The connection /,, fans out in the output switch OS4 into outlet link OLIO. The connection I_x2 fans out once in the input switch IS4 into middle switch MS5, fans out in the middle switch MS5 twice into output switches OS3 and OS4. The connection I_X2 fans out in the output switch OS3 and OS4 into outlet links OL8 and OL11 respectively.

FIG. 6B, FIG. 6C and FIG. 6D illustrate the implementation of the TST configuration of the (6,3,4) network of FIG. 6A. According to the current invention, in TST configuration also the multicast assignment is setup by fanning out each connection not more than once in the first stage, with exactly the same the scheduling method as it is performed in SSS configuration. Since in the network of FIG. 6A n = 3 , the TST configuration of the network of FIG. 6A has n = 3 different time steps; and since 5 = 2 , the middle stage in the TST configuration implements only 2 middle switches each with 4 first internal links and 4 second internal links as shown in FIG. 6B, FIG. 6C, and FIG. 6D. In the first time step, as shown in FIG. 6B the two middle switches function as MSI and MS2 of the network of FIG. 6A. Similarly in the second time step, as shown in FIG. 6C the two middle switches function as MS3 and MS4 of the network of FIG. 6A and in the third time step, as shown in FIG. 6D the two middle switches function as MS5 and MS6 of the network of FIG. 6A. In the first time step, FIG. 6B implements the switcnmg tunctionanτy oi miuuie switches MSI and MS2, and since in the network of FIG. 6A, connections I_x and I₆ are fanned out through middle switches MSI and MS2 to the output switches OSl and OS3 respectively, and so connections 7, and 7₆ are fanned out to destination outlet links OL2, OL3 and OL9 respectively, just exactly the same way they are set up in the network of FIG. 6A in all the three stages. Similarly in the second time step, FIG. 6C implements the switching functionality of middle switches MS3 and MS4, and since in the network of FIG. 6A, connections 7₂ and 7₉ are fanned out through middle switches MS3 and MS4 to the output switches {OSl, OS3, OS4} and OS2 respectively, and so connections 7₂ and 7₉ are fanned out to destination outlet links {OL1, OL7, OL12} and {OL4, OL5,

OL6} respectively, just exactly the same way they are set up in the network of FIG. 6A in all the three stages.

Similarly in the third time step, FIG. 6D implements the switching functionality of middle switches MS5 and MS6, and since in the network of FIG. 6A, connections 7_U and 7₁₂ are fanned out through middle switches MS5 and MS6 to the output switches OS4 and {OS3, OS4} respectively, and so connections 7_n and 7₁₂ are fanned out to destination outlet links OLIO and {OL8, OL11 } respectively, just exactly the same way they are routed in the network of FIG. 6A in all the three stages. In digital cross connects, optical cross connects, and packet or cell switch fabrics since the inlet links and outlet links are used time-division multiplexed fashion, the switching network such as the V(m,n_x,r_x,n₂,r ) network implemented in TST configuration will save cost, power and space. in accordance with the invention, the V(m,n_x,r_x,n₂,r₂) network implemented in TST configuration, using the same scheduling method as in SSS configuration i.e., with each connection fanning out in the first stage switch into only one middle stage switch, and in the middle switches and last stage switches it can fan out any arbitrary number of times as required by the connection request, is operable in strictly nonblocking manner with number of middle switches is equal to s, if m ≥ s * MIN(n_x,n₂) where

5 = 2 when r₂ = [9,l l], 5 = 3 when r₂ = [25,48], 5 = 4 when r₂ = [49,99], 5 = 5 when r₂ = [100,154], 5 = 6 when r₂ = [155,224], and 5 = 7 when r₂ = [225,278]. Numerous modifications and adaptations of the embodiments, implementations, and examples described herein will be apparent to the skilled artisan in view of the disclosure.

For example the current invention can be extended for a Vim, n_x,r ,n₂,r₂) for r₂ > 278.

For example, in one embodiment, a method of the type described above is modified to set up a multirate multi-stage network as follows. Specifically, a multirate connection can be specified as a type of multicast connection. In a multicast connection, an inlet link transmits to multiple outlet links, whereas in a multirate connection multiple inlet links transmit to a single outlet link when the rate of data transfer of all the paths in use meet the requirements of multirate connection request. In such a case a multirate connection can be set up (in a method that works backwards from the output stage to the input stage), with fan-in (instead of fan-out) of not more than s in the output stage and arbitrary fan-in in the input stages and middle stages. And a three-stage multirate network is operated in strictly nonblocking manner with the exact same requirements on the number of middle stage switches as described above for certain embodiments.

Numerous such modifications and adaptations are encompassed by the attached claims.

Claims

CLAIMSWhat is claimed is:

1. A network having a plurality of multicast connections, said network comprising: an input stage comprising r_x input switches, and «, inlet links for each of said r, input switches; an output stage comprising r₂ output switches, and n₂ outlet links for each of said r₂ output switches; and a middle stage comprising m middle switches, and each middle switch comprising at least one link (hereinafter "first internal link") connected to each input switch for a total of at least r first internal links, each middle switch further comprising at least one link (hereinafter "second internal link") connected to each output switch for a total of at least r₂ second internal links; said network further is always capable of setting up said multicast connection by never changing path of an existing multicast connection, and the network is hereinafter "strictly nonblocking network", if m ≥ s * MIN(n_x , n₂ ) where 5 = 2 when r₂ = [9,l l], 5 = 3 when r₂ = [25,48], 5 = 4 when r₂ = [49,99], 5 = 5 when r₂ = [l00,154], s = 6 when r₂ = [l 55,224], and 5 = 7 when r₂ = [225,278]; wherein each multicast connection from an inlet link passes through at most s middle switches, and said multicast connection further passes to a plurality of outlet links from said at most s middle switches.

2. The network of claim 1 further comprising a controller coupled to each of said input, output and middle stages to set up said multicast connection.

3. The network of claim 1 wherein said r, input switches and r₂ output switches are the same number of switches and r, = r₂ = r .

4. The network of claim 1 wherein said », inlet links and n₂ outlet links are the same number of links and n_x = n₂ - n, then m > s * n where 5 = 2 when r₂ = [9,l l], 5 = 3 when r₂ = [25,48], 5 = 4 when r₂ = [49,99], 5 = 5 when r₂ = [100,154], 5 = 6 when r₂ = [l 55,224], and 5 = 7 when r₂ = [225,278].

5. The network of claim 1, wherein each of said input switches, or each of said output switches, or each of said middle switches further recursively comprise one or more networks.

6. A method for setting up one or more multicast connections in a network having an input stage having n * r_x inlet links and r, input switches, an output stage having n₂ * r₂ outlet links and r₂ output switches, and a middle stage having m middle switches, where each middle switch is connected to each of said input switches through r, first internal links and each middle switch further comprising at least one link connected to at most d said output switches for a total of at least d second internal links, wherein 1 < d ≤ r₂ , and said multicast connection has a fan-out / ; said method comprising: wherein the set of all the destination output switches of said multicast connection is arbitrarily divided into at most s subsets, where 5 = 2 when r₂ = [9,l l], 5 = 3 when r₂ = [25,48], 5 = 4 when r, = [49,99], 5 = 5 when r₂ = [100,154], 5 = 6 when r₂ = [l 55,224], and 5 = 7 when r₂ = [225,278]; such that each destination output switch of said multicast connection is in only one of said s subsets of destination output switches, checking if at least a first subset of destination output switches of said subsets of said multicast connection have available second internal links to a first middle switch.

7. The method of claim 6 further comprising: checking if the input switch of said multicast connection has an available first internal link to said first middle switch.

8. The method of claim 6 further comprising: prior to said checkings, checking if all the destination output switches of said multicast connection are available at said first middle switch when / < 3 if r₂ = [9,99], / < 5 if r₂ = [100,224], / < 7 if r₂ = [225,278].

9. The method of claim 6 further comprising: repeating said checkings of available first and second internal links to said first subset of destination output switches for each middle switch other than said first middle switch.

10. The method of claim 6 further comprising: repeating said checking of available first and second internal links to all the destination output switches for each middle switch other than said first middle switch when / < 3 if r₂ = [9,99], f < 5 if r₂ = [100,224], / < 7 if r₂ = [225,278].

11. The method of claim 6 further comprising: repeating said checkings of available first and second internal links to all the remaining s subsets of said multicast connection for each middle switch.

12. The method of claim 6 further comprising: setting up each of said multicast connection from its said input switch to its said output switches through not more than s middle switches, selected by said checkings, by fanning out said multicast connection in its said input switch into not more than said s middle stage switches.

13. The method of claim 6 wherein any of said acts of checking and setting up are performed recursively.

14. A network having a plurality of multicast connections, said network comprising: an input stage comprising r, input switches, and n_Xv inlet links in input switch w , for each of said η input switches such that w e [l,r,] and n_x = MAX(n_Xw); an output stage comprising r₂ output switches, and n_lv outlet links in output switch v, for each of said r₂ output switches such that v e [l,r₂] and n₂ = MAX(n_2v); and a middle stage comprising m middle switches, and each middle switch comprising at least one link (hereinafter "first internal link") connected to each input switch for a total of at least r_x first internal links, each middle switch further comprising at least one link (hereinafter "second internal link") connected to at most d said output switches for a total of at least d second internal links, wherein 1 < d ≤ r₂ , and; said network further is always capable of setting up said multicast connection by never changing path of an existing multicast connection, and the network is hereinafter "strictly nonblocking network", if m ≥ s*MLN(n_x,n₂) where 5 = 2 when r₂ = [9,11] , 5 = 3 when r₂ = [25,48], 5 = 4 when r₂ = [49,99], 5 = 5 when r₂ = [l00,154], 5 = 6 when r₂ = [l 55,224], and 5 = 7 when r₂ = [225,278]; wherein each multicast connection from an inlet link passes through at most s middle switches, and said multicast connection further passes to a plurality of outlet links from said at most s middle switches.

15. The network of claim 14 further comprising a controller coupled to each of said input, output and middle stages to set up said multicast connection.

16. The network of claim 14 wherein said r, input switches and r₂ output switches are the same number of switches and r_x ~ r₂ - r .

17. The network of claim 14 wherein said «, inlet links and n₂ outlet links are the same number of links and «, = n₂ = n , then m ≥ s * n where 5 = 2 when r₂ = [9,l l], 5 = 3 when r₂ = [25,48], 5 = 4 when r₂ = [49,99], 5 = 5 when r₂ = [100,154], s = 6 when r₂ = [l 55,224], and 5 = 7 when r₂ = [225,278].

18. The network of claim 14, wherein each of said input switches, or each of said output switches, or each of said middle switches further recursively comprise one or more networks.