WO2005022808A2

WO2005022808A2 - Multiple bonded channel extensions to th ieee 802.11 standard

Info

Publication number: WO2005022808A2
Application number: PCT/US2004/027047
Authority: WO
Inventors: Kevin J. Smart
Original assignee: Micro Linear Corporation
Priority date: 2003-09-02
Filing date: 2004-08-18
Publication date: 2005-03-10
Also published as: TW200511772A; WO2005022808A3

Abstract

The present invention discloses an apparatus for and a method of increasing the bandwidth available for data communications, including a channel extender comprising a data allocator and a channel assembler. The data allocator allocates data contained in a digital data signal among a plurality of data segments transmitted along a plurality of corresponding logical channels. The channel assembler translates each of the data segments into a plurality of modulated data signals and combines them to form a composite data signal. A channel restorer extracts the digital data signal from the composite signal. The channel restorer comprises a channel disassembler and a data deallocator. The channel disassembler translates data contained in a composite signal into a plurality of data segments. The data deallocator translates the data segments to recover the digital data signal.

Description

MULTIPLE BONDED CHANNEL EXTENSIONS TO THE IEEE 802.11 STANDARD

Field of the Invention This invention relates to the field of data communications. More particularly, this invention relates to increasing the bandwidth available for transmitting data under the IEEE 802.1 la and 802.1 lg protocols.

Background of the Invention Wireless communications systems allow computer users to be more mobile, and hence more productive. Using a wireless communications system, a user can access a network, and the files located on them, quickly, easily, and from many locations. One wireless transmission protocol, the IEEE 802. llg standard, defines usable channels in the 2.4 GHz band. Within this band a wireless device (a station) can communicate either with other stations or with an access point, a bridge to a wired network. Under the 802.1 lg standard, communications between two stations or between a station and an access point occur within only one channel. Compared to other transmission protocols, the 802.1 lg standard does not efficiently utilize the available bandwidth. In an Ethernet LAN, for example, when other hosts are not transmitting data along the Ethernet cable, two hosts may monopolize the available bandwidth by continually transmitting data. The available bandwidth is thus efficiently used. In contrast, under the IEEE 802.1 lg standard, a station transmits data along only a single channel even if unused channels are available. This limitation is most noticeable in data- intensive applications, such as streaming video, which require large bandwidths. Accordingly, what is needed is a wireless communications system that increases the bandwidth available for data communication.

Summary of the Invention In accordance with the present invention, a channel extender increases the bandwidth available for data transmission. Preferably, the channel extender receives a digital baseband signal from a source host, such as a personal computer, for transmission across a wireless medium to a destination host. The channel extender comprises a data allocator and a channel assembler. The data allocator allocates data contained in a digital signal among a plurality data segments. The channel assembler combines the data segments into a composite signal. The data segments are transmitted along a plurality of logical channels. The plurality of logical channels are each shifted to unique, non-overlapping frequencies and combined to form a composite signal. The composite signal is transmitted across the wireless medium to a channel restorer, as described below, which performs a function complementary to that of the channel extender. In one embodiment, the channel assembler comprises a plurality of modulators, a plurality of filters, a plurality of frequency shifters, and a signal combiner. Each logical channel is coupled to one corresponding modulator. In one embodiment, each modulator comprises an 802.1 lg or an 802.1 la modulator. In one embodiment, each modulator output is upsampled and filtered to give enough bandwidth for frequency shifting and combining. In operation, the data allocator receives a digital signal containing data from a source host. The data allocator allocates the digital signal among several data segments. Each data segment is input to the channel assembler, where a composite signal is generated. In one embodiment, the channel assembler is optimized for digital signals by using multirate filter components. In one embodiment, the data segments are modulated with a plurality of modulators. The modulator outputs are input into a corresponding frequency shifter. Each frequency shifter output is input to into a plurality of phase rotators. The plurality of outputs from the plurality of phase rotators are combined to form a plurality of intermediate signals. The plurality of intermediate signals are sent through a plurality of filters. Each filtered output is sequentially selected by a commutator to create the higher rate composite signal, preferably for transmission across a wireless medium. One skilled in the art will realize that this is equivalent to frequency shifting, upsampling, filtering, and combining. In accordance with another embodiment of the present invention, a channel restorer performs a function complementary to that of the channel extender. The channel restorer receives a composite signal from a channel extender, recovers the digital signal generated by the source host, and routes it to the destination host. A channel restorer in accordance with the present invention comprises a channel disassembler and a data deallocator. In one embodiment, the channel disassembler comprises a plurality of frequency shifters, a plurality of filters, a plurality of demodulators. A connection upon which a composite signal is received is coupled to each of the frequency shifters. Each of the frequency shifters is coupled to a corresponding filter. Each filter is coupled to a corresponding demodulator. Each demodulator is coupled to the data deallocator. Preferably, the channel data deallocator is coupled to a distribution system containing the destination host. In one embodiment, the demodulators each performs orthogonal frequency division demultiplexing, such as according to the IEEE 802.1 lg or 802.11a standard. In one embodiment, the channel disassembler comprises a plurality of filters, a plurality of phase rotator banks, a plurality of signal combiners, and a plurality of frequency shifters. Each filter is coupled to each phase rotator bank, which generates a plurality of outputs. The outputs of each phase rotator bank are coupled to a corresponding signal combiner. The output of each signal combiner is coupled to a corresponding frequency shifter. In operation, the received composite signal is digitally sampled and sequentially selected into the plurality of filters. The filtered outputs are sent to the plurality of phase rotator banks. The outputs of each phase rotator bank are combined and sent to the plurality of frequency shifters. The frequency shifter outputs are transmitted to the data deallocator and the plurality of data segments contained in the composite signal are recovered.

Brief Description of the Drawings Figure 1 is a schematic block diagram of a wireless communications system in accordance with the present invention. Figure 2 is a high-level schematic block diagram of a channel extender in accordance with one embodiment of the present invention. Figure 3 is a high-level schematic block diagram of a channel restorer in accordance with one embodiment of the present invention. Figure 4 is a schematic block diagram of an analog or digital channel assembler in accordance with one embodiment of the present invention. Figure 5 is a schematic block diagram of a digital channel assembler in accordance with one embodiment of the present invention. Figure 6 is a schematic block diagram of a digital channel assembler in accordance with one embodiment of the present invention. Figure 7 is a schematic block diagram of a channel assembler using an inverse FFT processor, in accordance with one embodiment of the present invention. Figure 8 is diagram showing how data blocks are allocated by a data allocator, in accordance with one embodiment of the present invention. Figure 9 is diagram showing how data blocks are allocated by a data allocator, in accordance with another embodiment of the present invention. Figure 10 is diagram showing how data bits are allocated by a data allocator, in accordance with another embodiment of the present invention. Figure 11 is a schematic block diagram of an analog or digital channel disassembler in accordance with one embodiment of the present invention. Figure 12 is a schematic block diagram of a digital channel disassembler in accordance with one embodiment of the present invention. Figure 13 is a schematic block diagram of a digital channel disassembler in accordance with one embodiment of the present invention. Figure 14 is a schematic block diagram of a channel disassembler using an FFT processor, in accordance with one embodiment of the present invention.

Detailed Description of the Preferred Embodiments Figure 1 illustrates a high level block diagram of one embodiment of a wireless communications system 100 in accordance with the present invention. Figure 1 shows a station 110 configured to transmit data according to a wireless protocol. The station 110 comprises a host 101 coupled by a bus 111 to a channel extender 125, described more fully below. The host 101 can be a personal computer, a personal digital assistant, or any other processor-based system. Preferably, the bus 111 is internal to the host 101. Alternatively, the bus 111 can be a channel external to the host 101. The channel extender 125 is coupled by a connection 114 to a transmitter 130. Preferably, the bus 111 is hard- wired. Alternatively, the bus 111 is a wireless channel or any medium that allows data to be transmitted between two points. Figure 1 also illustrates an access point 150 coupled by a channel 117 to a distribution system 165. The access point 150 comprises a receiver 151 coupled by a connection 116 to a channel restorer 155, described more fully below. The channel restorer 155 is coupled by a channel 117 to a distribution system 165. The distribution system 165 comprises a local area network cable 107 on which reside a plurality of hosts 161-163. Preferably, each of the channels 107 and 117 is a hard- wired channel. Alternatively, any or both of the channels 107 and 117 can be a wireless channel or any medium that allows data to be transmitted between two points. In operation, the host 101 on station 110 can communicate with any of the hosts 161- 163 on the distribution system. The host 101 transmits data in the form of a digital signal to the channel extender 125. As described in more detail below, the channel extender 125 allocates the data contained within the digital signal among several data segments that are later combined to form a composite signal. The channel extender 125 transmits the composite signal via the transmitter 130 to the access point 150, according to a wireless protocol. As described below, at the access point, the receiver 151 receives the composite signal and the channel restorer 155 recovers the digital signal originally generated by the station 101. The baseband data signal is then transmitted to a destination, one or more of the hosts 161-163. Figure 1 has been simplified to show a system for transmitting data signals from the host 101 on the station 110 to one or more of the hosts 161-163. The hosts 161-163 on the distribution system 165 can also be configured to transmit data to the host 101 via the access point 150. Thus, it will be appreciated that the access point can also be configured with a channel extender so that it can transmit data signals to a station or access point (e.g., station 110) in accordance with the present invention. Similarly, the host 101 can also be coupled with a channel restorer so that it can receive data signals from a station or access point (e.g., access point 150) in accordance with the present invention. It will be appreciated that while Figure 1 depicts the host 101 communicating with an access point 150, the host 101 can alternatively communicate with other systems, such as another host in accordance with the present invention. The following discussions describing a host communicating with an access point are for illustration only and do not limit the present invention. Figure 2 is a more detailed schematic of the channel extender 125 depicted in Figure 1. The bus 111 is coupled with the channel extender 125. The channel extender 125 comprises a data allocator 121 which outputs two data segments in the logical channels 112 and 113 to a channel assembler 122. Preferably, the channel assembler 122 is coupled by the connection 114 to a transmitter (e.g., 130, Figure 1). As described in more detail below, the data allocator receives a digital signal from a host and allocates the data contained in the digital signal among a plurality of data segments transmitted on plurality of logical channels. Figure 2 depicts a configuration for allocating data within the digital signal among two data segments transmitted on the two logical channels 112 and 113. It will be appreciated that in accordance with the present invention, data within the digital signal can be allocated among more than two logical channels. Figure 3 is a more detailed schematic of the channel restorer 155 depicted in Figure 1. Figure 3 depicts the connection 116 coupled at one end to the channel restorer 155. Preferably, the connection 116 is coupled on another end to a receiver (e.g., 151, Figure 1). Preferably, the channel restorer 155 is also coupled by the channel 117 to a distribution system (e.g., 165, Figure 1). As described in more detail below, the channel restorer 155 separates a composite signal received by the receiver into data segments that are transmitted along the logical channels 118 and 119 to a data deallocator 152. The data deallocator 152 then combines the relocated channel signals to reconstitute the digital signal originally transmitted by a host (e.g., 101, Figure 1). The data deallocator 152 then transmits the baseband data signal along the channel 117 to one or more hosts 161-163 on the distribution system (165, Figure 1). A description of the channel assembler 122 is now given, followed by a description of the data allocator 121. Later, a description of both the channel restorer 155 and the data deallocator 152 are given. Figure 4 illustrates a high-level overview of one embodiment of the channel extender 125 of Figure 2, comprising a data allocator 121 and a channel assembler 122. The embodiment illustrated in Figure 4 can be used to process analog or digital signals and thus can comprise analog or digital components. The channel assembler 122 comprises a plurality of modulators 715-1 through 715-N, a plurality of filters 720-1 through 720-N, a plurality of frequency shifters 730-1 through 730-N, and a signal combiner 740. As used herein, N is any integer greater than 1. As illustrated in Figure 4, the bus 111 is coupled at one end to an input of the data allocator 121. The data allocator 121 is coupled by the logical channels 201-1 through 201-N to the channel assembler 122 at inputs of the modulators 715-1 through 715-N. Thus, for example, the data allocator 121 is coupled by the logical channel 201-1 to an input of the modulator 715-1; by the logical channel 201-2 to an input of the modulator 715-2; up through the logical channel 201-N, which couples the data allocator 121 to an input of the modulator 715-N. It will be appreciated that when N equals 2, the logical channels 201-1 and 201-2 are the analogue of the logical channels 112 and 113, respectively. Each of the modulators 715-1 through 715-N has an output coupled to a corresponding filter 720-1 through 720-N, respectively. Thus, for example, the modulator 715-1 has a modulated output 716-1 coupled to an input of the filter 720-1; the modulator 715-2 has a modulated output 716-2 coupled to an input of the filter 720-2; up through the modulator 715-N, which has a modulated output 716-N coupled to an input of the filter 720- N. Each of the filters 720-1 through 720-N has a modulated output coupled to a corresponding frequency shifter 730-1 through 730-N, respectively. Thus, for example, an output of the filter 720-1 is coupled to an input of the frequency shifter 730-1; an output of the filter 720-2 is coupled to an input of the frequency shifter 730-2; up through the filter 720-N, which has an output coupled to an input of the frequency shifter 730-N. Each of the frequency shifters 730-1 through 730-N has an output coupled to an input of the signal combiner 740. Thus, for example, the frequency shifter 730-1 has an output coupled to an input of the signal combiner 740; the frequency shifter 730-2 has an output coupled to an input of the signal combiner 740; up through the frequency shifter 730-N, which has an output coupled to an input of the signal combiner 740. The signal combiner 740 has an output connection 114 that is preferably coupled to a transmitter (e.g., 130, Figure

1). In operation, the data allocator 121 receives on the bus I li a digital signal from the host 101. The digital signal contains information Data, such as data packets that the host 101 transmits to another host (e.g., 161, Figure 1) across a wireless medium. The data allocator 121 allocates segments of the Data among data segments and transmits the data segments along the N logical channels 201-1 through 201-N. Thus, as illustrated in Figure 4, the information Data, comprises data segments Data 1 through Data N. The segment Data 1 is in the form of a data signal transmitted along the logical channel 201-1; the segment Data 2 is in the form of a data signal transmitted along the logical channel 201-2; up through the segment Data N, which is in the form of a data signal transmitted along the logical channel 201-N. As will be described in more detail below, the segments Data 1 through Data N can later be recombined to recover the original information Data. Next, the modulator 715-1 modulates the data signal transmitted on the channel 201-1 (thus containing the segment Data 1) to produce a modulated output signal 716-1. The modulated output signal 716-1 is transmitted to the filter 720-1, which generates a filtered signal. The filtered signal is transmitted to the frequency shifter 730-1, which mixes the filtered signal with a local oscillator signal e^j2πfI to produce an output signal that is shifted in frequency fl hertz. The frequency shifted output signal is then transmitted to one input of the signal combiner 740. Data signals transmitted on the logical channels 201-2 through 201-N travel similar paths in parallel. Thus, for any integer K between 1 and N inclusive, the modulator 715-K modulates the data signal transmitted on the logical channel 201-K to generate a modulated output signal 716-K. The modulated output signal 716-K is transmitted to the filter 720-K, which generates a filtered output signal. The filtered output signal is then transmitted to an input of the frequency shifter 730-K, which mixes the filtered output signal with a local oscillator signal e^j2πfK to produce a signal that is shifted in frequency fK hertz. The frequency shifted output signal is then transmitted to one input of the signal combiner 740. The signal combiner 740 sums the output signals from each of the frequency shifters 730-1 through 730- N to generate a composite signal on the connection 114. Preferably, each of the modulators 715-1 through 715-N, each of the filters 720-1 through 720-N, each of the frequency shifters 730-1 through 730-N, and the signal combiner 740 is a digital component processing digital signals. It will be appreciated, however, that one or more of the modulators 715-1 through 715-N, one or more of the filters 720-1 through 720-N, one or more of the frequency shifters 730-1 through 730-N, and the signal combiner 740 can be either an analog or a digital component. Figure 5 is a high-level overview of a digital channel extender 800 in accordance with one embodiment of the present invention. Thus, the channel extender 800 receives a digital signal on the bus 111 and digitally processes it to generate a composite signal. The channel extender 800 comprises a data allocator 821 and a channel assembler 822. The channel assembler 822 comprises a plurality of 802.1 lg modulators 815-1 through 815-N, a plurality of modulated outputs 816-1 through 816-N, a plurality of upsamplers 818-1 through 818-N, a plurality of filters 820-1 through 820-N, a plurality of frequency shifters 830-1 through 830-N, and a signal combiner 840. Each of the 802.1 lg modulators 815-1 through 815-N, each of the modulated outputs 816-1 through 816-N, each of the upsamplers 818-1 through 818-N, each of the filters 820-1 through 820-N, each of the frequency shifters 830-1 through 830-N, and the signal combiner 840 is a digital component, processing digital signals. While the channel assembler 822 comprises 802.1 lg modulators, which function according to the IEEE 802.1 lg standard by using orthogonal frequency division multiplexing (OFDM), it will be appreciated that modulators that function according to other standards can be used in accordance with the present invention. For example, modulators can be used that function according to the IEEE 802.1 la standard, the IEEE 802.1 lb standard, another wireless communications protocol, or other data transmission protocols. Modulation according to the IEEE 802.1 la standard is described in ISO/TEC 8802-1 l:1999/Amd 1 :2000(E), titled "Part 11 : Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications; High-Speed Physical Layer in the 5GHz Band." As illustrated in Figure 5, the bus 111 is coupled at one end to an input of the data allocator 821. Logical output channels 801-1 through 801-N of the data allocator 821 are coupled to the channel assembler 822 at inputs of the 802.1 lg modulators 815-1 through 815- N. Thus, for example, the data allocator 821 is coupled by the channel 801-1 to an input of the 802.1 lg modulator 815-1; by the channel 801-2 to an input of the 802.1 lg modulator 815-2; up through the channel 801-N, which couples the data allocator 821 to an input of the 802.1 lg modulator 815-N. It will be appreciated that when N equals 2, the logical channels 801-1 and 801-2 are the analog to the logical channels 112 and 113 respectively. Each of the 802.11g modulators 815-1 through 815-N has an 802.11g modulated output 816-1 through 816-N, respectively, coupled to an input of a corresponding upsampler 818-1 through 818-N, respectively. Thus, for example, the 802. llg modulated output 816-1 of the 802.1 lg modulator 815-1 is coupled to an input of the upsampler 818-1; the 802.1 lg modulated output 816-2 of the 802.1 lg modulator 815-2 is coupled to an input of the upsampler 818-2; up through the 802.1 lg modulated output 816-N of the 802.1 lg modulator 815-N, which is coupled to an input of the upsampler 818-N. An output of each of the upsamplers 818-1 through 818-N is coupled to an input of a corresponding filter 820-1 through 820-N, respectively. Thus, for example, the output of the upsampler 818-1 is coupled to an input of the filter 820-1; the output of the upsampler 818-2 is coupled to an input of the filter 820-2; up through an output of the upsampler 818-N, which is coupled to an input of the filter 820-N. Each of the filters 820-1 through 820-N has an output coupled to an input of a corresponding frequency shifter 830-1 through 830-N, respectively. Thus, for example, an output of the filter 820-1 is coupled to an input of the frequency shifter 830-1; an output of the filter 820-2 is coupled to an input of the frequency shifter 830-2; up through an output of the filter 820-N, which is coupled to an input of the frequency shifter 830-N. Each of the frequency shifters 830-1 through 830-N has an output coupled to an input of the signal combiner 840. Thus, for example, the frequency shifter 830-1 has an output coupled to an input of the signal combiner 840; the frequency shifter 830-2 has an output coupled to an input of the signal combiner 840; up through the frequency shifter 830-N, which has an output coupled to an input of the signal combiner 840. The signal combiner 840 has an output connection 114 that is preferably coupled to a transmitter (e.g., 130, Figure

1). In operation, the data allocator 821 receives on the bus I li a digital baseband data signal from a host. The data allocator works in a manner similar to the data allocator 121 of

Figure 4, generating data signals containing data segments on the logical channels 801-1 through 801-N. Next, the 802.1 lg modulator 815-1 modulates the data signal transmitted on the logical channel 801-1 according to the 802. llg standard to produce an 802.1 lg modulated output signal 816-1. The 802.1 lg modulated output signal 816-1 is transmitted to the upsampler 818-1, which generates an upsampled signal. The upsampler increases the bandwidth available to the modulated output signal. The upsampled signal is transmitted to the filter 820-1, which generates a filtered output signal, which is transmitted to an input of the frequency shifter 830-1. The filter 820-1 is used to remove images produced by the upsampler 818-1. Thus, for example, if a segment Data 1 of a data signal Data 1 traveling on the logical channel 801-1 is sampled at 20 Mega samples per second (Msps), upsampling by three would produce a signal at 60 Msps having images. These images can be removed, for example, by a filter (e.g., 820-1) having a center frequency of 0 MHz and a bandwidth of 10 MHz. Next, the frequency shifter 830-1 mixes the filtered output signal with a local oscillator signal e^j2πfl to produce a frequency shifted output signal. The frequency shifted output signal is then transmitted to one input of the signal combiner 840. Data signals transmitted on the channels 801-2 through 801-N travel similar paths in parallel. Thus, for any integer K between 1 and N inclusive, the 802.1 lg modulator 815-K modulates the data signal transmitted on the channel 801-K to generate an 802. llg modulated output signal 816-K. The 802. llg modulated output signal 816-K is transmitted to the upsampler 818-K, which generates an upsampled signal. The upsampled signal is transmitted to the filter 820-K, which generates a filtered output signal, which is transmitted to an input of the frequency shifter 830-K. The frequency shifter 830-K mixes the filtered output signal with a local oscillator signal er^~2πiκ to produce a frequency shifted output signal. The frequency shifted output signal is then transmitted to one input of the signal combiner 840. The signal combiner 840 sums the frequency shifted output signals from each of the frequency shifters 830-1 through 830-N to generate a composite signal at the connection 114.

It will be appreciated that the data allocators illustrated in Figure 4 and Figure 5 will work with any digital signal having a limited bandwidth. It will also be appreciated that upsamplers, modulators, and mixers can be used in any combination and any order to combine relocated channels in accordance with the present invention. This will become clearer by analyzing the channel combiner 850 described in Figure 6. Figure 6 illustrates a more detailed view of one embodiment of a digital channel combiner 850 in accordance with the present invention. Figure 6 illustrates an embodiment that processes modulated digital data signals 410 and 411. The channel combiner 850 comprises two first-stage frequency shifters 412 and 413, two phase rotator banks 414 and 419, three signal combiners 420a-c, three filters 422a-c, and one commutator 430. Figure 6 illustrates a first modulated input 410 coupled with the first-stage frequency shifter 412. Similarly, a second modulated input 411 is coupled with the first-stage frequency shifter 417.

Preferably, the data signals on the first modulated input 410 and the second modulated input 411 are sampled at a critically-sampled data rate. In one embodiment, each of the modulated inputs 410 and 411 are signals that have been modulated according to the 802. l lg standard. The output from the first-stage frequency shifter 412 is coupled with the first phase rotator bank 414, which comprises a plurality of phase rotators 414a-c. The first-stage frequency shifter 412 is coupled with each of the plurality of phase rotators 414a-c. The output from the first-stage frequency shifter 417 is coupled with the second phase rotator bank 419, which comprises a plurality of phase rotators 419a-c. The first-stage frequency shifter 417 is coupled with each of the plurality of phase rotators 419a-c. As illustrated in Figure 6, selected pairs of outputs of the first phase rotator bank 414 and of the second phase rotator bank 419 are coupled with a set of signal combiners 420a-c. An output of the phase rotator 414a of the first phase-rotator bank 414 and an output of the phase rotator 419a of the second phase-rotator bank 419 are coupled with the signal combiner 420a. An output of the phase rotator 414b of the first phase-rotator bank 414 and an output of the phase rotator 419b of the second phase-rotator bank 419 are coupled with the signal combiner 420b. And an output of the phase rotator 414c of the first phase-rotator bank 414 and an output of the phase-rotator 419c of the second phase-rotator bank 41 are coupled with the signal combiner 420c. The output of each of the signal combiners 420a-c is coupled with a filter 422a-c, respectively. The output of the signal combiner 420a is coupled with the filter 422a. The output of the signal combiner 420b is coupled with the filter 422b. The output of the signal combiner 420c is coupled with the filter 422c. The output of each of the filters 422a-c is coupled to an input of the commutator 430. The commutator 430 is configured so that its input selectively couples with (e.g., sequentially selects) an output of one of the filters 422a-c. The commutator is programmed to select the outputs of the filters 422a-c in order; i.e., the output of the filter 422a is selected first, followed by the output of the filter 422b, followed by the output of the filter 422c, etc. The output of the commutator 430 is the connection 114. It will be appreciated that Figure 6 illustrates a multi-rate combination of two channels on the modulated inputs 410 and 411. It will be appreciated that the output sample rate is three times the sample rate of the modulated inputs 410 and 411. It will also be appreciated that the three filters 422a-c are parts of a bandpass filter used to select each band of interest. In this illustration, two channels are shifted in frequency, the relative phases are rotated (so that the filtering can be identical), the channels are combined, a bandpass filter is applied, and the combined signals are upsampled. In a preferred embodiment, the output of the commutator 430 (the connection 114) is coupled with a transmitter (e.g., 130, Figure 1) configured to transmit the composite data signal across a wireless medium. While Figure 6 illustrates a channel extender 122 having a first phase-rotator bank 414 with three phase rotators 414a-c, a second phase rotator-bank 419 with three phase rotators 419a-c, three signal combiners 420a-c, and three filters 422a-c, it will be appreciated that a channel extender in accordance with the present invention can have more or fewer components. For example, a channel extender may combine more than two channels. Additionally, a channel extender can contain four phase rotators in each phase-rotator bank, four signal combiners coupled with outputs of each phase-rotator bank, four filters each coupled with a signal combiner, and a commutator that sequentially selects one of four outputs from the filters. The number of phase rotators in a phase-rotator bank can be determined by an upsampling rate. Thus, for example, if an upsampling rate of 4:1 is desired, four phase rotators will be used in each phase- rotator bank, and four filters connected to each phase-rotator bank. In operation, a first modulated input signal 410 is input to the first-stage frequency shifter 412. As illustrated in Figure 6, the first-stage frequency shifter 412 shifts the center frequency of the modulated input 410 by multiplying the modulated input 410 with the sequence m₄₁₂. Preferably, the sequence m₄₁₂ is the signal (-1)", where n is a time index. Thus, in Figure 6, m₄₁₂ will take on the values -1 when time n=l, +1 when n=2, etc. In other words, m₄₁₂ will sequentially take on the values in the series {-1, +1, -1, +1, . . . }. It will be appreciated that the modulation signal m₄₁₂ can have other functions determined, for example, by the desired upsampling rate, the desired frequency shift, as well as other factors. The first frequency-shifted output signal is transmitted to the first phase rotator bank 414, and thus to each of the phase rotators 414a-c. The phase rotator 414a multiplies the output of the frequency shifter 412 with the constant signal m_414a to generate a phase rotated output signal on an output line of the phase rotator 414a. The phase rotator 414b multiplies the output of the frequency shifter 412 with the constant m_414b to generate a phase rotated output signal on an output line of the phase rotator 414b. The phase rotator 414c multiplies the output of the frequency shifter 412 with the constant m_414c to generate a phase rotated output signal on an output line of the phase rotator 414c. One embodiment of the present invention, referred to as Example 1, the constant m_414a is represented by the complex number e^(+0jπ/3), or 1 ; the constant m_4Mb is represented by the complex number e^{(+ljπ 3)}, or approximately 0.5 + jO.8660; and the constant m_414c is represented by the complex number e^{(+2jπ 3)}, or approximately -0.5 + jO.8660. Similarly, a second modulated input signal 411 is input to the first-stage frequency shifter 417. As illustrated in Figure 6, the first-stage frequency shifter 417 shifts the center frequency of the modulated input 411 by multiplying the modulated input 411 with the sequence m₄₁₇. In a preferred embodiment, the sequence m₄₁₇ is the signal (-l)ⁿ, where n is a time index. Thus, in Figure 6, m₄₁₇ will take on the values -1 when time n=l, +1 when n=2, etc. In other words, m₄₁₇ will sequentially take on the values in the series {-1, +1, -1, +1, . . .

}• The second frequency-shifted output signal is then transmitted to the second phase rotator bank 419, and thus to each of the phase rotators 419a-c. The phase rotator 419a multiplies the output of the frequency shifter 417 with the constant m_419a to generate a phase- rotated output signal on an output line of the phase rotator 419a. The phase rotator 419b multiplies the output of the frequency shifter 417 with the constant m_419b to generate a phase- rotated output signal on an output line of the phase rotator 419b. The phase rotator 419c multiplies the output of the frequency shifter 417 with the constant m_419o to generate a phase- rotated output signal on an output line of the phase rotator 419c. Continuing the Example 1, the constant m_419a is the complex number e^{("ojπ 3)}, or 1; the constant m_419b is the complex number e^{("ljπ 3)}, or approximately 0.5-J0.8660; and the constant m_419o is the complex number e^{("2jπ 3)}, or approximately -0.5 - jO.8660. In this Example 1, each phase rotator constant is a multiple of a single phase, π/3 radians. The first set of modulation signals m_414a - m_414c are thus conjugates of the second set of modulation signals m_419a - m_419c . It will be appreciated that the first set and second set of modulation signals do not have to be conjugates of each other. It will also be appreciated that the phase rotator constants in one set do not have to have phases that are all multiples of a single phase. Next, the output signal from the phase rotators 414a and 419a are transmitted to the signal combiner 420a, where they are linearly combined (added, in this example) to form an output signal. This output signal is transmitted to the filter 422a, which produces a first filtered output signal. The output signal from the phase rotators m_414b and m_419b are transmitted to the signal combiner 420b, where they are linearly combined (added, in this example) to form an output signal. This output signal is transmitted to the filter 422b, which produces a second filtered output signal. The output signal from the phase rotators m_414c and m_419c are transmitted to the signal combiner 420c, where they are linearly combined (added, in this example) to form an output signal. This output signal is transmitted to the filter 422c, which produces a third filtered output signal. Each of the filters 422a-c is a digital filter. In this Example 1, the filter 422a is defined by the impulse response (-l)ⁿh(3n), the filter 422b by the impulse response (-l)ⁿh(3n + 1), and the filter 422c by the impulse response (-l)ⁿh(3n + 2), where h(n) is the impulse response of the anti-aliasing filter, or lowpass filter, used to eliminate images of the modulated input 410 and 411 caused by upsampling. Finally, the commutator 430 sequentially selects the first, second, and third filtered output signals. Preferably, the multiplexer 430 transmits the sequentially selected first, second, and third filtered output signals to a transmitter for transmission across a wireless medium. It will be appreciated that each data signal selected by the commutator 430 has both a real component and an imaginary component, sometimes referred to as an in-phase component and a quadrature component, respectively. While Figure 6 depicts the commutator 430 selecting from and transmitting a single output signal from the filter 422a, the commutator 430 will select and transmit a data signal having both an in-phase component and a quadrature component. In one embodiment, that portion of the channel extender 125 comprising the 802.1 lg modulators 815-1 through 815-N, the upsamplers 818-1 through 818-N, filters 820-1 through 820-N, the frequency shifters 830-1 through 830-N, and the signal combiner 840 is replaced by a digital component that performs an inverse discrete-fourier transform (IDFT). Usually, the IDFT is implemented with an inverse fast-fourier transform (IFFT), which limits its length to 2^k for an integer k. As will be described in more detail below, a signal combiner must perform the inverse function of a corresponding channel restorer. Thus, if that portion of the channel extender 125 comprising the 802.1 lg modulators 815-1 through 815-N the upsamplers 818-1 through 818-N, the filters 820-1 through 820-N, the frequency shifters 830-1 through 830-N, and the signal combiner 840 are implemented as digital components performing an IDFT, then a corresponding channel restorer must use digital components performing a DFT to recover the transmitted data signal. On the other hand, if that portion of the channel extender 125 comprising the 802.1 lg modulators 815-1 through 815-N, the upsamplers 818-1 through 818-N, the filters 820-1 through 820-N, the frequency shifters 830-1 through 830-N, and the signal combiner 840 are implemented as digital components performing a DFT, then a corresponding channel restorer must be implemented using digital components that perform an IDFT. In a preferred embodiment containing N channels, the DFT must be at least N*64 points. Typically, the DFT will be implemented using an FFT. Under the IEEE 802.1 lg standard, data carriers are numbered from -26 to +26, each carrier number being referred to as a bin. In the present invention, the bins are shifted from the 802.1 lg standard. In the present invention, for the kth channel (for k having values from 0 to N-l), the bins normally defined from -26 to +26 are mapped into bins numbered -26 + (k - (N-l)/2))*64 to +26 + (k - (N-l)/2))*64, respectively. Preferably, the channel extender will use an IFFT and the channel restorer (discussed below) will use an FFT, both with the appropriate bin mapping to combine and separate the channels, respectively. Alternatively, the channel extender uses an FFT, and the channel restorer an IFFT. This embodiment advantageously minimizes inter- symbol interference because a filter is not required. To improve spectral containment, the symbol windowing function (rather than a filter) is adjusted. Alternatively, filtering and windowing can both be performed in accordance with the present invention. Figure 7 illustrates a channel combiner 750 that uses an FFT implementation. The channel combiner 750 comprises a data allocator 755 that receives digital data on the connection 740 and allocates it among the N channels 760-1 through 760-N. Each of the channels 760-1 through 760-N is coupled to an 802.1 lg coder/mapper 770-1 through 770-N, respectively. It will be appreciated that each coder/mapper 770-1 through 770-N comprises a convolution coder (e.g., a puncture convolutional coder). The convolution coder possibly punctures code (e.g., to 2/3) and maps the remaining bits to an appropriate bin. It will be appreciated that each 802.1 lg coder/mapper can also include a forward error correction (FEC) component. Each of the 802.1 lg coder/mappers 770-1 through 770-N is coupled to one of the N bin mappers 775-1 through 775-N, respectively. Each of the bin mappers 775-1 through 775- N maps one of the N channels to a bin, as defined above. For example, the bin mapper 775-1 maps the channel 1 to the bin -26 + (0- (N-l)/2)*64. The bin mapper 775-2 maps the channel 2 to the bin -26 + (1- (N-l)/2)*64. This continues up through the bin mapper 775-N, which maps the Nth channel to the bin -26 + (N-l- (N-l)/2)*64. Each bin mapper 775-1 through 775-N is coupled to the FFT processor 780, which is coupled to a periodic extension component 785. Preferably, the periodic extension component 785 inserts an 800ns guard band between symbols. It will be appreciated that in accordance with the present invention, the periodic extension component 785 can insert guard bands having other durations between symbols to reduce inter-symbol interference. The periodic extension component 785 has an output coupled to a windowing component 790, which in turn is coupled to a filter 795 used to produce a filtered output corresponding to a composite data signal on the connection 796, as described above. It will be appreciated by those skilled in the art, that a corresponding channel restorer will have components that perform complementary functions used to recover a digital signal generated by the channel combiner 750 Referring again to Figures 1 and 2, in accordance with the present invention, the data allocator (121, Figure 2) allocates a data signal (or data frame) among a plurality of data segments traveling along a plurality of logical channels. Thus, for example, a data signal (or channel, e.g., I ll, Figure 1) can be divided into a first portion that is relocated to travel on a 24 Mbps channel (e.g., 112, Figure 2) and a second portion that is relocated to travel on a 54 Mbps channel (e.g., 113, Figure 2). This data allocation is used to increase the total bandwidth of the communication between a station and an access point. In one embodiment, the data allocator 121 can allocate data according to the maximum reliable channel transmission rates. The data allocator 121 can divide data frames transmitted by a station 110 into N equal-time transmissions. Thus, for example, a data frame may contain 1000 bytes. This and later examples will assume that the logical channel 112 transmits data at 24 Mbps and the logical channel 113 transmits data at 54 Mbps. The data allocator 121 will divide the data frame into two blocks, one 307 bytes long and the other 693 bytes long. The data allocator 121 will route the 307-byte block to the logical channel 112 and the 693-byte block to the relocated channel 113. In general, if each channel has a data rate Ri and the total number of bytes is T, then the number of bytes in a channel n will be (Υ*(RJ( ∑ RJ), where ∑Rj means the sum of all the rates. The data allocator 121 can use the length of a data packet, found in its transmission header, to allocate the data blocks accordingly. The data allocator 121 will generally allocate extra bytes in a manner that minimizes or at least does not increase the total transmission time. Figure 8 generally illustrates data allocation according to this embodiment. As shown in Figure 8, a data frame 710 comprises the data segments 710A through 7 ION. The data segment 710A comprises the bits 0 through M*(R₁/^R_i) -1 of the data frame 710, where M is the number of bits in a frame; the data segment 710B comprises the bits M*(R,/∑R;) through M*((Rj + ₂)/XRj) - 1 of the data frame 710; up through the data segment 7 ION, which comprises the bits M*((R, + . . . + R_N)/∑R;) -1 through M-l of the data frame 710. The data segment 710A is transmitted along the logical channel 1; the data segment 710b is transmitted along the logical channel 2; up through the data segment 7 ION, which is transmitted along the logical channel N. It will be appreciated that the mathematical representation of the number of bits in each data segment M*(^R_J/^R_i, for j=l to k and i=l to N) is not necessarily an integer, but can be rounded blindly or taken to put the remainders into the channels with the highest rates. If the rates are sorted so that R^R₂ . . _N, then the equation could be floor (M*∑R_j/∑Ri) for allocation of the remainder of the bits into the fastest channel. In another embodiment, the data allocator 121 can split the data frame into symbols and route data blocks equal to one symbol to each logical channel. Thus, for example, when 1000 total bytes are transmitted over the bus 111, then the data allocator 121 will allocate 96 bits (corresponding to one symbol at 24 Mbps according to the IEEE 802.1 lg protocol, referred to as N_DBPS) to the logical channel 112, and 216 (corresponding to one symbol at 54 Mbps according to the IEEE 802.1 lg protocol, referred to as N_DBPS) bits to the logical channel 113. This would be repeated until all 1000 bytes have been allocated among the relocated channels 112 and 113. Figure 9 generally illustrates data allocation according to this embodiment. As shown in Figure 9, a data frame 810 comprises the data segments 810A1 through 810AN, 810B1 through 810BN, etc, each corresponding to one symbol (N_DBPS) according to the IEEE 802.1 lg protocol. Here, symbols are allocated to the logical channels in a round robin fashion. For example, the data segment 810A1 is supplied to the logical channel 1; the data segment 810A2 is supplied to the logical channel 2; up through the data segment 810AN, which is supplied to the logical channel N. Next, the data segment 810B1 is supplied to the logical channel 1, etc. This is repeated until all of the data segments are allocated to the logical channels. In a third embodiment, the data allocator 121 can split the bit streams from the bus 111 on-the-fly into each relocated channel 112 and 113. In this embodiment, the fastest logical channel (in this case, the logical channel 113) is allocated the bits early in the allocation process to minimize added transmission time. Thus, for example, when 1000 total bytes are transmitted over the baseband bus 111, the data allocator 121 will allocate three bits to the logical channel 113 followed by one bit to the logical channel 112. In the next three iterations, the data allocator 121 will allocate two bits to the logical channel 113, followed by one bit to the logical channel 112. Thus, a total of nine bits would be allocated to the logical channel 113 and four bits to the logical channel 112. This process would be repeated until all of the bits have been assigned to each logical channel. This method divides the bits evenly across the logical channels by dividing the rates of each logical channel by the minimum rate for all of the logical channels: (^/(min _{ Rj)). If the result includes a remainder, the extra bit is assigned immediately so the uneven timing will be absorbed by the fastest logical channel(s), thereby increasing throughput by decreasing transmission time. Figure 10 generally illustrates data allocation according to this embodiment. As shown in Figure 10, a data frame 910 comprises the data segments 910A1 through 910AN, 910B1 through 910BN, etc, each corresponding to a sequence of bits. Here, each data segment contains a sequence of bits that are allocated to the logical channels in a round robin fashion. For example, the data segment 910A1 contains the first sequence of bits in the data frame 910 that is (RJmin Ri) bits long; the data segment 910A1 is supplied to the logical channel 1. The data segment 910B1 contains the next sequence of bits (R₂/min Ri) bits long; the data segment 910B1 is supplied to the logical channel 2. This is continued up through the data segment 910N1, which contains the sequence of bits (R_N/min Ri) and is supplied to the logical channel N. The allocation method continues so that the next sequence of bits, (R,/min Ri) bits long, labeled by the data segment 910B1 is supplied to the logical channel 1, etc. It will be appreciated that, in general, R_k/min R; is not an integer. Preferably, if R_k/min R, is not an integer, the extra bit is added early. That is, the total number of bits allocated should be related to the ceiling function of the number of times the logical channel is assigned data relative to the minimum rate of all the logical channels. It will be appreciated, however, that other methods for allocating the remaining bits can also be used. Figure 11 illustrates a high-level overview of a channel restorer 300 in accordance with one embodiment of the present invention. The channel restorer 300 comprises a data deallocator 340 and a channel disassembler 310. The channel disassembler 310 comprises a plurality of demodulators 315-1 through 315-N, a plurality of filters 325-1 through 325-N, and a plurality of frequency shifters 330-1 through 330-N. As illustrated in Figure 11, the connection 116 is coupled to an input of the channel disassembler 310, and hence to an input of each of the frequency shifters 330-1 through 330- N. Each of the frequency shifters 330-1 through 330-N has an output coupled to one of the filters 325-1 through 325-N, respectively. Thus, for example, the output of the frequency shifter 330-1 is coupled to an input of the filter 325-1; the output of the frequency shifter 330-2 is coupled to an input of the filter 325-2; up to the output of the frequency shifter 330- N, which is coupled to an input of the filter 325-N. Each of the filters 325-N has an output coupled to an input of a corresponding demodulator 315-1 through 315-N, respectively. Thus, for example, an output of the filter 325-1 is coupled to an input of the demodulator 315-1; an output the filter 325-2 is coupled to an input of the demodulator 315-2; up to the filter 325-N, which has an output coupled to an input of the demodulator 315-N. Each of the demodulators 315-1 through 315-N has an output coupled to an input of the data deallocator 340. The data deallocator 340 has an output 117, which, preferably, is coupled to a data distribution system, such as the data distribution system 165 illustrated in Figure 1. The operation of the channel restorer 300 is best understood by appreciating that it performs a function complementary to that of a channel extender. In operation, the channel restorer 300 receives a composite data signal on the connection 116. The connection 116 can be connected to a receiver, such as the receiver 151 illustrated in Figure 1. The composite signal is transmitted to the input of the frequency shifter 330-1, which multiplies the composite signal with the sequence {e ²ⁿⁿⁿ}, where n is the time index, to generate a frequency-shifted output signal. The frequency-shifted output signal is transmitted to the filter 325-1 to produce a Signal 1. The Signal 1 is then transmitted to the input of the demodulator 315-1, which generates a data signal containing a data segment Data 1. The data signal containing the data segment Data 1 is then transmitted to an input of the data deallocator 340. The composite signal transmitted to each of the mixers 330-2 through 330-N travels similar, parallel paths. Thus, for example, for any integer K between 1 and N inclusive, the composite signal is transmitted to the frequency shifter 330-K, which multiplies the composite signal with the sequence {e^i2πfKn}, where n is the time index, to generate a frequency-shifted output signal. The frequency-shifted output signal is transmitted to the filter 325-K to produce a Signal K. The Signal K is then transmitted to the input of the demodulator 315-K, which produces a data signal containing a data segment Data K. The data signal containing the data segment Data K is then transmitted to an input of the data deallocator 340. The data deallocator 340 receives the data signals containing the data segments Data 1 through Data N, and combines them to form a data signal containing the data Data. The data signal containing Data is then transmitted on the channel 117. Preferably, each of the frequency shifters 330-1 through 330-N, each of the filters 325-1 through 325-N, and each of the demodulators 315-1 through 315-N is a digital component. It will be appreciated, however, that each of the frequency shifters 330-1 through 330-N, each of the filters 325-1 through 325-N, and each of the demodulators 315-1 through 315-N can be either an analog or a digital component. It will be appreciated that the frequency shifter will change for an analog mode: Instead of a { ^2πkn}, a time-domain function {ej^2πkt} will be multiplied in the frequency shifter, where t is time. Figure 12 is a high-level overview of a channel restorer 500 in accordance with one embodiment of the present invention. As described below, each component illustrated in Figure 12 is a digital component. The channel restorer 500 comprises a data deallocator 340 and a channel disassembler 510. The channel disassembler 510 comprises a plurality of 802.1 lg demodulators 515-1 through 515-N, a plurality of downsamplers 520-1 through 520- N, a plurality of filters 525-1 through 525-N, and a plurality of frequency shifters 530-1 through 530-N. As illustrated in Figure 12, the connection 116 is coupled to an input of the data disassembler 510, and hence to an input of each of the frequency shifters 530-1 through 530- N. Each of the frequency shifters 530-1 through 530-N has an output coupled to a corresponding filter 525-1 through 525-N, respectively. Each filter 525-1 through 525-N is coupled to an input of a corresponding downsampler 520-1 through 520-N, respectively. Each of the downsamplers 520-1 through 520-N has an output coupled to an input of a corresponding 802. llg demodulator 515-1 through 515-N, respectively. Each of the 802. llg demodulators 515-1 through 515-N has an output coupled to one input of the data deallocator 340. The data deallocator 340 has an output 117, which can be coupled, for example, to a host or to a distribution system containing a host. In operation, the channel restorer 500 receives a composite data signal on the connection 116. The connection 116 can be connected to a receiver. The composite signal is transmitted to the input of the frequency shifter 530-1, which multiplies the composite signal with the sequence { ^2πnn}, where n is the time index, to generate a frequency-shifted output signal. The frequency-shifted output signal is transmitted to the filter 525-1, which generates a filtered output signal. The filtered output signal is transmitted to an input of the downsampler 520-1, which generates a downsampled output signal, denoted in Figure 12 as Signal 1. If the channel restorer 500 is configured to receive a composite signal from the channel assembler 800 of Figure 5, then the Signal 1 of Figure 12 may correspond to the Signal 1 of Figure 5. The Signal 1 is next transmitted to the input of the 802. llg demodulator 515-1, which produces a demodulated output signal containing a data segment Data 1. If the channel restorer 500 is configured to receive a composite signal from the channel assembler 800 of Figure 5, then the data segment Data 1 may correspond to the data segment Data 1 of Figure 5. The data signal containing the data segment Data 1 is next transmitted to the data deallocator 340. The composite signal transmitted to each of the frequency shifters 530-2 through 530- N travels similar, parallel paths. Thus, for example, for any integer K between 1 and N inclusive, the composite signal is transmitted to the frequency shifter 530-K, which multiplies the composite signal with the sequence {e^j2πfKn}, where n is the time index, to generate a frequency-shifted output signal. The frequency-shifted output signal is transmitted to the filter 525-K, which generates a filtered output signal. The filtered output signal is transmitted to an input of the downsampler 520-K, which generates a downsampled output signal, denoted in Figure 12 as Signal K. If the channel restorer 500 is configured to receive a composite signal from the channel assembler 800 of Figure 5, then the Signal K of Figure 12 may correspond to the Signal K of Figure 5. The Signal K is next transmitted to the input of the 802.1 lg demodulator 515-K, which produces a demodulated output signal containing a data segment Data K. If the channel restorer 500 is configured to receive a composite signal from the channel assembler 800 of Figure 5, then the data segment Data K may correspond to the Data K of Figure 5. The data signal containing the data segment Data K is next transmitted to the data deallocator 340. The data deallocator 340 generates a data signal containing data Data on channel 117, which can then be transmitted to a host. If the channel restorer 500 is configured to receive a composite signal from the channel assembler 800 of Figure 5, then the data Data may correspond to the Data of Figure 5. In the embodiment depicted in Figure 12, each of the frequency shifters 530-1 through 530-N, each of the filters 525-1 through 525-N, each of the downsamplers 520-1 through 520-N, and each of the 802.1 lg demodulators 515-1 through 515-N is a digital component that processes digital signals. Figure 13 illustrates a channel separator 950 in accordance with one embodiment of the present invention. The channel separator 950 receives a composite signal, downsamples the signal with a commutator 603, filters the downsampled signal, and frequency shifts the separated channels, and provides demodulator inputs 611 and 612. The channel separator 950 comprises a commutator 603, a plurality of filters 620a-c, two phase rotator banks 610 and 615, two signal adders 625a and 625b, and two last-stage frequency shifters 660a and 660b. In operation, a composite signal is transmitted along a path to the connection 116. The commutator 603 sequentially routes portions of the composite signal to one of the three filters 620a-c. Preferably, the commutator 603 is a time-division switch, sequentially routing the composite signal on the connection 116 to the input of one of the filters 620a-c at predetermined time intervals. It will be appreciated that the commutator 603 performs a downsampling operation by taking every third sample and putting it into the filter 620a. Similarly, the commutator takes every third sample delayed by one and puts it into the filter 620b. The commutator takes every third sample delayed by two and puts it into the filter 620c. Thus, the connection 116 has three times the rate as the signals through any of the filters 620a-c. Figure 13 illustrates the commutator 603 routing the composite signal to the filter 620c. It will be appreciated that Figure 13 illustrates a multi-rate separation of two channels of the composite signal on the connection 116. It will be appreciated that the demodulator inputs 611 and 612 are running at one third the rate of the composite signal on the connection 116. It will also be appreciated that the three filters 620a-c are parts of a filter used to select each individual channel. In this illustration, the phase rotator banks 610 and 615, along with the signal adders 625a and 625b, make it possible for the same filters to be used for both channels. Finally, two channels are frequency shifted with the frequency shifters 660a and 660b to create the demodulator inputs 611 and 612. In a preferred embodiment, each of the filters 620a-c is matched to one of the filters (e.g., 422a-c, Figure 6) in a channel extender. For example, if the channel separator 950 were configured to receive a composite data signal from the channel combiner 850 of Figure 6, then the filter 620a can have the same response function as that of the filter 422a; the filter 620b can have the same response function as that of the filter 422b; and the filter 620c can have the same response function as that of the filter 422c. Moreover, the timing of the commutator 603 would match that of the commutator 430 of the channel combiner 850 illustrated in Figure 6 (it is also noted that the sequencing is reversed, i.e., in the channel combiner 850, the sequence is 422a, 422b, 422c, 422a, etc, but in the channel separator, the sequence is 620c, 620b, 620a, 620c, etc.). The output of each filter 620a-c is coupled to each of the two phase-rotator banks 610 and 615. Each phase-rotator bank generates a set of phase-rotated signals that corresponds to the set of frequency-shifted signals generated by a channel combiner. For example, if the channel separator 950 were configured to receive a composite data signal from the channel combiner 850 of Figure 6, then the set of phase-rotated signals generated by the phase-rotator bank 610 will correspond to the set of frequency-shifted signals input to the phase-rotator banks 414 and 419 illustrated in Figure 6. As described above, each phase-rotator bank contains a plurality of phase-rotators, which together generate a set of phase-rotated outputs. The phase-rotator bank 610 is comprised of the phase rotators 610a-c, and the phase-rotator bank 615 is comprised of the phase rotators 615a-c. Each phase rotator bank 610 and 615 receives one input from each of the filters 620a-c and generates a set of phase-rotated outputs that are transmitted to a corresponding signal summer 625a-b. Thus, for example, the phase rotator 610a receives an output from the filter 620a and rotates its phase by multiplying it by the constant m_610a to produce a phase-rotated output signal that is routed to an input of the signal summer 625a. The phase rotator 610b receives an output from the filter 620b and rotates its phase by multiplying it by the constant m_610b to produce a phase-rotated output signal that is routed to an input of the signal summer 625a. The phase rotator 610c receives an output from the filter 620c and rotates its phase by multiplying it by the constant m_610c to produce a phase-rotated output signal that is routed to an input of the signal summer 625 a. Similarly, the phase rotator bank 615 generates a set of phase-rotated signals that are fed to the signal summer 625b. The phase rotator 615a receives an output from the filter 620a and rotates its phase by multiplying it by the constant m_615a to produce a phase-rotated output signal that is routed to an input of the signal summer 625b. The phase rotator 615b receives an output from the filter 620b and rotates its phase by multiplying it by the constant ^m ₆i_5b ^t0 produce a phase-rotated output signal that is routed to an input of the signal summer 625b. The phase rotator 615c receives an output from the filter 620c and rotates its phase by multiplying it by the constant m_615c to produce a phase-rotated output signal that is routed to an input of the signal summer 625b. Each of the signal summers 625a-b receives a set of phase-rotated signals and generates a summed output signal. For example, the signal summer 625a receives the set of phase-rotated signals generated by the phase-rotator bank 610, that is the signals generated by the phase rotators 610a-c, and combines them to produce an output signal, which it routes to the last-stage frequency shifter 660a. The last-stage frequency shifter 660a multiplies the output from the signal summer 625a with the sequence m_660a to shift the center frequency of the demodulator input 611. Similarly, the signal summer 625b receives the set of signals generated by the phase- rotator bank 615, that is the signals generated by the phase rotators 615a-c, and combines them to produce an output signal, which it routes to the last-stage frequency shifter 660b. The last-stage frequency shifter 660b multiplies the output of the signal summer 625b with the sequence m_660b to shift the center frequency for the demodulator input 612. The demodulator inputs 611 and 612 are then fed to the demodulator (e.g., an 802.1 lg demodulator). The demodulator outputs are then fed to a data deallocator (e.g., 152, Figure 3), which combines relocated signals to form a baseband data signal that can be routed to a distribution system. As described above, the data deallocator 152 performs a complementary function to that of the data allocator and will not be described in detail here. As an Example 2, the channel separator 950 can be configured to communicate with the channel combiner 850 of Figure 6. In this Example 2, the channel combiner 850 has the same parameters as those discussed in Example 1, above. In this Example 2, the filter 620a is the same as the filter 422a of Figure 6; the filter 620b is the same as the filter 422b of Figure 6; and the filter 620c is the same as the filter 422c of Figure 6. In addition, the output of the phase rotator bank 610 in conjunction with the signal summer 625 a is configured to extract the output of the frequency shifter 412 of Figure 6. And the output of the phase rotator bank 615 in conjunction with the signal summer 625b is configured to extract the output of the frequency shifter 417 of Figure 6. Accordingly, in this Example 2, the channel separator 950 is configured so that the multiplier constants have the values, m_610a = e^{("0jπ 3)}, or 1; m_610b = e^("ljπ/3), or approximately 0.5 - jO.8660; m_610c = e^{("2jπ 3)}, or approximately -0.5 - jO.8660; m_615a = e^{(+0jπ 3)}, or 1; m_615b = e^{(+ljπ 3)}, or approximately 0.5 + jO.8660; and m_615c = e^{(+2jπ 3)}, or approximately -0.5 + jO.8660. The filter 620a has the impulse response (-l)ⁿh(3n); the filter 620b has the impulse response (- l)ⁿh(3n+l); and the filter 620c has the impulse response (-l)ⁿh(3n+2), where h(n) is the impulse response of the anti-aliasing filter, or lowpass filter, used to eliminate aliased images caused by downsampling the composite signal on the connection 116. Similarly, the demodulator (e.g., 315-1 through 315-N, Figure 7) is configured to perform the inverse operation of the modulator (e.g., 715-a through 715-N, Figure 4), providing the inputs to the data deallocator 152. Similarly, the data deallocator (e.g., 152, Figure 3) is configured to perform the inverse operation of the data allocator (e.g., 121, Figure 2), transferring data from the relocated channels (118 and 119, Figure 3) to the channel 117. Figure 14 illustrates a channel separator 548 in accordance with one embodiment of the present invention. The channel separator 548 can be used, for example, to receive a composite signal transmitted by the channel combiner 750 of Figure 7. The channel separator 548 comprises a connection 546 coupled to a receiver (not shown) on which a composite signal is received. The connection 546 is coupled to a signal timing and extraction component 550. The signal timing and extraction component 550 is coupled to an FFT processor 555 having N vector outputs. Each of the N vector outputs of the FFT processor 555 is coupled to a respective inverse bin mapper 560-1 though 560-N. It will be appreciated that if the channel separator 548 is configured to receive a composite signal transmitted by the channel combiner 750 of Figure 7, then each of the inverse bin mappers 560-1 through 560-N will perform a function inverse to that of the corresponding bin mappers 775-1 through 775-N, respectively, of Figure 7. Each of the inverse bin mappers 560-1 through 560-N is coupled to a corresponding equalizer 564-1 through 564-N, respectively. Each of the equalizers 561-1 through 561-4 is coupled to a corresponding 802.1 lg decoder/demapper, 565-1 through 565-N, respectively. It will be appreciated that in an alternative embodiment, each of the equalizers 564-1 through 564-N is coupled between the FFT processor 555 and a corresponding inverse bin mapper, 560-1 through 560-N, respectively. It will be appreciated that if the channel separator 548 is configured to receive a composite signal transmitted by the channel combiner 750 of Figure 7, then each of the 802.1 lg demappers 565-1 through 565-N will perform a function inverse to that of the corresponding 802.1 lg mappers 770-1 through 770-N, respectively, of Figure 7. Each of the 802.1 lg decoder/demappers 565-1 through 565-N is coupled to a data deallocator 571. It will be appreciated that the channel separator 548 can contain other components known to those skilled in the art, such as filters, an adaptive frequency controller (AFC) coupled to the connection 546, and an equalizer coupled to the 802.1 lg demappers 565-1 through 565-N. A channel extender can be configured to communicate with conventional stations and access points (legacy devices), configured to process data signals not in accordance with the present invention. As described in more detail below, a legacy device with which the channel extender communicates will alert the channel extender that it is not equipped to communicate according to the present invention. The channel extender then will communicate not with a composite data signal but with a data signal that is not produced from relocated channels in accordance with the present invention. A channel extender can discover the existence of legacy devices in its transmission area in two ways. First, the channel extender can broadcast a probe request frame to elicit a probe response frame containing information about local stations or access points; second, it can listen for beacon frames that contain similar information. The channel extender can then parse probe response frames and beacon frames to determine whether access points and stations with which it communicates are configured to exchange data in accordance with embodiments of the present invention. Further, when a channel extender communicates with a legacy device, a data allocator can set all but one relocated channel data rate to 0 bits per second, thus forcing data to be transmitted along one channel. Moreover, when receiving data from a legacy device, the channel restorer can decode the data so that all but one relocated channel receives data at 0 bits per second, thus ensuring communication along a single channel. It will be readily apparent to one skilled in the art that other various modifications may be made to the preferred embodiments without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

ClaimsI claim:

1. A channel extender comprising: a. a data allocator for allocating data contained within a data signal among a plurality of data segments; and b. a channel assembler coupled to the data allocator, the channel assembler configured to combine the data segments to form a composite data signal.

2. The channel extender of claim 1, wherein the channel assembler comprises: a. a plurality of modulators, each modulator configured to receive a data segment from the data allocator along a corresponding logical channel; b. a plurality of filters, each filter coupled to a corresponding one of the plurality of modulators; c. a plurality of frequency shifters, each frequency shifter coupled to a corresponding one of the plurality of filters; and d. a signal combiner coupled to each of the plurality of frequency shifters.

3. The channel extender of claim 2, wherein each of the plurality of modulators is configured to modulate a corresponding one of the data segments using orthogonal frequency division multiplexing.

4. The channel extender of claim 3, wherein the orthogonal frequency division multiplexing is according to an IEEE 802.11 standard.

5. The channel extender of claim 4, wherein the IEEE 802.11 standard is the IEEE 802. l lg standard.

6. The channel extender of claim 4, wherein the IEEE 802.11 standard is the IEEE 802.11a standard.

7. The channel extender of claim 2, further comprising a plurality of upsamplers, each upsampler coupled to a corresponding one of the filters and a corresponding one of the frequency shifters.

8. The channel extender of claim 7, wherein a rate of each upsampler is proportional to a total number of the logical channels.

9. The channel extender of claim 1, further comprising a wireless transmitter coupled to the channel assembler.

10. The channel extender of claim 1, wherein the channel assembler comprises: a. a plurality of signal mappers, each signal mapper configured to receive a corresponding data segment from the data allocator along a corresponding logical channel; b. a plurality of frequency bin mappers, each frequency bin mapper coupled to a corresponding signal mapper; and c. a discrete fourier transform processor coupled to each of the plurality of frequency bin mappers.

11. The channel extender of claim 10, wherein each of the signal mappers maps a data segment according to an IEEE 802.11 standard.

12. The channel extender of claim 11, wherein the IEEE 802.11 standard is the IEEE 802. l lg standard.

13. The channel extender of claim 11 , wherein the IEEE 802.11 standard is the IEEE 802.11a standard

14. The channel extender of claim 11 , wherein a frequency bin mapper maps an output of a corresponding signal mapper according to the equation -26 + (k-1 -(N-l)/2))*64, wherein k is an integer corresponding to the frequency bin mapper and N equals a total number of the logical channels.

15. The channel extender of claim 11 , further comprising an extension component coupled to an output of the discrete fourier transform processor, the extension component configured to introduce guard bands between outputs of the discrete fourier transform processor.

16. The channel extender of claim 15, further comprising a windowing component coupled to the extension component.

17. The channel extender of claim 16, further comprising a filter coupled to the windowing component.

18. The channel extender of claim 1, wherein the channel assembler comprises: a. a plurality of first-stage frequency shifters, each first-stage frequency shifter coupled to the data allocator on a corresponding logical channel; b. a plurality of phase-rotator banks, each phase-rotator bank coupled to a corresponding logical channel and configured for receiving a data segment on the corresponding logical channel and modulating the data segment by a plurality of phases to produce a set of phase-rotated data signals; c. a plurality of signal combiners, each signal combiner configured for receiving a phase-rotated data signal from each set of phase-rotated data signals and combining the received phase-rotated data signals; d. a plurality of filters, each filter coupled to an output of a corresponding signal combiner; and e. a commutator having an output line, the commutator configured to sequentially couple to each of the filters, thereby producing the composite data signal on the output line.

19. The channel extender of claim 18, wherein each phase-rotator bank comprises a set of phase-rotators, each phase-rotator configured for receiving a data segment and modulating the data segment by a modulation signal selected from a set of modulation signals to produce a modulated data signal.

20. The channel extender of claim 18, wherein a first phase-rotator bank modulates a first data segment using a first set of modulation signals to produce a first set of modulated data signals, and a second phase-rotator bank modulates a second data segment using a second set of modulation signals that are conjugates of the first set of modulation signals to produce a second set of modulated data signals.

21. The channel extender of claim 20, wherein each signal in a set of modulation signals has a phase that is a multiple of a single phase.

22. The channel extender of claim 18, wherein each of the plurality of filters has an impulse response shifted by one time unit from an impulse response of one other of the plurality of filters .

23. The channel extender of claim 1, wherein the data allocator is configured to allocate a portion of the data contained within the data signal to a logical channel in a proportion related to a bit rate of the logical channel to a combined bit rate of the plurality of logical channels.

24. The channel extender of claim 1, wherein the data allocator is configured to allocate a portion of the data contained within the data signal to a data segment in a round-robin manner.

25. A channel extender comprising: a. means for allocating data contained within a data signal among a plurality of data segments; and b. means for combining the plurality of data segments to form a composite data signal.

26. A method of forming a composite data signal, comprising the steps of: a. allocating data contained within a data signal among a plurality of data segments along a plurality of corresponding logical channels; and b. combining the plurality of data segments to form the composite data signal.

27. The method of claim 26, wherein the step of combining the plurality of data segments comprises the steps of: a. modulating each data segment to form a set of modulated data signals; b. filtering each modulated data signal to form a set of filtered data signals; c. frequency-shifting each filtered data signal to form a set of frequency-shifted data signals; and d. combining each frequency-shifted data signal to generate the composite data signal.

28. The method of claim 27, further comprising the step of upsampling each filtered data signal before frequency-shifting the data signal.

29. The method of claim 27, wherein each data segment is modulated using orthogonal frequency division multiplexing.

30. The method of claim 29, wherein the orthogonal frequency division multiplexing is performed according to an IEEE 802.11 standard.

31. The method of claim 30, wherein the IEEE 802.11 standard is the IEEE 802.1 lg standard.

32. The method of claim 30, wherein the IEEE 802.11 standard is the IEEE 802.1 lg standard.

33. The method of claim 28, wherein a rate of upsampling is proportional to a total number of the plurality of data segments.

34. The method of claim 26, further comprising the step of wirelessly transmitting the composite data signal.

35. The method of claim 26, wherein the step of combining the plurality of data segments comprises the steps of: a. frequency mapping each data segment to a corresponding mapped data segment; b. bin mapping each mapped data segment to produce a plurality of bin mapped outputs; and c. performing a discrete fourier transform on the plurality of bin-mapped outputs to form a DFT output signal.

36. The method of claim 35, wherein frequency mapping each data segment is performed according to an IEEE 802.11 standard.

37. The method of claim 36, wherein the IEEE 802.11 standard is the IEEE 802. llg standard.

38. The method ofclaim 36, wherein the IEEE 802.11 standard is the IEEE 802.1 la standard.

39. The method of claim 36, wherein a data segment is bin-mapped according to the equation -26 + (k-1 - (N-l)/2))*64, wherein N equals a total number of the plurality of data segments and k is an integer between 1 and N inclusive.

40. The method of claim 39, further comprising the step of adding guard bands to the DFT output signal to form a guarded signal.

41. The method of claim 40, further comprising the step of performing windowing on the guarded signal to form a windowed signal.

42. The method of claim 41 , further comprising the step of filtering the windowed signal to produce a filtered signal.

43. The method of claim 26, wherein the step of combining comprises a. phase rotating each data segment by a corresponding set of phases to produce a plurality of sets of phase-rotated data signals; b. combining a phase-rotated data signal from each set of phase-rotated data signals to generate a set of combined data signals; c. filtering each of the combined data signals to generate a set of filtered data signals; and d. sequentially selecting a signal from the set of filtered data signals to produce the composite data signal.

44. The method of claim 43, wherein a first set of phases are conjugates of a second set of phases.

45. The method ofclaim 43, wherein a first set of phases contains phases that are multiples of a first predetermined phase and a second set of phases contains phases that are multiples of a second predetermined phase.

46. The method of claim 26, wherein the step of allocating data comprises dividing a data frame into a plurality of data packets and selectively allocating the data packets among predetermined ones of the plurality of logical channels.

47. The method of claim 46, wherein a number of data packets allocated to a logical channel is related to a proportion of a bit rate of the logical channel to a combined bit rate of the plurality of logical channels.

48. The method ofclaim 26, wherein the step of allocating data comprises dividing a data frame into a plurality of data blocks and selectively allocating each data block among predetermined ones of the plurality of logical channels.

49. The method ofclaim 48, wherein a proportion of the data blocks allocated to a logical channel is related to a proportion of a bit rate of the logical channel to a combined bit rate of the plurality of logical channels.

50. The method ofclaim 26, wherein the step of allocating data comprises dividing a data frame into a plurality of symbols and selectively allocating each symbol among predetermined ones of the plurality of logical channels.

51. The method of claim 50, wherein a number of symbols allocated to a logical channel is related to a proportion of a bit rate of the logical channel to a combined bit rate of the plurality of logical channels.

52. A channel restorer for restoring a data signal, comprising: a. a channel disassembler for translating data contained in a composite signal into a plurality of data segments; and b. a data deallocator for combining the plurality of data segments to form the data signal.

53. The channel restorer ofclaim 52, wherein the channel disassembler comprises: a. a plurality of frequency shifters, each frequency shifter configured to receive the composite signal; b. a plurality of filters, each filter coupled to a corresponding frequency shifter; and c. a plurality of demodulators each coupled to a corresponding filter, each demodulator further coupled to the data deallocator.

54. The channel restorer ofclaim 53, wherein each demodulator is configured to demodulate a data signal using orthogonal frequency division demultiplexing.

55. The channel restorer ofclaim 54, wherein the orthogonal frequency division demultiplexing is according to an IEEE 802.11 standard.

56. The channel restorer ofclaim 55, wherein the IEEE 802.11 standard is the IEEE 802. l lg standard.

57. The channel restorer of claim 55, wherein the IEEE 802.11 standard is the IEEE 802.11a standard.

58. The channel restorer ofclaim 55, further comprising a plurality of downsamplers, each downsampler coupled to a corresponding one of the filters and a corresponding one of the frequency shifters.

59. The channel restorer ofclaim 53, further comprising a wireless receiver coupled to each of the plurality of frequency shifters.

60. The channel restorer ofclaim 52, wherein the channel disassembler comprises: a. a commutator configured to receive the composite signal; b. a plurality of filters, each filter coupled to the commutator for sequentially receiving a slice of the composite signal and producing a filtered output signal; c. a plurality of phase-rotator banks, each phase-rotator bank coupled with each filter, each phase-rotator bank having a set of outputs; and d. a plurality of signal combiners, each signal combiner coupled to a set of outputs from a corresponding phase-rotator bank, each signal combiner having an output coupled to the data deallocator.

61. The channel restorer of claim 60, wherein each phase-rotator bank comprises a set of phase rotators, each phase rotator coupled to an output of a corresponding filter from the plurality of filters.

62. The channel restorer of claim 61 , wherein each phase-rotator bank uses phases that are multiples of a single phase.

63. The channel restorer of claim 61 , wherein a first phase-rotator bank uses a first set of phases to produce a first set of phase-rotated output signals, and a second phase- rotator bank uses a second set of phases that are conjugates of the first set of phases to produce a second set of phase-rotated output signals.

64. The channel restorer of claim 53, further comprising a receiver coupled with the channel disassembler.

65. The channel restorer ofclaim 64, wherein the receiver receives the composite data signal according to a wireless protocol.

66. The channel restorer of claim 52, wherein the channel disassembler comprises: a. a symbol timing-and-extraction component; b. a fourier transform processor couple to the symbol timing-and-extraction component; c. a plurality of inverse bin mappers each coupled to a respective output of the fourier transform processor; d. a plurality of equalizers, each coupled to a respective one of the inverse bin mappers; and e. a plurality of 802.11 demodulators, each coupled to a respective one of the plurality of the equalizers, wherein each of the plurality of 802.11 demodulators is coupled to the data deallocator.

67. The channel restorer ofclaim 66, wherein each of the 802.11 demodulators is an 802. llg demodulator.

68. The channel restorer of claim 66, wherein each of the 802.11 demodulators is an 802.11 a demodulator.

69. A channel restorer for restoring a digital data signal, comprising: a. means for translating data contained in a composite data signal into a plurality of data segments; and b. means for combining the data segments to form the digital data signal.

70. A method of restoring a digital data signal, comprising: a. translating the composite signal into a plurality of data segments; and b. deallocating the data segments to form the digital data signal.

71. The method of claim 70, wherein the step of translating the composite signal comprises the steps of: a. frequency-shifting the composite signal by a plurality of frequencies to produce a plurality of frequency-shifted signals; b. filtering each frequency-shifted signal to produce a plurality of filtered signals; c. demodulating each filtered signal to produce the plurality of data segments.

72. The method ofclaim 71, further comprising the step of downsampling each filtered signal before the step of demodulating each filtered signal.

73. The method of claim 72, wherein the step of demodulating each frequency-shifted signal is performed using an orthogonal frequency division demultiplexing.

74. The method of claim 73, wherein the orthogonal frequency division multiplexing is performed according to an IEEE 802.11 standard.

75. The method of claim 74, wherein the IEEE 802.11 standard is the IEEE 802.1 lg standard.

76. The method of claim 74, wherein the IEEE 802.11 standard is the IEEE 802.11 a standard.

77. The method of claim 70, further comprising the step of receiving the composite signal according to a wireless protocol.

78. The method ofclaim 70, wherein the step of translating the composite signal comprises the steps of: a. sequentially selecting the composite data signal; b. filtering the sequentially selected composite data signal to produce a set of filtered data signals; c. rotating the phase of each filtered data signal by a plurality of phases to produce a plurality of sets of phase-rotated signals; and d. combining the each set of phase-rotated signals to produce the plurality of data segments.

79. The method of claim 70, wherein the step of translating the composite signal comprises the steps of: a. extracting a plurality of symbols from the composite signal; b. performing a fourier transform on the plurality of symbols to generate a first plurality of data signals; c. performing an inverse bin mapping on the first plurality of data signals to generate a second plurality of data signals; and d. demodulating each of the second plurality of data signals to generate the plurality of data segments.

80. The method of claim 79, wherein the step of demodulating is performed according to an IEEE 802.11 standard.

81. The method of claim 80, wherein the IEEE 802.11 standard is the IEEE 802.11 g standard.

82. The method of claim 80, wherein the IEEE 802.11 standard is the IEEE 802.1 la standard.