Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
  • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
  • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
  • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3181—Functional testing
  • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
  • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
  • G01R31/318555—Control logic
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3181—Functional testing
  • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
  • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
  • G01R31/318572—Input/Output interfaces
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L25/00—Baseband systems
  • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
  • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
  • H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
  • H04L25/03866—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using scrambling

Definitions

• the invention relates generally to sequential logic cell content and specifically to protecting register content in microcontrollers.
• the Prior Art Integrated circuits (ICs) are typically tested for defects arising out of fabrication, and one of the tests used is a scan test.
• One problem with ICs is protecting sensitive register content.
• Registers may be comprised of sequential logic cells and each sequential logic cell is scannable. Scan methods are very efficient but provide an easy means of seeing the logical values of many nets or registers of the IC. Downloading the content of each register using the scan test is possible after a period of operation for the circuit.
• scan tests are not available or they use scan methods combined with built-in scan vector generators and signature analyzer modules so that nothing can be downloaded from the pins of the ICs but defects may be found even if scan chain inputs and outputs do not appear on the top-level pin of the circuit.
• SRAM Static RAM
• Flash the data could be scrambled using crypt algorithms when write access is performed or unscrambled/decrypt when read.
• FIG. 1 is schematic illustrating a prior art simplified microcontroller and scan chain system.
• Microcontroller 100 includes microprocessor 102 coupled to memory 104.
• Address decoder 106 receives and decodes addresses from microprocessor 102 for memory 104 and peripherals 108.
• Address decoder 106 and peripherals 108 receive addresses on address bus 110 while address decoder 106 transmits select information on memory select 112 and peripheral select 114.
• Data is transmitted between microprocessor 102, memory 104, and peripherals 108 on data bus 116.
• a read or a write signal is transmitted between microprocessor 102 and memory 104 and peripherals 108 on read/write signal 117.
• Microcontroller 100 receives clock signal 118 and reset signal 120.
• Input 122 includes, for example, timer triggers and Universal Asynchronous Receiver/Transmitter (UART) input data while output 124 includes, for example, UART transmitter output data.
• Peripherals 108 may be functional logic, for example UART, crypto-processing, digital signal processing (DSP), and digital filtering.
• Scan chain system 126 connects to microcontroller 100. Dashed lines are used in the Figures to illustrate the path of signals related to scan chain system 126, while solid lines represent the path of signals following non-scan chain circuitry.
• Microcontroller 100 receives a scan chain control signal on scan chain control 128 and data on scan chain input 130. Microcontroller 100 transmits data to scan chain system 126 on scan chain output 132. Within microcontroller 100, microprocessor 102 transmits control and data information on scan chain 134 to peripherals 108. Output from scan chain input determines whether peripherals 108 have fabrication defects.
• Figure 2 is a schematic illustrating a more detailed, prior art example of peripheral 108 from Figure 1.
• peripheral 108 includes address sub-decoder 200, configuration register 202, and processing logic 204. Inputs to peripheral 108 include peripheral select 114, read/write signal 117, address bus 110, clock 118 and data bus 116. Scan chain control 128 and scan chain input 130 are transmitted to peripheral 108 along scan chain 134 (not shown in Figure 2, see Figure 1).
• address sub-decoder 200 receives signals from microprocessor 102 and address decoder 106. Address sub-decoder 200 transmits a write enable signal along enable write line 206 to selected multiplexers 208.
• a multiplexer receives a write enable signal it selects from input available through data bus 116 and also from a sequential cell, for example a scan D flip-flop (SDFF) 210.
• Multiplexers 208 transmit received input to their respective SDFFs 210.
• SDFFs 210 transmit to processing logic 204 when they receive clock signals from clock 118.
• a SDFF is a normal DFF with the D input driven by the output of a two-to-one multiplexer (not shown), the multiplexer having inputs SD and D, and a select pin SC (the two-to-one multiplexer is shown as a part of scan DFF 210, with inputs SC, SD and D).
• the SD input is driven by either scan chain input 130 or output from a preceding scan DFF.
• SDFF 210-1 receives data at input SD from scan chain input 130
• SDFF 210- 2 receives data at input SD from the output of SDFF 210-1
• Both SDFF 210 1 and 2 receive scan chain control signals (select signals) at input SC from scan chain control 130.
• Microcontroller 100 may be operated normally, storing values in peripherals 108, and then switched to scan mode and the content of registers in peripherals 108 may be read out and analyzed.
• SDFF 210-2 will transmit its value through scan register output 214 to processing logic 204.
• Processing logic 204 transfers data from scan register output 214 directly to scan chain output 132 without altering the value.
• Control signals transfer data from SDFF 210-1 to SDFF 210-2 and then out to scan chain output 132.
• sensitive data loaded into registers may be read out using scan methodology.
• a system and method of protecting sequential cell, or register content, in systems employing scan chain methodology is needed.
• the system should protect sensitive data loaded into registers while allowing scan chain testing for functionality.
• the system and method described here provides a way to scramble the value of the register without affecting the functionality of the associated logic.
• a combinatorial network of logic cells is placed in front of the register and acts as a scrambling function not specified in any user datasheet because there is no user functionality associated.
• the reverse combinatorial function is placed after the register. Therefore, even if register location is known through the scan register chain and its content after regular operation is downloaded, it is more difficult to ascertain the functional meaning of the value for the current application.
• the invention reduces the ability to download the content of any sequential cell
• Figure 1 is a schematic illustrating a prior art simplified microcontroller.
• Figure 2 is a schematic illustrating a more detailed prior art example of a peripheral from Figure 1.
• Figure 3 is a schematic illustrating the invention implemented with a peripheral from
• Figure 1 is a schematic illustrating one embodiment of the invention using a predetermined scrambling function.
• Figure 5 is a schematic illustrating one embodiment of the invention using a random scrambling function.
• Figure 6 is a schematic illustrating one embodiment of the invention using a random scrambling function.
• Figure 7 is a flow diagram illustrating a method of implementing the invention. DETAILED DESCRIPTION OF THE INVENTION The following description the invention is not intended to limit the scope of the invention to these embodiments, but rather to enable any person skilled in the art to make and use the invention.
• the invention may use combinatorial networks to scramble memory cells making this method more convenient for pre-characterized DFFs, or SDFFs, (for example those DFFs within a register) while making sensitive material within the register more secure.
• the invention allows scrambling and unscrambling of the content of a register in one clock cycle, in the case of a combinatorial network.
• a sequential algorithm in front and after the targeted register may replace the combinatorial networks, though the sequential algorithm may take more than 1 clock cycle to scramble and unscramble the register content.
• Protecting content of a register may be achieved by not inserting the DFFs in the scan chain so that the DFFs will not be tested.
• the invention allows a straightforward test design flow (full scan) without the lack of confidentiality in a scan test.
• the invention may be used on sequential elements acting as a configuration register in order to protect their content from being easily downloaded.
• the scan chain system allows a read-out of the register content while the registers may hold sensitive or confidential data.
• FIG. 3 is a schematic illustrating one embodiment of the invention implemented with a configuration register in a peripheral from Figure 1.
• address sub-decoder 200 receives peripheral select 114, read/write signal 117, and address bus 110.
• Address sub- decoder is connected to configuration register 202 by enable write line 206.
• Configuration register 202 is connected to processing logic by descrambling unit 310.
• Scrambling unit 300 is coupled to data bus 116 and configuration register 202.
• Scrambling unit 300 is configured to receive data, or scrambling unit input, from data bus 116 and to scramble the input in either a predetermined, random, or pseudo-random method.
• the scrambled data is transmitted to configuration register 202. If normal operations are halted and the register content read out by scan chain system 126, only scrambled data will be transmitted through scan register output 214 and scan chain output 132, protecting register content.
• Descrambling unit 310 is coupled to configuration register 202 and is configured to receive the scrambled data from configuration register 202. Descrambling unit 310 is configured to descramble the scrambled data in the reverse manner that scrambling unit 300 scrambled the data.
• the values output from descrambling unit 310 should be identical to the values input from data bus 116.
• scrambling unit 300 and descrambling unit 310 are shown without a direct connection between them, one skilled in the art will recognize that they may receive/share a random or pseudo-randomly generated value.
• a scrambling function works as follows. A first combinatorial network, scrambling unit 300, uses function FI and a second combinatorial network, descrambling unit 310, uses function F2. If X is an n-bit (n being an integer) binary coded input from data bus 116, then F1(X) is the resulting output value of the first combinatorial network.
• FIG. 4 is a schematic illustrating one embodiment of the invention using a predetermined scrambling function.
• Scrambling register 300 includes inverter 400 and XOR 410.
• inverter 400 and XOR 410 The mathematical function of inverter 400 and XOR 410 is "+1 modulo 4.” If inputs D[0] and D[l] to scrambling unit 300 are "1" and "1,” respectively, then "11 +1 modulo 4" is equal to "00,” is the scrambling unit output of scrambling unit 300.
• One skilled in the art will recognize that many different functions may be used to scramble and descramble the data, for example "+1 modulo N,” N being any integer.
• Processing logic 204 should receive the initial input value of "11,” so inverter 420 and XNOR 430 of descrambling unit 310 produce the mathematical function "-1 modulo 4.”
• a descrambling unit input of "00” becomes “00-1 modulo 4,” which is equal to "11.”
• scrambling unit 300 produces a scrambling unit output that is loaded into configuration register 202 and transmitted to descrambling unit 310, which then produces a descrambled output, all within a single clock cycle.
• FIG. 4 is a schematic illustrating one embodiment of the invention using a random scrambling function.
• Scrambling unit 300 comprises, for example two-bit adder 500.
• Coupled to scrambling unit 300 is a number generator, either random or pseudo-random, for example number generator 505.
• Number generator 505 outputs a value to storage unit 510 and scrambling unit 300.
• Scrambling unit 300 receives the output from number generator 505 and adder 500 adds that number to a two-bit value received from data bus 116. The resulting sum is then transmitted to configuration register 202. For example, if number generator 505 produces the binary value "01,” and scrambling unit 300 receives "11" at its D[0] and D[l] inputs, then the resulting sum is "00.” "00" is the binary value transmitted to configuration register 202.
• Storage unit 510 saves the value output from number generator 505 so that whenever new data is written from data bus 116, a signal from write enable line 206 instructs storage unit 510 to output the new value, otherwise storage unit 510 outputs the last value used in scrambling unit 300.
• Descrambling unit 310 receives from storage unit the binary value transmitted from number generator 505 to storage unit 510 during a given clock cycle. Continuing with the above example, configuration register 202, after receiving the value "00" from scrambling unit 300, transfers the value "00" to descrambling unit 310.
• Descrambling unit 310 comprises two-bit subtracter 520, therefore descrambling unit 310 subtracts the value "01" from “00.”
• the value "01” was generated by number generator 505 and stored in storage unit 510 during the same clock cycle that descrambling unit 310 receives the value "00.”
• the result is "11,” which is the original value output from data bus 116 at the beginning of the clock cycle.
• storage unit 510 comprises multiplexer 530 and DFF 540.
• the content of configuration register 202 changes whenever it is being written to by data bus 116. In the next embodiment, the content of configuration register 202 changes every clock cycle, regardless of whether or not it is being written to.
• Figure 6 is a schematic illustrating one embodiment of the invention using a random scrambling function.
• data bus 116 transfers data to multiplexer 600.
• Multiplexer 600 receives a write-enable signal from enable write line 206 and transmits the data received from data bus 116 to scrambling unit 300.
• Scrambling unit 300 receives a random or pseudo-random number from number generator 505 and adds that number to the data received from multiplexer 600 with adder 500.
• the number is a two-bit binary number.
• the resulting scrambled number is transmitted to configuration register 610.
• Configuration register 610 loads one bit of each of the two-bit scrambled number into one of each of SDFF.
• DFF 630 also receives the random or pseudo-random number from number generator 505 and in the same clock cycle during which DFF 630 received the number, DFF 630 transmits the number to descrambling unit 310.
• Descrambling unit 310 receives the random or pseudo-random number from DFF 630 and it receives the scrambled content from SDFFs 620.
• Descrambling unit subtracts the random or pseudo-random number from the scrambled number using subtracter 525.
• Descrambling unit 310 outputs the descrambled value to processing logic 204 and to multiplexer 600.
• multiplexer 600 receives only descrambled output from descrambling unit 310. With no write-enable signal from enable write line 206, multiplexer 600 selects the descrambled output and transmits it to scrambling unit 300. Scrambling unit 300 receives a random or pseudo-random number from number generator 505 and the descrambled output, adds them and loads them into SDFFs 620. The effect of this is to rescramble with a new number, each clock cycle, the descrambled output from descrambling unit 310.
• number generator 505 could be another configuration register, a configurable register that is not part of scan chain system 126, the output of a finite state machine status flag, interrupt flag, or any other random or determinable value generator. Sensitive or confidential material loaded into configuration register 610 is more difficult to recover due to a variable and continuous scrambling function.
• Figure 7 is a flow diagram illustrating a method of scrambling sequential cell content in an integrated circuit. In block 700, scramble the data. In block 710, load the scrambled data into a sequential cell. In block 720, unload the scrambled data from the sequential cell. In block 730, descramble the data.

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• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Computer Security & Cryptography (AREA)
• Computer Hardware Design (AREA)
• Theoretical Computer Science (AREA)
• Software Systems (AREA)
• Logic Circuits (AREA)
• Storage Device Security (AREA)
• Test And Diagnosis Of Digital Computers (AREA)

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• 2004
  • 2004-07-08 WO PCT/US2004/022146 patent/WO2005008729A2/en active Application Filing
  • 2004-07-08 EP EP04777926A patent/EP1652217A4/de not_active Withdrawn

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