WO2005008501A1

WO2005008501A1 - Cache memory device and cache memory control method

Info

Publication number: WO2005008501A1
Application number: PCT/JP2003/009237
Authority: WO
Inventors: Takuma Chiba
Original assignee: Fujitsu Limited
Priority date: 2003-07-22
Filing date: 2003-07-22
Publication date: 2005-01-27

Abstract

A cache memory device includes a cache memory (12) based on the set associative method having a plurality of ways and a hit way history data storage section (90) for storing hit way history data corresponding to the way and address selected from a plurality of ways by a memory access in the past. In the hit way history data storage section (90), a way is searched by using as a key the address index section <13:4> during memory access and the way is output as a prediction way.

Description

Cache memory device and cache memory control method

Technical field

The present invention relates to a cache memory device having an n-way set associative type cache memory and a cache memory control method, and more particularly to a cache memory device and a cache memory control method capable of achieving high-speed operation.

It is about the law. 1

Thread

Field background technology

FIG. 8 is a block diagram showing a configuration of a conventional cache memory device. The cache memory device shown in this figure is a device provided with a cache memory 12 in order to bridge the speed difference between the CPU (Central Processing Unit) 10 and the main memory 13.

The CPU 10 reads / writes data by accessing the cache memory 12 or the main memory 13.

The main memory 13 has a large capacity and the access time is slower than that of the cache memory 12. As shown in FIG. 9, the main memory 13 stores all data used in the CPU 10.

That is, in the figure, in the main memory 13, each data of the 64 bit configuration is associated with 6 3: 0> (0 bits to 63 bits), and each data of the 64 bit configuration < 6 3: 0> is stored.

Returning to FIG. 8, the cache memory 12 is, for example, a static random access memory (SRAM), and has a characteristic that the access time is shorter than that of the main memory 13.

Furthermore, from the viewpoint of storage capacity, the storage capacity of the main memory 13 is Memory 12 is larger than the storage capacity.

Here, data transfer between the CPU and the cache memory (main memory) is generally performed in line units, and there are several methods for associating data in the main memory with lines in the cache memory.

As a typical method, the main memory and the cache memory are divided into a plurality of sets (a set of lines: this is called a way), and certain data in the main memory is stored only in a predetermined line in each way. There is a set associative method that cannot be placed.

When the cache memory is treated as one way in the set associative method, it is called 'direct mapping method (or 1-way set associative method)' and when there are n ways Is called the n-way set-associative method.

Fig. 10 shows the cache memory 12 (tag RAM 12a and data RAM 1

FIG. 3 is a diagram illustrating a 4-way set associative method in 2b). In the figure, the tag RAMI 2a and the data RAMI 2b have four ways (WAY 0

~ WAY3). The way of the tag RAMI 2a and the way of the data RAMI 2b correspond one-to-one.

In the same figure, the index <13: 4> is for uniquely specifying the line (horizontal direction) of the tag RAMI 2a and the data RAMI 2b, and the main memory 13 (see FIG. 9). It consists of 10 bits (4th to 13th bits) in address 63: 0>.

In the tag RAMI 2a, each entry specified by the index and the way includes the address stored in the main memory 13 at 63: 0>.

3: 14> is stored as a tag. In each entry, a valid bit V indicating whether the tag is valid or not is stored. If the valid bit V is 1, the tag is valid. On the other hand, if the valid bit V is 0, the tag is invalid. On the other hand, in the data RAMI 2 b, each entry specified by the index and the way stores data 63: 0> stored in the main memory 13.

Returning to FIG. 8, the cache access control unit 11 controls access to the cache memory 12.

FIG. 11 is a diagram showing the configuration of the cache access control unit 11 and the cache memory 12 shown in FIG. In the figure, a latch circuit 20 is a circuit for latching an address byte offset part 3: 0> included in an address 63: 0> from the CPU 10 (see FIG. 8).

The latch circuit 21 is a circuit that latches the address tag portion 63:14> included in the address portion 63: 0>. In the tag RAMI 2a and the data RAMI 2b, the address index part 13: 4> included in the address 63: 0> is input as a search key.

As shown in FIG. 12, in the tag RAMI 2a and the data RAMI 2b, an index that matches the address index part 13: 4> is searched among a plurality of indexes, and the line corresponding to the index is uniquely identified. Is specified.

As shown in FIG. 10, the tag RAMI 2a outputs the tags 63:14> and the effective bits V stored in the respective entries of WAY0 to WAY3 corresponding to the above line. You. Returning to FIG. 11, the latch circuits 22 to 25 are circuits for latching the respective tags 63:14>, and correspond to WAY0 to WAY3 of the tag RAMI 2a (see FIG. 10). The latch circuits 26 to 29 are circuits for latching the above-mentioned effective bits, and correspond to WAY 0 to 3 (see FIG. 10) of the tag RAM 12a.

On the other hand, as shown in FIG. 10, the data RAMI 2b outputs the data 63: 0> stored in the respective entries of WAY 0 to 3 corresponding to the above line. Referring back to FIG. 11, the latch circuits 30 to 33 store the above data <63: 0>. This circuit corresponds to WAY 0-3 of data RAMI 2b (see Fig. 10).

The comparators 40 to 43 and AND circuits 50 to 53 correspond to WAYs 0 to 3, respectively. The comparator 40 compares the address tag section 63:14> latched by the latch circuit 21 with the tag section 63:14> (corresponding to WAY 0) latched by the latch circuit 22. WAY 0—HI T (See Figure 12: Way 0 hits).

The AND circuit 50 is a circuit for ANDing the output of the comparator 40 and the valid bit V latched by the latch circuit 26. When the AND condition is satisfied, the AND circuit 50 outputs WAY 0 — H IT to the OR circuit 60 and outputs WAY 0 — H IT to the selector 70 as a selection signal SEL 70 (corresponding to WAY 0).

The comparator 41 compares the address tag portion 63:14> latched by the latch circuit 21 with the tag tag 63:14> (corresponding to WAY 1) latched by the latch circuit 23, and when they match, WAY 1—HI T (See Fig. 12: Way 1 hits).

The AND circuit 51 is a circuit that ANDs the output of the comparator 41 and the valid bit V latched by the latch circuit 27. When the AND condition is satisfied, the AND circuit 51 outputs WAY 1 — HIT to the OR circuit 60 and outputs WAY 1 — HIT to the selector 70 as the selection signal SEL 70 (corresponding to WAY 1). .

The comparator 42 compares the address tag portion 63:14> latched by the latch circuit 21 with the tag <63:14> (corresponding to WAY 2) latched by the latch circuit 24, and when they match, WAY2_HIT (see Fig. 12: Pay 2 hit) is output.

The AND circuit 52 is a circuit that ANDs the output of the comparator 42 and the valid bit V latched by the latch circuit 28. The AND circuit 52 has the AND condition When the condition is satisfied, WAY 2 — HIT is output to the OR circuit 60, and WAY 2 — HIT is output to the selector 70 as the selection signal SEL 70 (corresponding to WAY 2).

The comparator 43 compares the address tag section 63:14> latched by the latch circuit 21 with the tag section 63:14> (corresponding to WAY 3) latched by the latch circuit 25, and when they match, Outputs WAY 3_H IT (see Fig. 12: way 3 hits).

The AND circuit 53 is a circuit that ANDs the output of the comparator 43 and the valid bit V latched by the latch circuit 29. When the AND condition is satisfied, the AND circuit 53 outputs WAY 3—HI へ to the OR circuit 60, and outputs WAY 3—HIT as the selection signal SEL 70 (corresponding to WAY 3) to the selector 70. I do.

The OR circuit 60 ORs the outputs of the AND circuits 50 to 53 (WAYO—HIT to WAY3—HIT). After latching the output of the OR circuit 60, the latch circuit 34 outputs CACHE-HIT (cache hit).

The selector 70 outputs the data <63: 0> latched in the latch circuit corresponding to the selection signal SEL70 (one of WAY0 to 3) among the data 63: 0> latched by the latch circuits 30 to 33. Select ＞ and output this. After latching the data <63: 0> selected by the selector 70, the latch circuit 35 outputs the result as a cache hit result.

At the time t0 shown in FIG. 13, the CPU 10 (see FIG. 8) transfers the necessary data from the cache memory 12 (the main memory 13 in the case of a cache miss). : 0> is output to the cache access control unit 11 to read out the address 63: 0> corresponding to the data 63: 0>.

Thereby, at time tl, the processing of the tag RAMI 2a and the processing of the data RAMI 2b are executed in parallel. That is, in the tag: RAMI 2a, the address index part 13: 4> included in the address <63: 0> is used as a search key, As shown in FIG. 10, an index matching the indexless index part 13: 4> is searched from a plurality of indexes, and a line corresponding to the index is specified at will.

As a result, at time t 2 (see FIG. 13), the tag RAM 63 a from the tag RAMI 2 a stored in the respective entries of WAY 0 to WAY 3 corresponding to the above-mentioned line is latch circuit 22. Latched to ~ 25.

Further, at time t2, the valid bits V stored in the respective entries of WAY0 to WAY3 corresponding to the above line are latched by the latch circuits 26 to 29 from the tag RAMI2a. '

On the other hand, in the data RAMI 2b, as shown in FIG. 10, the address index portion included in the address 63: 0> is used as a search key, and as shown in FIG. : 4 An index matching> is searched, and the line corresponding to the index is uniquely specified.

As a result, the data stored in each of the WAY 0 to WAY 3 entries corresponding to the above lines is latched from the data RAMI 2 b at the B temple time t 2 (see FIG. 13). Latched in circuits 30-33.

At time t2, the address byte offset portion 3: 0> is latched in the latch circuit 20, and the address tag portion 63:14> is latched in the latch circuit 21.

Then, from time t2 to time t3, comparison processing and hitway selection processing are performed. That is, in the comparison process, in the comparators 40 to 43, the address tags 63:14> latched by the latch circuit 21 and the tags respectively latched by the latch circuits 22 to 25:63:14> (Corresponding to WAY 0 to 3). In this case, assuming that the address tag 63:14> matches the tag 63:14> corresponding to WAY 0, the comparator 40 outputs WAYO-HIT to the AND circuit 50. The comparison results of the other comparators 41 to 43 are all inconsistent. The AND circuit 50 performs an AND operation on the output of the comparator 40 (WAY 0—HI T) and the output of the latch circuit 26 (valid bit V: supposed to be valid), and sends WAY 0 — HIT to the OR circuit 60 Output.

In the hitway selection process, WAYO-HIT from the AND circuit 50 is input to the selector 70 as a selection signal SEL70 (corresponding to WAYO). As a result, the selector 70 selects and outputs the data 63: 0> latched by the latch circuit 30 (corresponding to WAYO).

Then, at time t3, after the WAYO-HIT from the OR circuit 60 is latched by the latch circuit 34, a CACHE-HIT (cache hit) is output to the CPU 10. At time t 3, the data selected by the selector 70 (63: 0> (corresponding to WAYO)) is latched and then output to the CPU 10.

Patent Document 1 JP 2001-075864 A

By the way, as described above, in the conventional cache memory device and cache memory control method, a hitway is selected after an address 63: 0> is output from the CPU 10, and a data address 63: 0> is output from the cache memory 12. It takes four cycles (time t0 to time t3 in Fig. 13) to output, and there was a problem that it was not possible to sufficiently meet the needs for high speed.

The present invention has been made in view of the above, and has as its object to provide a cache memory device and a cache memory control method that can achieve high speed. Disclosure of the invention

In order to achieve the above object, the present invention relates to a cache memory adopting a set associative method having a plurality of ways, and a way address selected from a plurality of ways in a memory access in the past. Hitway history data storage means for storing hitway history data; a search means for searching a way from the hitway history data using an address at the time of memory access as a key; Data corresponding to the And reading means for reading out the memory.

Further, the present invention is a cache memory control method for controlling access to a cache memory employing a set associative method having a plurality of ways, wherein the cache memory is selected from a plurality of ways by memory access in the past. A search is made from the hitway history data using the hitway history data storage amount for storing the hitway history data corresponding to the accessed way and address, and the address at the time of memory access as a key, and the way is searched for. In particular, the method includes: a prediction step of setting a prediction way; and a reading step of reading data corresponding to the prediction layer from the cache memory.

According to the powerful invention, hitway history data corresponding to a way address selected from a plurality of ways in a memory access in the past is stored, and the way is set using the address at the time of memory access as a key. After searching and predicting the way as the prediction way, the data corresponding to the prediction way is read from the cache memory, so that the way to determine the data reading is determined earlier than in the past, High speed riding can be achieved. Brief Description of Drawings

FIG. 1 is a block diagram showing the configuration of the first embodiment according to the present invention. FIG. 2 is a diagram showing the configuration of the cache access control unit 80 and the cache memory 12 shown in FIG. FIG. 3 is a diagram showing the configuration of the hitway history data storage unit 90 shown in FIG. 2, and FIG. 4 is a diagram for explaining the operation of the first embodiment. FIG. 6 is a block diagram showing a configuration of a second embodiment according to the present invention. FIG. 6 is a diagram showing a configuration of the cache access control unit 140 and the cache memory 12 shown in FIG. FIG. 7 is a diagram showing the configuration of the hitway history data storage section 150 shown in FIG. 6, and FIG. 8 is a block diagram showing the configuration of a conventional cache memory device. FIG. 9 is a diagram showing the main memory 13 shown in FIG. 8, and FIG. Tag shown in FIG. 8 R AM I 2 a, and data R FIG. 11 is a diagram showing AM I 2b, FIG. 11 is a diagram showing the configuration of the cache access control unit 11 and the cache memory 12 shown in FIG. 8, and FIG. FIG. 13 is a diagram for explaining the operation of the cache memory device. FIG. 13 is a diagram for explaining the operation of the conventional cache memory device. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, Embodiments 1 and 2 according to the present invention will be described in detail with reference to the drawings.

(Embodiment 1)

FIG. 1 is a block diagram showing a configuration of a first embodiment according to the present invention. In this figure, parts corresponding to the respective parts in FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 1, a cache access control unit 80 is provided instead of the cache access control unit 11 in FIG.

The cache access control unit 80 has a function of predicting a way in addition to the function of the cache access control unit 11.

FIG. 2 is a diagram showing a configuration of the cache access control unit 80 and the cache memory 12 shown in FIG. In this figure, parts corresponding to those in FIG. 11 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 2, a hitway history data storage unit 90, a selector 100, a latch circuit 110 to 112, and a comparator 120 are newly provided.

The hitway history data storage section 90 stores history data of the latest four hitways, that is, the hitway selected by the hit selection processing (selection signal SEL70 (WAY0 to 3—HIT)). Is stored.

FIG. 3 is a diagram showing a configuration of the hitway history data storage unit 90 shown in FIG. In the hitway history data storage section 90 shown in the figure, the FIFO (Fast In Fast Out) register 91 stores the latest four hitways (WAY 0 HIT to WAY 3 HIT) and hits. Key when selecting way Stores history data consisting of the dress index part 13: 4>.

In the FIFO register 91, the way register section 91WO and the address register section 91AO store the latest hitway and address index section 13: 4> of the past four times.

The way register section 91W1 and the address register section 91A1 store the second newest hitway and address index section 13: 4> of the past four times.

The way register section 91W2 and address register section 91A2 store the third newest hitway address index section 13: 4> of the past four times. The way register section 91W3 and the address register section 91A3 store the oldest hitway and address index section <13: 4> of the past four times.

In the FIFO register 91, when a new hit way and address index section <13: 4> are stored, each piece of history data is shifted rightward in the figure, and the oldest history data is expelled.

The comparators 93 to 96 are provided corresponding to the address register sections 91 A0 to 91 A3, and have an address index section 13: 4> and an address index section stored in the address register sections 91 A0 to 91 A3. 13: 4> and compare. In addition, the comparators 93 to 96 output a selection signal SEL 97 for selecting the address register section (corresponding way register section) to the selector 97 when they match.

The selector 97 selects the hit way stored in the way register corresponding to the selection signal SEL 97 from among the hit ways stored in the pay registers 91W0 to 91W3, and predicts the hit way (P_WAY0_HIT to P—WAY). 3—HIT) and output to latch circuit 110 (see Fig. 2). The latch circuit 110 latches the predicted hitway.

In addition, the selector 97 selects the prediction hitway (P WAYO HIT to P WA Y3—HIT) is output to the selector 100 as the selection signal SEL 100 shown in FIG.

Selector 100 outputs the data corresponding to WAY 0 to 3 output from data RAMI 2b 63: 0> to the data of the way corresponding to selection signal SEL 100 (predicted hit way). Select> and output to the latch circuit 111.

The latch circuit 111 latches the data of the way 63: 0> as the prediction data 63: 0> based on the prediction hitway.

The comparator 120 compares the prediction hitway latched by the latch circuit 110 with the selection signal SEL70 (WAYO to 3—HI T), and turns on P_WA Y—HI T (prediction way hit) if they match. And outputs it to the latch circuit 112. The latch circuit 112 latches P—WAY_HIT (predicted way hit). The fact that this P—WAY-HIT (prediction way hit) is on means that the prediction hitway predicted by the hitway history data storage unit 90 and the actual hitway match, and the prediction was successful. Means that.

The latch circuit 112 that latches P—WAY—HIT (predicted way hit) outputs P—DATA—V (predicted data valid bit) to the CPU 10 (see FIG. 1). P—DATA—V (predicted data valid bit) enables the predicted data <63: 0> output from the latch circuit 111, while invalidates the data output from the latch circuit 35 (63: 0). Is a bit for

On the other hand, when the prediction way latched by the latch circuit 110 and the selection signal SEL 70 (WAY0 to 3—HI T) do not match, the comparator 120 outputs P—WAY—HI T (prediction way hit). Turn off and output to latch circuit 112. The fact that this P_WAY_HIT (predicted way hit) is off means that the predicted hit way predicted by the hittweet history data storage unit 90 does not match the actual hittwey and the prediction was missed. ing.

When P_DATA_V (predicted data valid bit) is off, the predicted data <63: 0> output from the latch circuit 111 is invalidated, while the latch circuit 35 is disabled. 63: 0> is valid.

In the above configuration, at time t0 shown in FIG. 4, the CPU 10 (see FIG. 1) reads out the necessary data (63: 0) from the cache memory 12 (in the case of a cache miss, the main memory 13). Then, the address <63: 0> corresponding to the data <63: 0> is output to the cache access control unit 140.

Thereby, at time tl, the processing of the tag RAMI 2a and the processing of the data RAMI 2b are executed in parallel. That is, in the tag RAMI 2a, the address index portion 13: 4> included in the address 63: 0> is used as a search key, and as shown in FIG. An index that matches 3: ⁴ > is searched, and the line corresponding to the index is uniquely specified.

As a result, at time t2 (see FIG. 4), the tag RAMI2a outputs the tag data 63:14> stored in each of the WAY0 to WAY3 entries corresponding to the above line to the latch circuit. Latched at 22-25.

Further, at time t2, from the tag RAMI2a, the valid bits V stored in the respective entries of WAY0 to WAY3 corresponding to the above line are latched by the latch circuits 26 to 29.

On the other hand, in the data RAMI 2b, as shown in FIG. 10, the address index part 13: 4> included in the address index 63: 0> is used as a search key, and as shown in FIG. : 4 An index matching <> is searched, and a line corresponding to the index is uniquely specified.

As a result, at time t 2 (see FIG. 4), the data RAMI 2 b outputs the data stored in each of the WAY 0 to WAY 3 entries corresponding to the above line.

: 0> is latched by the latch circuits 30 to 33.

In addition, in Toki'Jt2, the address byte offset portion is added to the latch circuit 20 at 3: 0.

Is latched, and the address tag section 63:14> is latched in the latch circuit 21. Further, at time t1, way prediction processing is executed in parallel with the processing of the tag RAMI 2a and the data RAMI 2b described above. Specifically, the address index part 13: 4> included in the address <63: 0> from the CPU 11 is input to the comparators 93 to 96 of the hitway history data storage unit 90 shown in FIG. You. As a result, the comparators 93 to 96 compare the input address index portion 13: 4> with the address index portion 13: 4> stored in the address register portions 91 A0 to 91 A3.

Here, if the input address index portion 13: 4> matches the address index portion 13: 4> stored in the address register portion 91 AO, the comparator 93 sets the address register portion. A select signal SEL 97 for selecting the way register section 91W0 corresponding to 91 AO is output to the selector 97. The selector 97 selects a hit way (WAY 0—HI T) stored in the way register section 91WO corresponding to the selection signal SEL 97 among the hit ways stored in the way register sections 91W0 to 91W3, and predicts the hit. It outputs to the latch circuit 110 shown in FIG. 2 as a way (P-WAYO-HI T).

Thus, the latch circuit 110 latches the predicted hit time (P—WAY 0—HI T) at time t 2 (see FIG. 4).

The selector 97 outputs the predicted hitway (P—WAY 0—HIT) to the selector 100 as a selection signal SEL100.

The selector 100 outputs the data corresponding to WAY0 to 3 output from the data RAMI 2b (63: 0), and selects the WAY0 corresponding to the selection signal SEL100 (predicted hitway (P-WAYO-HIT)). Select data 63: 0> and output it to the latch circuit 111.

As a result, at time t 2 (see FIG. 4), the latch circuit 111 latches the data of the WAY 0, 63: 0>, as prediction data <63: 0> based on the prediction way, and then latches this prediction. Outputs data <63: 0> to CPU10.

As a result, the CPU 10 has one cycle more than before (in the case of FIG. 13, Execute processing at time t3. In contrast, in the case of Fig. 4, processing is performed at time t2. ) Perform processing based on the predicted data 63: 0> quickly.

From time t2 to time t3, comparison processing, hitway selection processing, and prediction verification processing are performed. That is, in the comparison processing, in the comparators 40 to 43, the address tag section 63:14> latched by the latch circuit 21 and the tag <63:14> (WAY 0) latched by the latch circuits 22 to 25 respectively. (Corresponds to ~ 3).

In this case, if it is assumed that the address tag 63:14> matches the tag 63:14> corresponding to WAY 0, the comparator 40 outputs WAYO—HIT to the AND circuit 50. The comparison results of the other comparators 41 to 43 are all inconsistent.

In the AND circuit 50, the output (WAY0_HI T) of the comparator 40 and the latch circuit

AND with output (valid bit V: valid) with 26, WAY0

— Output HIT to OR circuit 60.

In the hitway selection process, WAYO-HIT from the AND circuit 50 is input to the selector 70 as a selection signal SEL70 (corresponding to WAY 0). As a result, the selector 70 selects and outputs the data 63: 0> latched by the latch circuit 30 (corresponding to WAYO).

In the prediction verification process, the comparator 120 compares the prediction hitway latched by the latch circuit 110 with the selection signal SEL 70 (WAY 0 to 3—HI T), and when they match, P_WAY_HIT Latch circuit (prediction way hit) 1

Output to 12.

Then, at time t3, after the WAYO-HIT from the OR circuit 60 is latched by the latch circuit 34, a CACHE-HIT (cache hit) is output to the CPU 10.

At time t3, the data <63: 0> (corresponding to WAYO) selected by the selector 70 is latched and then output to the CPU 10. Furthermore, Tokii lj t 3 In the latch circuit 112, P—WAY—HIT (predicted way hit) is latched.

Thereby, processing based on the prediction verification result is executed. That is, when P—WAY—HI T (predicted way hit) is on, the latch circuit 112 outputs P—DATA—V (predicted data valid bit) to the CPU 10 (see FIG. 1). You.

Accordingly, the CPU 10 validates the predicted data <63: 0> output from the latch circuit 111, and invalidates the data 63: 0> output from the latch circuit 35.

On the other hand, if P-WAY-HI T (predicted way hit) is off, P-DATA-V (predicted data valid bit) is turned off and output to CPU 10 (see Fig. 1).

As a result, the CPU 10 invalidates the prediction data 63: 0> output from the latch circuit 111, while validating the data 63: 0> output from the latch circuit 35. In this case, the CPU 10 executes the process using the data 63: 0> as in the conventional case.

As described above, according to the first embodiment, hitway history data corresponding to a way address selected from a plurality of ways in the past memory access is stored in the hitway history data storage unit 90. Then, using the address index part 13: 4> at the time of memory access as a key, a way is searched, and after predicting the way as a predicted way, data corresponding to the predicted way is read from the data RAMI 2b. However, as compared with the related art, the determination of the wire involved in the data reading is quicker, and the speed can be increased.

(Embodiment 2)

FIG. 5 is a block diagram showing a configuration of a second exemplary embodiment according to the present invention. In this figure, parts corresponding to the respective parts in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 5, the cache access control unit 80 shown in FIG. In addition, a cache access control unit 140 is provided.

The cache access control unit 140 has a function of predicting a way in the same way as the cache access control unit 80 (see FIG. 1), in addition to the function of the cache access control unit 11 (see FIG. 8). Have.

FIG. 6 is a block diagram showing a configuration of the cache access control unit 140 and the cache memory 12 shown in FIG.

In this figure, parts corresponding to those in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted.

In FIG. 6, a hitway history data storage unit 150 is provided in place of the hitway history data storage unit 90 shown in FIG.

As shown in FIG. 7, the hitway history data storage section 150 includes 4-way RAMs 60 to 163 in the same manner as the tag RAM 12a and the data RAMI 2b (see FIG. 6). .

In the cache memory 12 and the cache access control unit 140, when there is an access request from the CPU 10, the data corresponding to the access address (63: 0) from the CPU 10 is returned to the CPU 10 and the data from the CPU 10 is returned. The access address 17: 4> and the information of the WAY hit by the access are sent to the hit way history data storage unit 150.

In the hitway history data storage section 150 shown in FIG. 7, the access address 17:14> of the received access address <17: 4> is stored in the hitway history write data 17:14> and the access address 13: Data is written to RAMIs 60 to 163, with 4> being the hitway history write index 13: 4> and the hit WAY information being the hitway history storage section write way 3: 0>.

When the hitway history data storage unit 150 receives the hitway history write data # 17: 14>, the hitway history write index # 13: 4>, and the hitway history storage unit write way # 3: 0>, the RAMI 60 ~ 163 of Of these, four bits of hitway history write data <17:14> are located at the position corresponding to the hitway history write index 13: 4> in the RAM indicated by the hit history history storage unit write 3: 0>. Write the data of Also, when there is an access request from the CPU 10 to the cache access control unit 140 (cache memory 12), the hitway history data storage unit 150 stores the access address from the CPU 10 in the access address 63: 0>. Address 1 7: 4> is input.

The access address <17:14> of the input access address <17: 4> is used as way history comparison data 17:14>. In addition, the access address <13: 4> of the access address <17: 4> is used as the default address 13: 4>.

When the current index 13: 4> is input to the RAMI 60, the hitway history read data 3: 0>, which is 4-bit data corresponding to the index, is output.

At the same time, address index 13: 4> is also input to RAMI 61 ~: AMI 63, and hitway history read data 3: 0> is output from each.

The comparators 170 to 173 are provided corresponding to the RAMIs 60 to 163. The comparators 170 to 173 read the hitway history read data 3: 0> from the RAMIs 60 to 163 and the addresses 63: 0> from the CPU 10. The obtained hitway history comparison data <17:14> is compared, and if they match, the predicted hittuy corresponding to the way (one or more of P—WAYO—HIT to P—WAY3—HIT) Is output to the selector 180.

In addition, when the number of predicted hitways from the comparators 170 to 173 is one, the selector 180 selects one of the predicted hitways (P—WAYO—HIT to P—WAY3—HIT in FIG. 6). Output to latch circuit 110.

Also, the selector 180 selects the predicted hitway (P WAYO HI T ~ P _WAY 3 _HIT) is output to the selector 100 as the selection signal SEL 100 0 shown in FIG.

When the number of predicted hitways from the comparators 170 to 173 is plural (multi-hit), the selector 180 sets a plurality of predicted hitways (P—WAY 0—HIT to P—WAY). 3—HIT), the predicted hit way corresponding to the youngest way (or the predicted hit way corresponding to one randomly selected way or the predicted hit way corresponding to the newest one way) is output. The method of selecting a predicted hitway in the case of a multi-hit is also applicable to the first embodiment (selection signal SEL97 in FIG. 3).

As described above, according to the second embodiment, the same effects as in the first embodiment can be obtained.

Also, in the second embodiment, the value of the access address 17:14> used as the write data of the hitway history is changed according to the environment and the application to be used and the program to be executed. It may be configured to change to a value other than 4>. In this case, the accuracy of way prediction can be improved. For example, when the access address 17:14> in FIG. 7 is changed to the access address <21: 4>, the history data selection signal (not shown) causes the history write data 17: 14> or history write data <21: 18> is selected, and the 4-bit data obtained by that is used as way history comparison data.

When writing hit history log data to hit history log storage section 150, access address <21:18> or access address 17:14> is selected by the history data selection signal. The selected access address is used as hitway history write data. In this case, the selected hitway history write data is hitway history write data. By switching the history data selection signal in this way, the value of hitway history data can be changed arbitrarily, and the system status, environment, program Can be predicted.

Although the first and second embodiments according to the present invention have been described in detail with reference to the drawings, specific configuration examples are not limited to the first and second embodiments and do not depart from the gist of the present invention. Even a change in the design of the range is included in the present invention. As described above, according to the present invention, hitway history data corresponding to a way and an address selected from a plurality of ways in a past memory access is stored, and the address at the time of the memory access is used as a key. Since the way is searched, the way is predicted as the predicted way, and the data corresponding to the predicted way is read from the cache memory, the way to read the data is determined earlier than in the past. This has the effect of increasing the speed. Industrial applicability

As described above, the cache memory device and cache memory control method according to the present invention is useful for cache memory access control.

Claims

The scope of the claims

1. A cache memory employing a set associative method having a plurality of bays,

Hitway history data storage means for storing hitway history data corresponding to a way and an address selected from a plurality of ways in a memory access in the past;

Prediction means for searching a way from the hitway history data using an address at the time of memory access as a key, and using the way as a prediction way;

Reading means for reading data corresponding to the predicted way from the cache memory;

A cache memory device comprising:

2. The cache memory device according to claim 1, wherein said hitway history data storage means stores said hitway history data separately for each layer.

3. The prediction means according to claim 1, wherein in the case of a multi-hit in which a plurality of ways are searched in the hitway history data storage means, a way with a smaller number is set as the prediction way. Or the cache memory device described in paragraph 2.

4. In the case of a multi-hit in which a plurality of ways are retrieved from the hitway history data storage means, the prediction means sets one randomly selected way as the prediction way. 3. The cache memory device according to paragraph 1 or 2.

5. The multi-hit in which a plurality of ways are retrieved from the hitway history data storage means, wherein the prediction means sets the way stored latest as the prediction way. Or the cache memory device according to paragraph 2.

6. A prediction verification means for verifying the validity of the prediction way and invalidating data corresponding to the prediction way when the prediction of the prediction way is incorrect. Item 3. The cache memory device according to item 1 or 2.

7. The hitway history data is set to an arbitrary value, and the prediction means selects a desired value from the hitway history data stored in the hitway history data storage means. 3. The cache memory device according to claim 1 or 2.

8. A cache memory control method for controlling access to a cache memory employing a set associative method having a plurality of ways,

A hitway history data storage step of storing hitway history data corresponding to a way address selected from a plurality of ways in a memory access in the past;

A prediction step of searching for a way from the hit way history data using an address at the time of memory access as a key, and setting the way as a prediction way;

A reading step of reading data corresponding to the predicted way from the cache memory;

A cache memory control method comprising:

9. The cache according to claim 8, wherein in the hitway history data storing step, the hitway history data is stored separately for each key. Memory control method.

10. In the prediction step, in the case of a multi-hit in which a plurality of ways are searched in the hitway history data storage step, a way having a smaller number is set as the prediction way. A cache memory control method according to paragraph 8 or 9.

In the prediction step, in the case of a multi-hit in which a plurality of pairs are searched from the hitway history data storage step, one randomly selected phase is set as the prediction layer. The cache memory control method according to claim 8 or 9, wherein

12. In the prediction step, in the case of a multi-hit in which a plurality of layers are searched from the hitway history data storage step, a way whose storage is latest is set as the prediction layer. 10. The cache memory control method according to item 8 or 9.

13. A prediction verification step of verifying the validity of the prediction way and, if the prediction of the prediction way is incorrect, including a prediction verification step of invalidating data corresponding to the prediction way. 10. The cache memory control method according to item 9 or.