WO2005001720A1 - Verknüpfung und darstellung von signalen einer vorrichtung zur hardware-simulation und elementen eines listings eines programms - Google Patents
Verknüpfung und darstellung von signalen einer vorrichtung zur hardware-simulation und elementen eines listings eines programms Download PDFInfo
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- WO2005001720A1 WO2005001720A1 PCT/EP2004/004991 EP2004004991W WO2005001720A1 WO 2005001720 A1 WO2005001720 A1 WO 2005001720A1 EP 2004004991 W EP2004004991 W EP 2004004991W WO 2005001720 A1 WO2005001720 A1 WO 2005001720A1
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- WIPO (PCT)
- Prior art keywords
- program
- signals
- elements
- listing
- display means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
Definitions
- the invention relates to a system and a method for displaying signals of a device for hardware simulation and a troubleshooting tool.
- a hardware software cosimulator for simulating a hardware software system which has a logical simulator, bus interface models, memory models, instruction set simulators and a so-called co-simulation optimization manager.
- the simultaneous simulation of hardware and software is also called cosimulation.
- the cosimulation is carried out with a single, coherent look at the memory of the hardware software system, which is maintained transparently by the cosimulation optimization manager for both hardware and software simulations.
- the invention has for its object to enable the common representation of signals from a device for hardware simulation and elements of a program listing.
- a system for linking and displaying signals from a device for hardware simulation and elements of a program listing wherein the device for hardware simulation is the behavior of a circuit with a processor, a program memory, which contains the program code of the program contains and simulates application-specific hardware components and generates signals as a result of the simulation, • the elements of the program listing are linked to the signals generated during the simulated execution of the program code contained in the program memory and corresponding to these elements, • the elements of the program listing in a first partial area of a graphic display means and the signals in a second Part of the display means can be displayed.
- This object is achieved by a method for linking and displaying signals from a device for hardware simulation and elements of a program listing,
- the device for hardware simulation simulates the behavior of a circuit with a processor, a program memory which contains the program code of the program, and application-specific hardware components and generates signals as a result of the simulation,
- the device for hardware simulation simulates the behavior of a circuit with a processor, a program memory which contains the program code of the program, and application-specific hardware components and generates signals as a result of the simulation, •
- the debugging tool has means for linking the elements of the listing of the program with the signals generated during the simulated execution of the program code contained in the program memory and corresponding with these elements, the elements of the listing of the program in a first partial area of a graphic display means and the signals can be represented in a second partial area of the display means.
- the invention is based on the knowledge that the design of hardware software systems is considerably simplified by a linked representation of the signals of a hardware simulator and the elements of the listing of a program.
- the system and method according to the invention enables simple and fail-safe tracking of the execution of a program.
- the presentation of the program's listing provides a direct link to the actual program, in particular the comments inserted in the original source text can also be displayed due to the use of the list file.
- An abstract software model of the processor is not required to link and display the signals of the hardware simulation device and the elements of the program listing. It is therefore guaranteed that the processor used in the circuit is actually simulated. Errors in the simulation caused by a description of the processor by means of a model are thus excluded.
- the visualization of the program flow takes place in a form similar to that of conventional development tools for debugging pure software.
- the training period for users of the system or the method, who have experience in the development of software or firmware, is therefore relatively short.
- a marking of an element of the listing of the program in the first partial area of the graphic display means and Marking of the signals associated with this element is provided in the second section of the display means.
- the graphic representation is thus based on conventional software debugging tools.
- the program progress can be followed by marking an element of the program listing.
- a marker moves synchronized to the mark in the first part of the display means, so that cross-relationships to the other hardware can also be detected.
- a third sub-area of the graphic display means is advantageously provided for displaying at least a part of the signals, in particular further values.
- Other values can be register values, for example.
- the system can be adapted to different processors with little effort if, in accordance with an advantageous embodiment of the invention, means are provided for adapting the system to different processor types.
- 1 shows a schematic representation of a system for linking and representing signals of a device for hardware simulation and elements of a program listing
- 2 shows a section of a representation of signals from a device for hardware simulation
- FIG. 3 shows a representation of signals from a device for hardware simulation and elements of a program listing.
- the device for hardware simulation 1 simulates the behavior of a circuit 6 with a processor 7, a program memory 8 and application-specific hardware components 10.
- the processor 7 can e.g. B. be a microprocessor or microcontroller.
- the program memory 8 contains the program code 9 of the program 3.
- the reference code 17 denotes the source code in VHDL.
- the device for hardware simulation 1 is accordingly also referred to as an HDL simulator.
- An example of an HDL simulator is the "ModelSim” product from Model Technology, Portland, Oregon, USA.
- the HDL source code 17 is converted with a suitable compiler into an HDL simulator format 18, which can be processed by the hardware simulation device 1.
- the device for hardware simulation 1 generates signals 4, 5 as a result of the simulation.
- Program 3, or program code 9 of program 3 is converted by means of a compiler into a data file 16 (usually with data in hexadecimal form) and a listing 2, also called a list file.
- Listing 2 contains both the program commands and the due comments.
- Listing 2 is structured line by line, with each line containing a program command or instruction, possibly with the associated comment.
- a line, a program command, an instruction or a comment are elements 15 of the listing 2.
- a debugger 19 links the elements 15 of the listing 2 of the program 3 with the program codes which correspond to these elements 15 when the execution of the program contains 8 9 generated signals 4, 5.
- the elements 15 of the listing 2 of the program 3 are shown in a first partial area 11 of the graphic display means 14 and the signals 4, 5 in a second partial area 12 or in a third partial area 13 of the display means 14.
- the 2 shows a section 30 of a representation of signals 4, 5 of a device for hardware simulation 1.
- the signals 4, 5 are represented as so-called waveforms 35, 36 and 37.
- the 3 shows a representation 23 of signals 4, 5 of a device for hardware simulation 1 and elements 15 of a listing 2 of a program 3.
- the elements 15 of the listing 2 are in a first partial area 11, the signals 4, 5 in a second 12 or a third 13 partial area of a display means 14.
- the elements 15 can be marked 20, e.g. B. a color coding.
- the signals 4 can be marked 21, e.g. B. a cursor.
- a display means 14 can be a screen surface, the partial areas 11 to 13 can be realized as a display window.
- the sequence of the program 3 in the processor 7 (see FIG. 1) is visualized with the help of the graphic front end, the debugger 19, which is based on the signals 4, 5 of the device for hardware simulation 1.
- the program sequence is visualized by accessing signals of the processor 7, the values of which have been calculated by the hardware simulation device 1.
- HDL objects can e.g. B. are represented as waveforms.
- the debugger 19 is divided into two sections.
- a first general part provides procedures for visualization.
- a second processor-specific part is adaptable to the respective processor and is set, for. B. from the following procedures:
- frame_toolbar. autostep_right configure -background gray -activebackground khaki2 .mainFrame.
- label_message configure -bg DimGray -fg red -text "End of Simulation reached.” set minideb (auto_step_right) 0 .mainFrame. frame_toolbar. autostep right configure -background gray -activebackground khaki2 .mainFrame.
- the command currently being executed is identified in FIG. 2 by the reference symbol 31)
- the valid command is determined on a processor-specific basis. In modern processor architectures, it is usually not sufficient to track the program counter 36, but rather additional signals 4, 5 are to be evaluated which indicate whether the current command is valid (e.g. the signal on which the waveform 34 is based). If a valid command has been determined, the marking 20 of the command currently being executed takes place in the displayed listing in the first partial area 11 of the display means 14 and the register values are displayed in the third partial area 13 of the display means 14 (see the following section of a listing).
- progadr_int [hex2int $ progadr] set progadr_int [expr $ minideb (address multiplier) * $ progadr_int] set progadr [int2hex $ progadr_int]
- the invention thus relates to a system and a method for linking and displaying signals 4, 5 of a device for hardware simulation 1 and elements 15 of a listing 2 of a program 3, and a troubleshooting tool.
- the device for hardware simulation 1 determine the behavior of a circuit 6 with a processor 7, a program memory 8, which contains the program code 9 of the program 3, and simulates application-specific hardware components 10 and generates signals 4, 5 as a result of the simulation that the elements 15 of the listing 2 of the program 3 with those contained in the program memory 8 in the simulated execution signals 4, 5 generated with these elements 15 corresponding program codes 9 are linked and that the elements 15 of the listing 2 of the program 3 can be represented in a first partial area 11 of a graphic display means 14 and the signals 4, 5 in a second partial area 12 of the display means 14 are.
- the circuits described are e.g. B. in so-called embedded systems (more commonly the corresponding English term "embedded systems") is used.
- Examples of programming languages for use in embedded systems are C, assembler, C ++ and Java. Common to these languages is the use of a compiler, which prescribes a step-by-step approach to code development, the so-called edit-compile-load-debug cycles.
- Debugging tools called debuggers, are commonly used to track down software programming errors. Since most software development systems provide an integrated development environment for this, debuggers can change the program code relatively easily and check them on their target system with individual steps or set control points. You can use it to execute a program in a controlled manner, i.e.
- TCL is a cross-platform script programming language.
- the combination of word processing, file processing and system control functions optimizes TCL for this purpose.
- EDL tools Electronic Design Automation
- TCL uses TCL together with the graphic toolkit TK to offer a flexible and platform-independent graphical user interface. This includes, for example, ModelSim.
- Hardware and software design often begin before the system architecture is completed or even before the specification is finally finalized.
- System architects, users and customers or marketing experts jointly develop requirement definition and specification.
- the system architect uses this to develop a system of cooperating system functions as the basis for a subsequent, parallel design of hardware and Software.
- the rough architecture of the target hardware is also specified here.
- the hardware / software interface design requires the involvement of hardware and software developers.
- the integration of the hardware and software components and the test of the integrated system follows as the last step. In all phases, deviations from expected design results or changes in the specification lead to a repetition of design steps.
- a central problem in the design process is the monitoring and integration of the parallel hardware and software design. Early detection of errors requires control of consistency and correctness, which becomes more complex the more detailed the design is worked out.
- exact modeling requires adapted memory and Bus models and special simulation techniques, such as the Seamless CVS cosulator from Mentor Graphics, Wilsonville, 0-regon, USA, provide an example.
- the Seamless CVS product uses an abstract processor model that simulates instruction execution (a so-called instruction set simulator).
- instruction set simulator For the storage Access bus models are used, the / abstraction of which depends on the simultaneous access of processor and hardware. Memories that are only accessed by the processor are therefore modeled more abstractly than those in which conflicts can occur.
- the prerequisite is the availability of a library of models, which is obtained from the CAD provider or the processor manufacturer.
- a more abstract approach reduces the processor model to pure program execution on the PC or workstation and only models the interface with time behavior.
- the software version is then linked to the hardware model using a simulator-specific communication protocol that the developer must insert into the software. Only interface models are required for this modeling, which considerably simplifies the library problem.
- the time behavior is only correctly modeled on the hardware side.
- An example of such a cosimulator is the product Eagle from Synopsys, Mountain View, California, USA.
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Abstract
Description
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/562,303 US20060178863A1 (en) | 2003-06-27 | 2004-05-10 | Combining and representing signals of a hardware simulation device and elements of a program listing |
EP04731897A EP1639508A1 (de) | 2003-06-27 | 2004-05-10 | Verknüpfung und darstellung von signalen einer vorrichtung zur hardware-simulation und elementen eines listings eines programms |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10329147A DE10329147A1 (de) | 2003-06-27 | 2003-06-27 | Verknüpfung und Darstellung von Signalen einer Vorrichtung zur Hardware-Simulation und Elementen eines Listings eines Programms |
DE10329147.4 | 2003-06-27 |
Publications (1)
Publication Number | Publication Date |
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WO2005001720A1 true WO2005001720A1 (de) | 2005-01-06 |
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Application Number | Title | Priority Date | Filing Date |
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PCT/EP2004/004991 WO2005001720A1 (de) | 2003-06-27 | 2004-05-10 | Verknüpfung und darstellung von signalen einer vorrichtung zur hardware-simulation und elementen eines listings eines programms |
Country Status (4)
Country | Link |
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US (1) | US20060178863A1 (de) |
EP (1) | EP1639508A1 (de) |
DE (1) | DE10329147A1 (de) |
WO (1) | WO2005001720A1 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007128753A1 (en) * | 2006-05-03 | 2007-11-15 | International Business Machines Corporation | Method, system and program product supporting specification of signals for simulation result viewing |
Families Citing this family (2)
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US8893065B2 (en) * | 2012-07-11 | 2014-11-18 | Mentor Graphics Corporation | Biometric markers in a debugging environment |
US20160070457A1 (en) * | 2014-09-04 | 2016-03-10 | Home Box Office, Inc. | Platform-independent user interface system |
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WO2001095161A2 (en) * | 2000-06-02 | 2001-12-13 | Virtio Corporation | Method and system for virtual prototyping |
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TW421761B (en) * | 1994-04-12 | 2001-02-11 | Yokogawa Electric Corp | Verification support system |
US5768567A (en) * | 1996-05-14 | 1998-06-16 | Mentor Graphics Corporation | Optimizing hardware and software co-simulator |
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US6298320B1 (en) * | 1998-02-17 | 2001-10-02 | Applied Microsystems Corporation | System and method for testing an embedded microprocessor system containing physical and/or simulated hardware |
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2003
- 2003-06-27 DE DE10329147A patent/DE10329147A1/de not_active Withdrawn
-
2004
- 2004-05-10 US US10/562,303 patent/US20060178863A1/en not_active Abandoned
- 2004-05-10 EP EP04731897A patent/EP1639508A1/de not_active Withdrawn
- 2004-05-10 WO PCT/EP2004/004991 patent/WO2005001720A1/de active Application Filing
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WO2001095161A2 (en) * | 2000-06-02 | 2001-12-13 | Virtio Corporation | Method and system for virtual prototyping |
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WO2007128753A1 (en) * | 2006-05-03 | 2007-11-15 | International Business Machines Corporation | Method, system and program product supporting specification of signals for simulation result viewing |
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Publication number | Publication date |
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DE10329147A1 (de) | 2005-01-20 |
US20060178863A1 (en) | 2006-08-10 |
EP1639508A1 (de) | 2006-03-29 |
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