WO2004113868A2

WO2004113868A2 - Samples for atom probes and method of producing the same

Info

Publication number: WO2004113868A2
Application number: PCT/US2004/019311
Authority: WO
Inventors: Keith J. Thompson; John H. Booske
Original assignee: Wisconsin Alumni Research Foundation
Priority date: 2003-06-17
Filing date: 2004-06-16
Publication date: 2004-12-29
Also published as: WO2004113868A3

Abstract

Sample tips for atom probe analysis are obtained by defining and isolating a sample region having a long dimension along the surface of the semiconductor wafer and a width along the surface and depth into the wafer which are less than the long dimension of the sample region. A moat is formed into the wafer to at least partially surround the sample region, and the sample region is then undercut by an etching process to free the sample region from the wafer beneath it. The undercut sample region may then be removed from the rest of the wafer and processed as appropriate to be used as an atom probe in an atom probe microscope. The top surface of the sample region will contain semiconductor devices that can be analyzed utilizing the atom probe to investigate the circuit devices formed on the semiconductor wafer.

Description

SAMPLES FOR ATOM PROBES AND METHOD OF PRODUCING

THE SAME

FIELD OF THE INVENTION

[0001] This invention pertains generally to the field of microscopy, atom probes, and mass spectrometry, and particularly to the preparation and use of samples for atom probes.

BACKGROUND OF THE INVENTION

[0002] In the atom probe field ion microscope, the sample to be analyzed is formed as a tip that functions as the anode of the microscope. The electric field is increased to a point where the atoms on the surface of the sample tip are evaporated by the field. A very high electric field is created at the surface of the tip by applying a high voltage between the tip and an image screen. The tip is typically sharply pointed, with a radius of curvature at the apex of about 10 to 200 nm. Because the process of field evaporation involves ionizing the atoms, they are accelerated to the imaging screen by the applied field. The flight times of the ions from the specimen to the image screen can be used to identify the atoms by mass spectrometry. The field evaporation must be pulsed so that a definite time of departure can be determined. The standing high voltage is generally kept low enough so that the evaporation rate between pulses is negligible, and a very short duration, high voltage pulse is applied which causes evaporation of a fraction of a monolayer of atoms from the specimen's surface on each pulse. A variety of devices have been developed to carry out atom probe microscopy in this manner. [0003] To address some of the limitations of conventional atom probes, a local electrode atom probe (LEAP) has been developed which is capable of rapidly pulsed field evaporation or desorption of ions from a tip utilizing a local extraction electrode positioned closely adjacent to the tip. See U.S. Patent No. 5,440,124 to Kelly, et al. The LEAP device can be utilized as a diagnostic tool for determining the identity and location of atoms in three dimensions at the sample tip. Such sample analysis is of particular significance in the semiconductor manufacturing industry for chip diagnostic purposes; for example, in advanced CMOS and nanotechnology fabrication, device structures are so small that individual atomic interactions play a significant role in device performance. Conventional techniques cannot image the semiconductor structures on an atom by atom basis, and research and testing has been carried out with the limited data available from secondary ion mass spectrometers and without specific knowledge of the atom level interactions. The LEAP is essentially the only commercially viable tool that can image CMOS devices below 100 nm, providing three dimensional analysis of semiconductor integrated circuits to accurately determine the material composition and dimensions of the formed circuits.

[0004] To carry out LEAP analysis on an integrated circuit, a small sample of a typical region of the wafer containing circuitry (which may be test circuitry) is removed from the wafer and formed into a tip that can be utilized as an atom probe. The sample must have dimensions in the range of 50 to 200 microns in height, and lateral dimensions (the maximum width of a cross-section) in the range of 100 nm to 10 microns. The cross-section of the sample may have various geometries, e.g., square, rectangular, other polygonal shapes, or round. Optimal dimensions for the tip are a height of about 200 microns and lateral dimensions of about 200 nm. One technique that has been used to obtain samples with these dimensions is initial patterning of the (e.g., silicon) wafer with an organic photo-sensitive resist followed by a deep reactive ion etch (DRIE). The etch must remove at least 100-200 microns of silicon without removing the photoresist mask and without undercutting the silicon post that is being etched. Given a maximum resist coating of 5 microns, this requires a silicon-to-resist etch selectivity of at least 25:1 (preferably higher) and anisotropy of at least 40:1 , which is a difficult, generally time consuming, and expensive etch, requiring relatively expensive DRIE equipment. If the DRIE step does not achieve ideal dimensions (e.g., 200 nm tip diameter), the sample must then be refined utilizing a focused ion beam to smooth the sidewalls and to create a sample tip with the desired dimensions. It is also necessary that the conductivity of the sample be high enough for the electric field that is applied to the tip of the sample to ground effectively. If the conductivity is too low, the time delay (RC constant) to ground will prevent the sharp pulse necessary for efficient operation. Generally, the sample conductivity should be at least 10 S/cm and preferably 100 S/cm. One difficulty is that silicon devices typically do not have this level of conductivity throughout a depth of 100 microns into the silicon wafer. Typical devices meet this conductivity requirement in the top 200 nm to 1 micron of the silicon wafer. Beyond this depth, the conductivity falls to about 0.1 S/cm, which leads to difficulties in carrying out LEAP analysis on a sample formed of such material. Another difficulty is encountered in silicon-on-insulator (SOI) wafers. In this case, the bulk of the wafer is electrically isolated from the device regions that are to be analyzed. A sample that is taken down through the electrical isolation layer will thus have a barrier to conduction that prevents it from being used in the LEAP system. Under such circumstances, samples must be taken from wafers that are specifically prepared for atom probe analysis.

SUMMARY OF THE INVENTION

[0005] In the present invention, sample tips suitable for atom probe analysis are obtained by defining and isolating a sample region having a long dimension along the surface of a semiconductor wafer, and a width along the surface and a depth into the wafer which are less than the long dimension of the sample region on the surface. The laterally defined sample region is then undercut by an etching process to free the sample region from the wafer beneath it. The undercut removable sample region may be formed as a cantilever which is completely free of the remainder of the wafer except at one end, allowing the cantilever to be removed by breaking the junction between the sample region and the wafer. The sample region may also be formed as an island which is completely freed from the wafer after etching. The sample so removed will preferably have a length (or height) in the range of 50 to 500 microns, and lateral dimensions (a width in a direction along the surface of the wafer and a depth of the sample as cut into the wafer) in the range of 50 nm to 20 microns. Because this sample is taken from a relatively shallow depth into the wafer, it will have the relatively high conductivity found in the surface region of the semiconductor wafer, and thus is readily usable as a sample for atom probe analysis. Moreover, progressive desorption of atoms from the sample tip during atom probe analysis produces data that indicates the composition of the sample over the length of the sample along the surface of the wafer from which the sample was taken. In this manner, any changes in composition of the surface layer of the wafer can be detected. Further, because the sample is taken from a relatively shallow surface layer, the sample obtained in this manner is not affected by the insulating barrier layers found in SOI wafers.

[0006] The invention can be carried out utilizing conventional semiconductor processing techniques using relatively inexpensive conventional photoresists and liquid etchants. In an exemplary process for carrying out the invention, the wafer to be analyzed is coated with a photoresist which is exposed using a mask, leaving one or more sample areas in which a sample region is coated with the photoresist, while areas around the sample region have the photoresist removed. The photoresist may also remain covering a section of wafer adjacent to the photoresist that covers the intended sample region. An etchant, for example, a wet etchant, is then applied which etches the semiconductor (e.g., silicon) at all areas not covered by the photoresist down to a depth somewhat greater than the desired depth or thickness of the sample. This etch results in a depression or "moat" which partially or entirely surrounds the sample region. For silicon-on-insulator wafers, the etch may extend entirely through the top silicon layer down to the insulating layer (e.g., Siθ2 ) at which the etch naturally terminates. This moat etch step may then be followed by another etch using a liquid etchant which etches the SiO₂ or other insulating layer material but does not etch the silicon or other semiconductor. This etch will cut into the insulating layer under the sample region so as to free the sample region from the insulating layer, with the sample region entirely freed from the wafer or extending as a cantilever from its junction to the remainder of the wafer. Where the sample region remains attached to the wafer as a cantilever, it may then be physically broken away from the wafer at the junction to provide a sample that can be utilized for further processing as an atom probe. For wafers which do not have an insulating layer, after carrying out the moat etch to define the sample region, the sidewalls of the sample region and the surrounding sidewalls may be covered by an etch resist, such as a polymer, with the floor of the moat left exposed. Another liquid etch step may then be carried out which etches down into the floor of the moat and under the sample region to the point where the sample region is completely undercut from the remainder of the wafer, entirely separated from the wafer or, e.g., as a cantilever extending out from the junction to one of the walls of the moat. The cantilever sample region may then be broken away from the rest of the wafer at the junction. For some wafers, the top layer of the wafer may have a heavy concentration of dopant which renders it etch resistant while deeper layers of the wafer are less heavily doped and thus more vulnerable to certain etchants. Applying an etchant to the moat will then result in etching of the deeper material of the sample region until it is cut completely through, leaving the more heavily doped and etch resistant top layer as a freed sample region extending outwardly from a junction at a sidewall of the moat.

[0007] The resulting sample obtained from an integrated circuit wafer is a thin elongated section of semiconductor having a top surface lateral dimensions (width along the top surface and a depth) in the range of about 50 nm to 20 microns and a length or height in the range of 50 to 500 microns, with a top surface corresponding to the top surface of the wafer and having circuit structures formed therein. [0008] Further objects, features and advantages of the invention will be apparent from the following detailed description when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In the drawings:

[0010] Fig. 1 is a simplified cross-sectional view of a typical silicon-on-insulator (SOI) wafer.

[0011] Fig. 2 is a top view of the wafer of Fig. 1 showing sample areas defined therein.

[0012] Fig. 3 is a top view of one of the sample areas of the wafer of Fig. 2 with photoresist defining a sample region.

[0013] Fig. 4 is a simplified perspective view illustrating the

\ isolation of the sample region after the step of etching.

[0014] Fig. 5 is a simplified cross-sectional view through the sample region of Fig. 4 illustrating the relative dimensions of the sample region and the surrounding etched moat.

[0015] Fig. 6 is a top view of the sample region of Fig. 4 illustratively shown connected to a handle region.

[0016] Fig. 7 is a cross-sectional view illustrating application of an etchant that etches the insulating layer of the SOI wafer of Fig. 1 without affecting the semiconductor of the sample region. [0017] Fig. 8 is a simplified perspective view illustrating the fully isolated sample region after etching, with the sample region extending as a cantilever from a junction to one of the walls of the etch moat.

[0018] Fig. 9 is a simplified cross-sectional view of a semiconductor wafer with a device region formed on a bulk silicon substrate.

[0019] Fig. 1 0 is a simplified cross sectional view through the sample region formed in the wafer of Fig. 9.

[0020] Fig. 1 1 is a cross sectional view as Fig. 1 0 with a photoresist deposited on the top of the sample region and a protective polymer coating deposited on the sidewalls of the etch moat.

[0021] Fig. 1 2 is a cross-section as in Fig. 1 1 after the step of removing the protective polymer coating on the floor of the etch moat by an anisotropic sputter etch.

[0022] Fig. 1 3 is a cross-sectional view as in Fig. 1 2 showing the effect of applying an etchant to etch through the floor of the etch moat and under the sample region.

[0023] Fig. 14 is a simplified cross-sectional view of a wafer with a bulk silicon substrate, illustrating another etching process in which an uppermost layer of the device region is heavily doped and resists etching, while more lightly doped silicon under the sample region is attacked by the etchant to separate the sample region from the remainder of the wafer. DETAILED DESCRIPTION OF THE INVENTION

[0024] With reference to the drawings, a first exemplary process for forming sample tips taken from semiconductor wafers is illustrated with respect to Figs. 1 -8. Although the invention will be described with reference to a silicon wafer for illustration, the invention may utilize other semiconductors, e.g., GaAs, SiGe, etc. This process is carried out on a wafer with a bulk silicon substrate 31 having a relatively low conductivity (typically less than 0.1 S/cm), a silicon dioxide insulating layer 32, and a silicon layer 34 in which semiconductor devices are formed. The device region 34 has a relatively high conductivity, typically greater than 10 S/cm. As illustrated in the top view of Fig. 2, initial processing involves coating the wafer top surface 35 with a photoresist, patterning the photoresist utilizing a mask and light in a conventional photolithography process, and developing the photoresist to leave the surface 35 of the device region of the wafer covered with photoresist 36 except at one or more sample areas 37. A typical sample area 37, shown in more detail in Fig. 3, has an open area 38, exposing the surface 35, within which is a photoresist pattern 40. The illustrative photoresist pattern 40 shown in Fig. 3 includes a section of photoresist 41 that covers the desired sample region and a section of photoresist 42 which covers a handle region. In addition to conventional photoresists, other materials, such as Si₃N₄, Al, Siθ2, and so forth, may be used to protect the silicon in the sample region. The sample areas 37 may be located anywhere on the wafer where it is desired to analyze the circuit devices that are formed into the surface 35 of the device region 34. Typical dimensions for the section 41 of photoresist that covers the sample region may range from 50 to 500 microns long and 50 nm to 20 microns wide. The handle region is optional and may be useful in aiding in the break-off process. If the handle region is not used, the photoresist region 41 may be an island completely isolated from the rest of the photoresist, or it may extend from the body 36 of the photoresist that covers the remainder of the surface of the wafer.

[0025] A silicon etch (e.g., an anisotropic etch) may then be utilized to etch the areas of the wafer that are not covered by photoresist to define an etch moat 44, as illustrated in Fig. 4, which completely or at least partially surrounds the elongated sample region 45 which was under the photoresist region 41 . The etch moat 44 has a floor 46 which preferably extends to or into the insulating layer 32. The sample region 45 has upright sidewalls 48 and the etch moat 44 has lateral sidewalls 50. As illustrated in Fig. 6, the sample region 45 may be joined to a handle region 52 at a junction 53, or it may simply be joined directly to the rest of the wafer where the handle region 52 is not used so that the etch moat 44 only extends around the sample region 45. The sample region 45 may also be formed as an island completely surrounded by the moat 44. An example of an anisotropic silicon etch system that may be used is a chlorine inductively coupled plasma. Any other suitable etch may also be utilized. For example only, these etches include the Bosch passivation/etch process, an SFβ plasma, a CxFy plasma, a Br etch, or an NF3 plasma, and various combinations. Numerous wet chemicals can be used to define the etch moat. While wet chemistry is typically not as effective as plasma chemistry, the cost of wet etching can be significantly lower. It is preferable that the etching be as anisotropic as possible. [0026] As illustrated in Fig. 7, to separate the sample region 45 from the underlying layer 32, an isotropic SiO₂ etch is utilized that etches the SiO₂ layer much more rapidly than Si. An example of such an etchant is an HF solution, which may be straight HF, HF diluted with H2O, or HF buffered or mixed in any reasonable combination to achieve sufficient Siθ2 etching. Other wet etch solutions or plasmas can be used to etch Siθ2, but HF will generally be the most efficient. After etching, the sample region 45 is freed from the wafer material beneath it, completely separated from the wafer or extending as a cantilever from the junction 53 to the rest of the wafer as illustrated in Fig. 8. Where the sample region is formed as an island by itself, or attached to a handle region that is isolated from the rest of the wafer, the samples are freed to float in the etchant and may be recovered using a strainer or mesh basket with sufficiently small pores, followed by rinsing and baking. Any protective coatings on the sample 45 can be removed using a solvent such as acetone, wet chemistry such as a piranha etch (H₂SO₄: H₂U2), or an oxygen plasma ash. A cantilever sample may be removed from the wafer using a micromanipulator or other mechanism to grasp the sample 45 and break it from the wafer, preferably at the joint 53. Once the sample is freed, it can be further processed and sharpened in a conventional manner for use in the atom probe.

[0027] The invention may also be carried out with wafers which do not have an insulating layer between the device region and the bulk wafer, as illustrated in Fig. 9 in which the silicon substrate 31 has a low conductivity, typically less than 0.1 S/cm, and the device region 34 on the substrate 31 has a conductivity typically greater than 10 S/cm. The first step is to pattern the wafer to form the sample areas 37 and the photoresist sections 41 covering the sample regions, as shown and discussed above with respect to Figs. 2 and 3. An anisotropic silicon etch is then carried out to define the patterned area as illustrated in Fig. 10. The depth of the moat 44 is preferably sufficiently deep to clear the device layer 34, and the moat is preferably etched a few microns into the bulk silicon 31 . Such etching may be carried out with a chlorine inductively coupled plasma. Other plasmas may be utilized as discussed above with respect to the etching of the moat illustrated in Fig. 5.

[0028] With the vertical dimensions of the sample region sidewalls 48 defined, the silicon from beneath the sample region 45 must be removed to allow it to be released from the rest of the wafer. However, etchants that attack the bulk silicon 31 under the sample region 45 will also attack the silicon in the sample region itself. Various techniques may be utilized to protect the sample sidewalls 48 from attack. One technique, illustrated in Figs. 1 1 -1 2, is to deposit a polymer coating 55 that initially covers the sample sidewalls 48, the moat sidewalls 50, and the moat bottom wall or floor 46. The top of the sample region 45 is covered by a photoresist 56. Non-polymer coatings may be utilized, rather than the polymer layer 55, examples of which are metal, oxide or nitride layers. The coating 55 in the areas in which it covers the floor 46 of the etch moat are then removed, for example, by utilizing a light anisotropic sputter etch. This directional removal process clears the polymer layer 55 from the bottom 46 of the etch moat with minimal effect on the polymer on the sidewalls 48, as illustrated in Fig. 1 3. The sample region may then be freed from the underlying bulk silicon with an isotropic silicon etch. Various etches may be utilized. Examples include SFβ or NF₃ plasma etches, which may include various combinations of additives. However, wet etching is preferred because of its low cost and simple application. A variety of wet etch chemistries are available. Examples are Nitric acid/HF solutions that oxidize the silicon and then strip the oxide. XeF2 gas may be utilized to break into F radicals. These F radicals actively attack Si. Such gases are expensive but are highly effective for isotropically etching silicon. All of these etches will etch up into the sample region 45 to some extent. Thus, it is preferable that the depth of the etch moat be several microns deeper than the desired sample thickness. Any roughness in the surface of the sample after it is removed can be cleaned, for example, using a focused ion beam (FIB) process. After etching, the sample is freed from the wafer or extends in a cantilever fashion from an etch moat sidewall 50 in the same manner illustrated in Fig. 8. Any protective coatings on the sample can be removed using a solvent such as acetone, a wet chemistry such as a piranha etch (H2SO₄; H2O2), or an oxygen plasma ash. The cantilever sample can be broken away from the wafer utilizing an micromanipulator or other mechanism.

[0029] Another process in accordance with the invention that may be utilized with a wafer having a silicon substrate with a heavily doped device region 34 on it (as shown in Fig. 9), carries out initial patterning and etching as discussed above to provide the isolated sample region 45 illustrated in cross-section in Fig. 1 4. If the device region 34 is very heavily doped, e.g., a highly doped p-type layer, the doped layer may be more resistant to certain etches than the undoped or lightly doped silicon of the bulk substrate 31 . For example, in many finished wafers, the boron dopant concentration in the layer 34 may often be greater than 10¹⁸/cm³. Several etch chemistries, for example KOH, selectively etch undoped or lightly doped silicon over highly doped p-type layers. As a result, as illustrated in Fig. 1 6, the etchant will etch into the floor 46 of the etch moat and into those portions 60 of the sidewalls 48 of the sample region 45 that are below the highly doped device region layer 34. Because of this differential etching, it is not necessary to coat the sample region sidewalls. Eventually, the etching completely etches through the portion of the sample region beneath the layer 34, freeing it from the bulk silicon and leaving it as a free floating sample or as a cantilever as illustrated in Fig. 8. Protective coatings on the sample can now be removed, as discussed above, and the freed sample or the cantilever sample, after being broken away from the remainder of the wafer, can then be further processed into a suitable atom probe tip.

[0030] It is understood that the invention is not confined to the particular embodiments set forth herein as illustrative, but embraces all such forms thereof as come within the scope of the following claims.

Claims

What is claimed is: 1 . A method of obtaining a sample tip for use in an atom probe from a semiconductor wafer having a bulk substrate and a device region with a top surface in which semiconductor devices are formed, comprising: (a) protecting a sample region of the surface of the wafer and etching a moat at least partially around the sample region into at least the device region, the sample region having a long dimension along the surface of the wafer, and the sample region having a width along the surface of the wafer and a depth into the wafer which are less than the long dimension of the sample region on the surface; (b) etching the wafer through the moat under the sample region to free the sample region from the wafer beneath it; and (c) removing the sample region from the wafer.

2. The method of Claim 1 wherein the moat is etched partially around the sample region to leave the sample region joined to the wafer at a junction at one end of the sample region, wherein after etching under the sample region the sample region remains attached to the wafer at the junction, and wherein the step of removing the sample region from the wafer includes grasping the sample region and breaking it from the wafer at the junction to the wafer.

3. The method of Claim 1 wherein the wafer includes an insulating layer between the bulk semiconductor substrate and the device region, and wherein the step of etching the moat about the device region includes applying an etchant to the surface of the wafer that will etch the material of the device region more readily than the material of the insulting layer and terminating the moat etch at the insulating layer, and wherein the step of etching under the sample region includes applying an etchant to the moat that preferentially etches the material of the insulating layer more readily than it etches the material of the device region so that the material of the insulating layer under the sample region is etched away to free the sample region from the wafer beneath it.

4. The method of Claim 1 wherein after etching the etch moat, lateral sidewalls of the sample region are coated with a material that will resist etching, and then applying art etchant to the etch moat that etches into the wafer under the later sidewalls of the sample region that are covered by the protective coating to etch away the material of the wafer under the sample region to free the sample region from the wafer beneath it.

5. The method of Claim 4 wherein in the step of coating the sidewalls of the sample region, the floor of the etch moat is also coated with the protective coating, and including the additional step of removing the protective coating on the floor of the etch moat while leaving the protective coating on at least the sidewalls of the sample region.

6. The method of Claim 1 wherein the sample region has a length in the long direction along the surface of the wafer in the range of 50 to 500 microns and a width along the surface and a depth into the wafer in the range of 50 nm to 20 microns.

7. The method of Claim 1 wherein the step of etching a moat around a sample region includes photolithographically patterning a layer of photoresist on the top surface of the wafer to leave at least one sample area which includes a section of photoresist covering the area of the sample region to be formed, with the surface of the wafer exposed at least partially around the photoresist covering the area of the sample region, and then applying an etch to etch the areas of the wafer that are not covered by the photoresist to define the etch moat that at least partially surrounds the elongated sample region that is covered by the photoresist.

8. The method of Claim 7 wherein the section of photoresist which covers the desired sample region has a length in the range of 50 to 500 microns and a width in the range of 50 nm to 20 microns.

9. The method of Claim 7 wherein in the step of patterning the photoresist in the sample area a section of photoresist is formed in the sample area that is wider than the width of the section of photoresist covering the desired sample region and, after applying an etchant to the areas of the wafer surface not covered by photoresist, a handle region is formed partially surrounded by the etch moat and from which the sample region extends.

10. The method of Claim 1 wherein the bulk substrate and the device region of the wafer are formed of silicon.

1 1 . The method of Claim 1 wherein the device region has a conductivity greater than 1 0 S/cm.

12. The method of Claim 1 wherein at least a surface layer of the device region has a very high concentration of dopant that renders it resistant to etches that readily etch the semiconductor of the substrate, and wherein the step of etching under the sample region includes applying a wet etchant into the moat into which the heavily doped device region is resistant, to etch under the device region through the less heavily doped material of the wafer to free the device region from the wafer beneath it.

13. The method of Claim 12 wherein a layer of the device region has a dopant concentration of at least 10¹⁸/cm³.

14. The method of Claim 7 wherein multiple sample areas are defined on the surface of the wafer so that sample regions are formed at multiple selected positions in the wafer.

15. A method of obtaining a sample tip for use in an atom probe from a semiconductor wafer having a bulk substrate and a device region with a top surface in which semiconductor devices are formed, comprising: (a) protecting a sample region of the surface of the wafer and etching a moat at least partially around the sample region into at least the device region, the sample region having a long dimension along the surface of the wafer, the sample region having a width along the surface of the wafer and a depth into the wafer which are less than the long dimension of the sample region on the surface wherein the moat is etched partially around the sample region to leave the sample region adjoined to the wafer at a junction at one end of the sample region; (b) etching the wafer through the moat under the sample region to free the sample region from the wafer beneath it wherein after etching under the sample region the sample region remains attached to the wafer at the junction; and (c) removing the sample region from the wafer by grasping the sample region and breaking it from the wafer at the junction to the wafer.

1 6. The method of Claim 1 5 wherein the wafer includes an insulating layer between the bulk semiconductor substrate and the device region, and wherein the step of etching the moat about the device region includes applying an etchant to the surface of the wafer that will etch the material of the device region more readily than the material of the insulting layer and terminating the moat etch at the insulating layer, and wherein the step of etching under the sample region includes applying an etchant to the moat that preferentially etches the material of the insulating layer more readily than it etches the material of the device region so that the material of the insulating layer under the sample region is etched away to free the sample region from the wafer beneath it.

1 7. The method of Claim 1 5 wherein after etching the etch moat, lateral sidewalls of the sample region are coated with a material that will resist etching, and then applying an etchant to the etch moat that etches into the wafer under the later sidewalls of the sample region that are covered by the protective coating to etch away the material of the wafer under the sample region to free the sample region from the wafer beneath it.

1 8. The method of Claim 1 7 wherein in the step of coating the sidewalls of the sample region, the floor of the etch moat is also coated with the protective coating, and including the additional step of removing the protective coating on the floor of the etch moat while leaving the protective coating on at least the sidewalls of the sample region.

19. The method of Claim 15 wherein the sample region has a length in the long direction along the surface of the wafer in the range of 50 to 500 microns and a width along the surface and a depth into the wafer in the range of 50 nm to 20 microns.

20. The method of Claim 15 wherein the step of etching a moat around a sample region includes photolithographically patterning a layer of photoresist on the top surface of the wafer to leave at least one sample area which includes a section of photoresist covering the area of the sample region to be formed with the surface of the wafer exposed at least partially around the photoresist covering the area of the sample region, and then applying an etch to etch the areas of the wafer that are not covered by the photoresist to define the etch moat that at least partially surrounds the elongated sample region that is covered by the photoresist.

21 . The method of Claim 20 wherein the section of photoresist which covers the desired sample region has a length in the range of 50 to 500 microns and a width in the range of 50 nm to 20 microns.

22. The method of Claim 20 wherein in the step of patterning the photoresist in the sample area a section of photoresist is formed in the sample area that is wider than the width of the section of photoresist covering the desired sample region and, after applying an etchant to the areas of the wafer surface not covered by photoresist, a handle region is formed partially surrounded by the etch moat and from which the sample region extends.

23. The method of Claim 15 wherein the bulk substrate and the device region of the wafer are formed of silicon.

24. The method of Claim 15 wherein the device region has a conductivity greater than 10 S/cm.

25. The method of Claim 15 wherein at least a surface layer of the device region has a very high concentration of dopant that renders it resistant to etches that readily etch the semiconductor of the substrate, and wherein the step of etching under the sample region includes applying a wet etchant into the moat to which the heavily doped device region is resistant to etch under the device region through the less heavily doped material of the wafer to free the device region from the wafer beneath it.

26. The method of Claim 25 wherein a layer of the device region has a dopant concentration of at least 10¹⁸/cm³.

27. The method of Claim 20 wherein multiple sample areas are defined on the surface of the wafer so that sample regions are formed at multiple selected positions in the wafer.

28. A sample from a semiconductor wafer for use as an atom probe formed by the method of Claim 1 .

29. A sample from a semiconductor wafer for use as an atom probe formed by the method of Claim 15.