WO2004112041A2 - Low power manager for standby operation - Google Patents
Low power manager for standby operation Download PDFInfo
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- WO2004112041A2 WO2004112041A2 PCT/EP2004/050867 EP2004050867W WO2004112041A2 WO 2004112041 A2 WO2004112041 A2 WO 2004112041A2 EP 2004050867 W EP2004050867 W EP 2004050867W WO 2004112041 A2 WO2004112041 A2 WO 2004112041A2
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- pull
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-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
Definitions
- All of the memory cells connected to a common word line are also connected to a common return line to which is connected a single resistor and a single large MOS or FET device.
- the large MOS device is turned on during the active operation of the memory array (during write and read operations) and is turned off during the standby operation of the memory array.
- the resistor functions to insure that some current flow takes place, during the standby operation, from all the memory cells connected to the common return line in order to maintain the data states ("1" or "0") in each of the memory cells.”
- U.S. patent No. 6,236,617 of Hsu et al . entitled "High Performance CMOS Word-line Driver” describes wordline DRAM array having n groups of m wordlines, in which one group is driven by a group decoder circuit (having a voltage swing between ground and a circuit high voltage and one driver circuit in each group is exposed to a boosted wordline high voltage greater than the circuit high voltage, in which the wordline driver circuits have an output stage comprising a standard NFET in series with a high threshold voltage PFET.
- the wordline driver circuits have an output stage comprising a standard NFET in series with a high threshold voltage PFET.
- 1024 wordline drivers and a row (group) decoder "100" which drives the gates of a selected group of four of those wordline drivers.
- a wordline selector "200" provides an input to the source of a PFET transistors connected in series to a parallel pair of NFET transistors , one of which has its gate connected to the row (group) decoder and the other one of which has its gate connected to a restore circuit.
- the driver passes voltage Vpp on to a wordline, since WLDV connected to that driver is at Vpp. However, for the remaining (m-1) drivers in that group, the WLDV signals are kept at Vm (e.g. 0.7V) level and even though the gates of those drivers are pulled low, the high Vt (about -1.2V) of the PFET device, will not prevent the output of those drivers from being maintained by the restore circuit at a negative level (or -0.5V) .
- the restore circuit opens a path between a terminal and the wordline to restore the quiescent state on the wordline block.
- “Floating Wordline Using A Dynamic Row Decoder And Bitline VDD Precharge” describes a "wordline driver D consisting of a pullup pMOS PU, a pull-down MOS PD, and a second nMOS pull-down device K which is called a killer device. This killer device is used to deselect the half-selected wordlines so they will not be floating.”
- Dennard et al states further that "each decoded output from a level shifter is tied to a group of four wordline drivers . One of the four wordline drivers is selected by decoding the sources of the pull-up pMOS devices as well as the gates of the killer devices". Referring to Second Sense Amplifiers (SSA) 11, Hanson et al. U.S.
- patent No. 6,115,308 entitled “Sense Amplifier and Method of Using the Same with Pipelined Read, Restore and Write Operations” describes a second sense amplifier memory device which may have a sense amplifier circuit and two drivers connected to the sense amplifier circuit. Two data bus lines may be connected to the sense amplifier circuit to receive data signals. A first equalize signal and a second equalize signal are applied to the sense amplifier circuit to allow the sense amplifier circuit to receive the data signals across the data bus lines. A switch signal is applied to the sense amplifier circuit to connect the data bus lines to a read data bus. The state of the first equalize signal is changed so that the data bus lines either receive new data or the data bus lines are equalized to a predetermined voltage while the data is on the read data bus and is capable of being read.
- the row path is comprised of three key blocks; the RDEC (Row address DECoder) block 14, the RSEL (Row SELector level shifter as in Dennard et al . ) block 16, and the row or WLDRV (WordLine DRiVer) block 18 in which there are 128, i.e. (X+l) , wordline blocks WLDRV, e.g.
- wordline blocks DRl to DR512 for control codes WLDRV ⁇ 0>, WLDRV ⁇ 1>, WLDRV ⁇ 2>, WLDRV ⁇ 3>, ...WLDRV ⁇ X> where X 511.
- the RDEC block 14 and the RSEL block 16 perform a process of hierarchical decoding. First, the RDEC block 14 enables the selection of four (4) wordlines out of the total number of 512 wordlines WLDRV ⁇ 0>, WLDRV ⁇ 1>,
- the RDEC performs a 1/128 decode.
- the RSEL block 16 performs the final 1/4 decode with a two-bit predecoder (not shown) to activate one (1) of the four WLDRV blocks activated by the RDEC block 14 with a signal on one of the WLDV lines 20A-20D.
- IB can employ the two-bit predecoder (not shown) to activate line 2OA, which is one of the four wordline drivers 20A-20D
- the signal on WLDECN bus line performs the 1/128 decode, enabling four WLDRVs with horizontal buses.
- the RDEC block 14 sends a signal on lines WLDEC-I to WLDEC-128 to select four WLDRV units.
- line WLDEC-I line 15-1 can simultaneously energize four wordline drivers WLDRV ⁇ 0:3>, i.e. WLDRV ⁇ 0>, WLDRV ⁇ 1>, WLDRV ⁇ 2>, WLDRV ⁇ 3>) from the set of the 512 wordlines with the signal on the WLDECN (WordLine DECoder Signal @ low) line to perform a 1/32 decode.
- WLDRV ⁇ 0:3> i.e. WLDRV ⁇ 0>, WLDRV ⁇ 1>, WLDRV ⁇ 2>, WLDRV ⁇ 3>
- WLDECN-128 line 15-128 can energize the last four wordline drivers WLDRV ⁇ 508> driver (not shown) , WLDRV ⁇ 509> driver (not shown) , WLDRV ⁇ 510> driver (not shown) , and WLDRV ⁇ 511> driver DR512 which is the only one of the four shown in FIG. IB for convenience of illustration.
- the RSEL block 16 decodes a one (1) out of the four (4) signals from the data processing system (not shown) to select one of the four wordlines enabled by the RDEC block 14.
- the RSEL block 16 then encodes signals on vertical Word Line DriVe (WLDV) lines 20A-20D to enable H of the Word Line DriVe (WLDRV) blocks with signals on WLDV lines 20A-20D.
- the output of the RSEL block , H of the WLDV bus lines 20A-20D will be active while at the same time H of the Word Line ReSeT (WLRST) bus lines 22A-22D will be activated to ensure the deactivation of the remaining H of the wordline blocks WLDRV.
- WLRST Word Line ReSeT
- the non-activated wordlines are held low by three (3) out of four (4) of the Wordline Reset signals (WLRST ⁇ 0:3>) on wordline bus lines 22A-22D.
- WLRST ⁇ 0:3> the Wordline Reset signals
- FIG. 2 shows a portion 18' of the WLDRV block 18' of FIG. IB which includes two of the prior art wordline driver circuits DRl and DR2 plus BL ⁇ 0> bitline 28, and array transistors AO/Al with related array capacitors C1/C2.
- Block DRl includes pull-up PFET transistor Pl, pull-down NFET transistor Nl and killer NFET transistor N2.
- pull-up PFET Pl the source is connected to WLDV ⁇ 0> line 2OA and the drain is connected to node B2, as are the drains of pull-down NFET Nl and killer NFET N2.
- the gates of transistors Pl and Nl are connected via node Bl to WLDECN line 15-1.
- the gate of NFET N2 is connected to WLRST ⁇ 0> line 22A.
- the sources of transistors Nl and N2 are connected to ground (reference potential) .
- drains of transistors Pl, Nl and N2 are connected via node B2 to the wordline .output WL ⁇ 0> line 26-1 which connects to the gate of NFET array transistor AO which has its source connected to capacitor Cl (connected to ground) and its drain connected to node B5, which is the BL ⁇ 0> line 28.
- Block DR2 includes pull-up PFET transistor P2 and pull-down NFET transistor N3 and killer NFET transistor N4.
- PFET P2 the source is connected to WLDV ⁇ 1> line 2OB and the drain is connected to node B4, as are the drains of transistors N3 and N4.
- the gates of transistors P2 and N3 are connected via node B3 to WLDECN line 15-1.
- the gate of transistor N4 is connected to WLRST ⁇ 1> line 22B.
- the sources of transistors N3 and N4 are connected to ground (reference potential).
- the drains of transistors P2, N3 and N4 are connected via node B4 to the wordline output WL ⁇ 1> line 26-2 which connects to the gate of NFET array transistor Al which has its source connected to capacitor C2 (connected to ground) and its drain like the drain of NFET array transistor AO is also connected to node B5, which is the BL ⁇ 0> line 28.
- Examples of voltages applied to the circuit are VDD which has a value of about 1.2V, Vpp which varies between a value of OV and about 1.5V to 2.5V and WLRST which varies between about OV and VDD, i.e. 1.2V.
- the value of WLDV ⁇ 0> is shown to be VPP (e.g. 2.5V) after rising from OV.
- the value of WLDV ⁇ 1> is shown to be OV after falling from VPP (e.g. 2.5V) .
- a two-bit predecoder (not shown is used to activate line 2OA which is one of the four wordline drivers 20A-20D.
- the source of the pMOS pull-up device Pl is tied to VPP, while the gate of the killer device is tied to Ground on line 22A.
- the sources of the other three pMOS pullup devices in drivers DRl, DR2, DR3 and DR4 stay at ground, and the gates of the other three killer devices stay at VDD.
- This second level decoding is applied to all the wordline drivers in the first level decoded group of four.
- the signal on the shared WLDECN line 15-1 from the RDEC block 14 in FIG IB is low, preventing NFET transistors Nl in driver DRl WLDRV ⁇ 0> and N3 in WLDRV ⁇ 1> in driver DR2 from conducting.
- the input for code WLDV ⁇ 1> on line 2OB to the source circuit of PFET P2 in driver DR2 will be low and for the gate terminal of NFET N4 single code WLRST ⁇ 1> in driver DR2 the value will be high, preventing PFET P2 from conducting and enabling NFET N4 in driver DR2 to conduct, respectively.
- the input WLDV ⁇ 0> on the source terminal of PFET Pl is high enabling PFET Pl to conduct and charge the WL ⁇ 0> wordline 26-1, up to VPP, its boosted logic level ⁇ l' .
- the reset value on bus 22B for code WLRST ⁇ 1> would be high on the gate of NFET N4, thereby enabling NFET N4 to conduct and to discharge the wordline 26-2, WL ⁇ 1> up to ground, its logic level ⁇ 0' .
- the activated WL ⁇ 0> wordline 26-1 drives the gate of the array transistor PFET Al to read data from or to write data into the memory element.
- a memory system which includes a memory array with a plurality of wordline drivers included in a group of wordline drivers with n wordline drivers in a group.
- a row address decoder block has an output connected to each of the wordline drivers in the group of wordline drivers .
- a power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) are connected to the wordline drivers to lower power consumption thereof as a function of the power down input signal .
- WLPWRDN power down input signal
- WLPDN wordline power down output
- the power management circuit includes a plurality of FET devices, an inverter and a negative bias voltage, one of the FET devices connecting a reference potential to the WLPDN output in the absence of a WLPWRDN signal, and another FET connecting a negative voltage WLNEG to the WLPDN output in the presence of a WLPWRDN signal.
- the standby power management circuit includes an input terminal and an output terminal, and the output terminal is connected to vary bias to said driver circuits in the wordline driver to vary operation thereof between full power current operation and reduced standby current operation.
- the power management circuit includes a plurality of FET devices, an inverter and a negative bias voltage. One of the FET devices connecting a reference potential to the WLPDN output in the absence of a WLPWRDN signal and another FET connecting a negative voltage WLNEG to the WLPDN output in the presence of a WLPWRDN signal.
- a standby power management circuit includes an input terminal and an output terminal.
- Switching means are provided including MOSFET devices for switching between a positive output and a negative output signal at said output terminal as a function of an input on said input terminal.
- the switching means include at least one inverter and NMOS and PMOS devices.
- the input terminal is connected through an inverter to the gate of a pull-up transistor.
- the output terminal is connected in series with a pass through transistor.
- a pull down FET transistor having a source/drain circuit is connected in series with a source of negative potential coupled to said output, and control FET transistors are connected to switch the gate of the pull down FET transistor as a function of a power down signal applied to the input .
- the present invention uses a logic device for the array transistor to boost the array performance.
- the problem caused by using this device is that the cost of the additional performance is standby power of the device is IOOOX (pA) that of the DRAM-based array transistor (fA) . Therefore, a need exists for a means to manage the standby power of the logic-array device and the memory array constructed with those devices .
- FIGS. IA and IB describe a prior art DRAM memory configuration with the problem or achieve an of excessive consumption of power during standby operation.
- FIG. 2 shows a portion of the prior art WLDRV block of FIG. IB which includes two of the prior art wordline driver circuits plus A BL ⁇ 0> bitline , and array transistors with related array capacitors.
- FIG. 3 illustrates a modified row architecture in accordance with this invention, which provides a means for providing the two operating modes including a high-performance mode or a low-power mode.
- FIG. 4 shows a modification of the circuit diagram of FIG. 2 in accordance with this invention which demonstrates incorporation therewith of an embodiment of the Standby Power Management (SPM) block of FIG. 3.
- SPM Standby Power Management
- FIG. 5 illustrates an embodiment of the SPM power management block in accordance with this invention comprising a circuit incorporating MOSFET devices including pull-up PFET transistors, pull-down NFET transistors, a pass-through NFET transistor and an inverter.
- MOSFET devices including pull-up PFET transistors, pull-down NFET transistors, a pass-through NFET transistor and an inverter.
- FIG. 6 illustrates a modification of FIG.5 in which a SPM' power management block comprising a circuit incorporating MOSFET devices including PFET transistors, NFET transistors and two inverters.
- the present invention provides a means for managing the standby power of the type of logic-array device shown in FIG. 2.
- a standby power manager is provided that will modulate the bias of the array device depending on whether the memory array needs to be operated in two operating modes including a high-performance mode or a low-power mode.
- FIG. 3 illustrates a modified row architecture in accordance with this invention, which provides a means for providing the two operating modes including a high-performance mode or a low-power mode.
- the architecture is comprised of four other blocks; the row address decoder block 14, the row selector block 16, the wordline drivers block DR, and the standby power management block 40.
- the Standby Power Management (SPM) block 40 generates a WLPDN output on line 32 which modulates the bias point of the array transistor and the logic level ⁇ 0' of the outputs of the row decoder 14 and wordline driver blocks DR.
- SPM Standby Power Management
- the logic level ⁇ 0' of the outputs 15-1 to 15-128 of the row decoder 14 and wordline driver blocks DR lines 26-1 to 26-512 is ground. This maintains a bias upon the array the- transistor that yields the highest performance.
- the logic level ⁇ 0' of the outputs of the row decoder 14 and wordline driver blocks DR is a voltage that is negative with respect to ground. Depending upon the technology this voltage can range from -0.2V to -1.5V. This bias condition reduces the array standby current by three orders of magnitude (from
- FIG. 4 shows a modification of the circuit diagram of FIG. 2, which demonstrates incorporation therewith of an embodiment of the Standby Power Management (SPM) block 40 of FIG. 3.
- SPM Standby Power Management
- the SPM block 40 is interfaced with two (2) wordline driver circuits DRl and DR2 for purposes of illustration of an implementation which would include the full array of say 512 driver circuits DR1-DR512 as indicated in FIG. IB.
- DRl and DR2 the difference in the drivers DRl and DR2 from FIG.
- FIG. 5 illustrates an embodiment of the SPM power management block 40 comprising a circuit incorporating MOSFET devices including pull-up PFET transistors P3 and P4, pull-down NFET transistors N5, N6, and N8, pass-through NFET transistor N7 and an inverter II.
- WLPDN line 36 is connected to the gate of pull-up PFET P3 and the input of inverter II.
- the sources of pull-up PFET transistors P3 and P4 are connected via node BlO to positive voltage VDD, e.g. about 1.2V.
- the drain of pull-up PFET P3 is connected through node B8 to the gate of pull-down NFET N5 and the drain of pull-down NFET N6.
- the drains of pull-up PFET P4 and pull-down NFET N5 as well as the source of pass-through NFET N7 and the gate of NFET N6 are connected via node B7 to the gate of pull-down NFET N8.
- the sources of pull-down NFET transistors N5 and N6 are connected through node BO 9 to WordLine NEGative voltage WLNEG, e.g. from about. -0.2 to about -1.0V.
- the drain of pass-through NFET N7 and the source of pull-down NFET N8 are connected via node B6 to the Wordline Power Down Bus (WLPDN) line 32.
- the operation of the SPM block 40 is as follows.
- the input to the circuit, WLPWRDN on line 36 is high or logic level ⁇ l' .
- Pull-up PFET transistor P3 will be off, the output of inverter Il having its input connected to WLPWRDN line 36 and its output connected to node B12 will be logic level ⁇ 0' .
- the gates of pull-up PFET transistor P4 and of pass-through NFET transistor N7 are connected to node B12.
- the inverter Il which is at logic level ⁇ 0' produces a low potential on node B12 which prevents pass-through NFET N7 from conducting.
- the input to the circuit, WLPWRDN is low or logic level ⁇ 0' .
- Pull-up PFET transistor P3 will conduct and charge its drain to logic level ⁇ l'
- the output of inverter Il will also be logic level ⁇ l' .
- This potential at the gate of pass-through NFET N7 will allow it to conduct and pull its drain voltage to the same potential as its source terminal that is connected to node B7.
- the source potential on pass-through NFET N7 is set in the following manner.
- the logic level ⁇ l' on node B12 at the gate of pull-up PFET transistor P4 will disable conduction thereof into node B7.
- FIG. 6 illustrates a modification of FIG.5 in which a SPM' power management block 40' comprising a circuit incorporating MOSFET devices including PFET transistors P5 and P6 and NFET transistors N15, N16, N17 and two inverters 12/13.
- a SPM' power management block 40' comprising a circuit incorporating MOSFET devices including PFET transistors P5 and P6 and NFET transistors N15, N16, N17 and two inverters 12/13.
- WLPDN line 32 is connected to the input of inverter 12, the output of which is connected via Node B21 to the gate of PFET P5 and the input of inverter 13, the output of which is connected via node B22 to the gates of NFET 17 and PFET P6.
- the drain of PFET P5 is connected to the gate of NFET 15.
- the sources of PFET transistors P5 and P6 are connected via node B20 to positive voltage VDD, e.g. about 1.2V.
- the drain of PFET P6 is connected through node B17 to the gate of NFET N16 and the drain of NFET N15.
- the sources of NFET transistors N15 and Nl 6 are connected through node Bl9 to WordLine NEGative voltage WLNEG, e.g. from about. -0.2 to about -1.0V.
- the drains of NFET 17 and the drain of NFETl 6 are connected via node B6 to the Wordline Power Down Bus (WLPDN) line 32.
- WLPDN Wordline Power Down Bus
- the operation of the SPM block 40' is as follows.
- the input to the circuit, WLPWRDN on line 36 is high or logic level ⁇ l' .
- the output of inverter 12 having its input connected to WLPWRDN line 36 and its output connected to node B21 will be logic level ⁇ 0' .
- the output of inverter 13 having its input connected to the output B21 of inverter 12 and its output connected to node B22 will be logic level ⁇ l' .
- the gate of pull-up PFET transistor P5 is connected to node B21.
- the logic level y 0' or low potential on node B21 allows pull-up PFET transistor P5 to conduct and charge its drain terminal to VDD.
- the drain terminal of PFET P5 is connected to the gate terminal of pull-down transistor N15.
- the high potential at its gate terminal will cause pull-down transistor N15 to conduct and discharge node B17 to the WLNEG potential.
- Node B17 is also connected to the gate terminal of pull-down NFET transistor N16 and the drain of pull-up PFET transistor P6, respectively.
- the WLNEG potential on node B17 will disable conduction of pull-down NFET transistor N16.
- Node B22 which is at a logic level ⁇ l' is connected to the gate of pull-down NFET transistor N17 and the gate of pull-up PFET transistor P6, respectively.
- the high potential on node B22 will disable conduction of pull-up PFET transistor P6 and will enable conduction of pull-down NFET transistor N17, respectively.
- the conduction of pull-down NFET transistor N17 will discharge the WLDPN bus 32 to ground, the logic level ⁇ 0' for high performance mode.
- the input to the circuit, WLPWRDN on line 36 is low or at logic level ⁇ 0' .
- the output of inverter 12, having its input connected to WLPWRDN line 36 and its output connected to node B21 will be at logic level ⁇ l' .
- the output of inverter 13, having its input connected to the output of inverter 12 via node B21 and its output connected to node B22, will be at logic level ⁇ 0' .
- the gate of pull-up PFET transistor P5 is connected to node B21. The high potential on node B21 will prevent pull-up PFET transistor P5 from conducting.
- Node B17 is also connected to the gate terminal of pull-down NFET transistor N16 and the drain of pull-up PFET transistor P6, respectively.
- Node B22 which is at a logic level ⁇ 0' , is connected to the gate of pull-down NFET transistor N17 and the gate of pull-up PFET transistor P6, respectively.
- the low potential on node B22 will enable conduction of pull-up PFET transistor P6 and will disable conduction of pull-down NFET transistor N17, respectively.
- the conduction of pull-up PFET transistor P6 will charge the gate terminal of pull-down NFET transistor N16 to VDD. This will enable pull-down NFET transistor N16 to conduct and discharge the WLDPN bus 32 to WLNEG, the logic level ⁇ 0' for standby mode.
- This lower voltage on node B6 unlike the ground potential of FIG. 2 will bias the row driver circuits DRl, DR2 (up to DR 512) and array transistor circuits AO/Al, etc. to a reduced standby current state.
- the WLNEG voltage is connected to the node B6
- all of the sources of the NFETs in the driver circuits DR1-DR512 are lowered to near the WLNEG voltage, which, when the respective NFETs are conducting lowers the voltage on nodes B2 and B4 in FIG.4 to near WLNEG turning off the wordlines 26-1 and 26-2, etc. and placing a negative bias on the gates of the array transistor circuits AO/Al, etc.
Abstract
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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EP04741612A EP1639602B1 (en) | 2003-06-16 | 2004-05-19 | Low power manager for standby operation of a memory system |
DE602004018924T DE602004018924D1 (en) | 2003-06-16 | 2004-05-19 | LOW-POWER CONTROLLER FOR STANDBY OPERATION OF A STORAGE SYSTEM |
Applications Claiming Priority (2)
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US10/250,233 US7046572B2 (en) | 2003-06-16 | 2003-06-16 | Low power manager for standby operation of memory system |
US10/250,233 | 2003-06-16 |
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WO2004112041A2 true WO2004112041A2 (en) | 2004-12-23 |
WO2004112041A3 WO2004112041A3 (en) | 2005-05-12 |
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PCT/EP2004/050867 WO2004112041A2 (en) | 2003-06-16 | 2004-05-19 | Low power manager for standby operation |
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US (2) | US7046572B2 (en) |
EP (1) | EP1639602B1 (en) |
CN (1) | CN100570742C (en) |
AT (1) | ATE420439T1 (en) |
DE (1) | DE602004018924D1 (en) |
WO (1) | WO2004112041A2 (en) |
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US11830553B2 (en) | 2020-10-23 | 2023-11-28 | Changxin Memory Technologies, Inc. | Word line drive circuit and dynamic random access memory |
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US20010028591A1 (en) | 2000-03-30 | 2001-10-11 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device having normal and standby modes, semiconductor integrated circuit and mobile electronic unit |
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WO2004112041A3 (en) | 2005-05-12 |
US20040252573A1 (en) | 2004-12-16 |
ATE420439T1 (en) | 2009-01-15 |
DE602004018924D1 (en) | 2009-02-26 |
EP1639602A2 (en) | 2006-03-29 |
CN1799103A (en) | 2006-07-05 |
US20060039226A1 (en) | 2006-02-23 |
US7023758B2 (en) | 2006-04-04 |
EP1639602B1 (en) | 2009-01-07 |
US7046572B2 (en) | 2006-05-16 |
CN100570742C (en) | 2009-12-16 |
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