WO2004109909A1 - Systeme de commande automatique de gain - Google Patents

Systeme de commande automatique de gain Download PDF

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Publication number
WO2004109909A1
WO2004109909A1 PCT/IB2004/050820 IB2004050820W WO2004109909A1 WO 2004109909 A1 WO2004109909 A1 WO 2004109909A1 IB 2004050820 W IB2004050820 W IB 2004050820W WO 2004109909 A1 WO2004109909 A1 WO 2004109909A1
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WO
WIPO (PCT)
Prior art keywords
gain
level
quantizer
detector
count
Prior art date
Application number
PCT/IB2004/050820
Other languages
English (en)
Inventor
Jan Van Sinderen
Johannes Hubertus Antonius Brekelmans
Original Assignee
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Publication of WO2004109909A1 publication Critical patent/WO2004109909A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/001—Digital control of analog signals

Definitions

  • the invention relates to an automatic gain control (AGC) system for a digitally controlled analog amplifier, said AGC-system comprising a level- detector/quantizer receiving the analog signals amplified by said amplifier and generating first quantizer output signals when the detected level is larger than a predetermined upper level and second quantizer output signals when the detected level is lower than a predetermined lower level and a gain-step generator controlled by the first and second quantizer output signals for setting the gain of the amplifier.
  • AGC automatic gain control
  • the gain of a digitally controlled amplifier is controlled in steps. This has the advantage that for each discrete gain setting the amplifier can be optimized for such parameters as linearity, noise figure and magnitude of the step. For instance, at small signal levels the gain should be high with low noise factor while the linearity is not of primary importance. In contradistinction therewith at large signal levels the gain should be low with optimal linearity while the noise figure is of minor interest.
  • the level- detector/quantizer is implemented as a peak detector wherein the signal is compared with upper and lower comparator-levels and each time that the signal passes a comparator-level an up- or down stepping pulse is applied to the gain-step generator.
  • the gain-step generator comprises a stepping counter that receives its up/down stepping pulses from the level-detector/quantizer. Each tune that the signal is below the lower comparator-level an up-pulse is produced that increases the gain by one step and each time that the signal is above the upper comparator-level a down-pulse is produced that decreases the gain by one step.
  • the signal to be detected by the AGC-system can consist of a number of channels of substantially equal strength.
  • One problem identified is that, due to the strong non-linear properties inherent to a signal detection, small deviations from the equidistant frequency spacing of the plurality of channels leads to low frequency beat products at the detector output.
  • individual communication channels may be modulated in amplitude, the composite signal may also carry a low frequency modulation.
  • the prior art AGC-system attempts to remove said low frequency detector output fluctuations by controlling the gain of the amplifier accordingly.
  • the addition of a continuously controlled amplifier, to complement the digitally controlled amplifier as proposed in prior art document, is not able to prevent the system from following said fluctuations in detected signal.
  • the object of the present invention to provide an improved AGC- system of the abovementioned kind with reduced tendency to follow low frequency beat products in the detector output signal and which is moreover very well suited for integration in a monolithic integrated circuit with practically no external components and the AGC-system according to the invention is therefore characterized by a digital low pass filter receiving quantizer output signals from the level-detector/quantizer and generating there from stepping pulses and by means supplying the stepping pulses generated by the digital low pass filter to the gain-step generator.
  • the low pass filter effectively reduces the effect of the beat products of the received plurality of channels on the setting of the gain of the digitally controlled amplifier.
  • a suitable and easy to implement form of the AGC- system according to the present invention is characterized in that the digital low pass filter comprises a clock-pulse counter that is arranged to count in one direction upon reception of a second quantizer output signal and to count in the opposite direction upon reception of a first quantizer output signal, means to supply a step-down pulse to the gain-step generator when the counting reaches a maximum count-value in said one direction, to supply a step-up pulse to the gain-step generator when the counting reaches a maximum count- alue in said opposite direction and to supply both the step-up pulses and the step-down pulses to a reset input of the clock-pulse counter.
  • the digital low pass filter comprises a clock-pulse counter that is arranged to count in one direction upon reception of a second quantizer output signal and to count in the opposite direction upon reception of a first quantizer output signal, means to supply a step-down pulse to the gain-step generator when the counting reaches a maximum count-value in said one direction, to supply
  • a disadvantage of the above given embodiment is that the AGC-system cannot react fast enough when the output of the amplifier is overloaded (clipping).
  • the AGC system of the present invention may be made to react asymmetrically between increasing and decreasing the gain of the digitally controlled amplifier.
  • a specific embodiment of the AGC-system of this kind is characterized by the digital filter comprising a clock-pulse counter that starts changing the count-value upon the reception of a second quantizer output signal, by means to supply a step-up pulse to the gain-step generator when the count- value of the clock-pulse counter reaches a predetermined value and by supplying the unfiltered first quantizer output signals as step-down pulses to the gain-step generator.
  • the level-detector of the above mentioned prior published patent application is essentially a peak detector.
  • a further characteristic of the AGC-system of the invention is that the level-detector/quantizer has a mainly quadratic detection characteristic. It has been found that with a mainly quadratic detector (power detector) instead of a peak detector a smoother detection output without sharp peaks is obtained. The result is that the time constant(s) of the digital low pass filter can be reduced so that the AGC-system will react more quickly on level variations.
  • a chain of signal processing stages such as mixer, IF channel filter, IF- amplifier, detector etc, will often follow the digitally controlled analog amplifier.
  • An improved gain control action may be obtained when various signals in the chain are used to influence the gain setting of the digitally controlled amplifier.
  • the AGC-system of the present invention may be characterized by a plurality of level-detector/quantizers, each of the level-detector/quantizers receiving a signal from a different tap of said chain and by a single digital filter and gain-step generator receiving the first and second quantizer output signals generated by the plurality of level-detector/quantizers .
  • Fig. 1 a first embodiment of an automatic gain control system according to the invention
  • Fig. 2 a second embodiment of an automatic gain control system according to the invention.
  • the automatic gain control system of figure 1 comprises a digitally controlled amplifier A that receives an input signal V; and supplies an output signal V 0 .
  • the signal amplified by the amplifier A may comprise a large number of channels although the AGC-system of the present invention may also be used for controlling an amplifier handling a single channel.
  • the output signal N 0 of the amplifier is applied to an analog power detector P that may comprise a non-linear device having a quadratic transfer characteristic such as a MOS-transistor.
  • the power detector may also comprise a small capacitor to limit the spectral contents of the detected signal.
  • the detector output signal is subsequently applied to a quantizer Q comprising two comparators and C 2 .
  • the comparator Ci compares the detector output signal with a high threshold T h and produces an amplitude-discrete time-continuous first quantizer output signal when the level of the signal is higher than the threshold T h .
  • Equally the comparator C 2 compares the detector output signal with a low threshold Ti and produces a similar second quantizer output signal when the level of the signal is lower than the threshold Ti.
  • the system of figure 1 further comprises an up/down clock-pulse counter F that counts clock pulses C L and that is controlled by the output signals of the quantizer Q.
  • the counter increases its count-value on each clock transition when a second quantizer output signal of the comparator C 2 is present at an "up"-input F u and decreases its count-value on each clock transition when a first quantizer output signal of the comparator Ci is present at a "down"-input Fd.
  • the detector output level is in the "dead zone" between the quantizer levels Ti and T h , the inputs F d and F u of the counter F receive no signal at all and the stops changing its count-value.
  • the counter F counts between a negative value with a predetermined absolute value and a positive value with the same absolute value and the digital count-words are obtained from a counter output F 0 .
  • a bit-separator B each output word of the counter F is separated in a multi-bit absolute value and a single sign bit.
  • the sign bit is applied to an up/down input I s of a gain-step generator G.
  • the absolute value from the bit-separator is applied to a digital comparator C 3 where it is compared with a threshold T a that represents the maximum absolute count-value.
  • a step pulse is generated that is applied to a step input I a of the gain-step generator. Simultaneously this pulse is applied through an OR-gate O to a reset input F r of the counter F.
  • the count-value increasing upon reception of a second quantizer output signal at input F u , decreasing upon reception of a first quantizer output signal at input F d and halting when no such signal is received, may freely vary between the values -T a and +T a .
  • the sign-bit applied to the input I s of the gain-step generator G sets this generator in position "down".
  • the digital comparator C 3 generates a pulse at the input I a of the gain-step generator and this gain-step generator will make one step in downward direction. This pulse also resets the counter F to reset the count-value to zero.
  • the sign-bit applied to the input I s of the gain-step generator sets this generator in the position "up" and when then the count-value reaches its negative maximum value -T a , the comparator digital C 3 generates again a pulse and the gain-step generator will make one step in upward direction. Again this pulse resets the counter F to zero.
  • the arrangement of figure 1 comprises a frequency divider D, having a dividing ratio a, taking the clock signal C L at its input and producing a reset signal for counter F.
  • the reset signal is being applied through the OR-gate O.
  • This provision will reset the counter F in case, over a period of time determined by the product of clock period T ⁇ ⁇ and dividing ratio No, the counter contents does not reach one of the threshold values.
  • the provision solves a problem related to a digitally controlled amplifier A in that the gain can never be set exact to the required value because gain settings are discrete. As a result, the number of 'up' and 'down' pulses received by the counter in steady state operation on average will not be zero and the counter contents will drift away from zero.
  • the arrangement of figure 2 comprises two level-detectors P a and Pb, each having a MOS-transistor l a , lb, a gate capacitor 2 a , 2 b through which the signal V 0 from the amplifier A is applied to the gate terminals of the MOS-transistors, a bias resistor 3 a , 3b through which a bias voltage V a , Vb is applied to the respective gate terminal, a source-drain smoothing capacitor 4 a , 4 b and a DC current source 5 a , 5 b connected to each respective drain terminal.
  • the two MOS-transistors operate as power detectors by virtue of their I S - V gs transfer function being approximately quadratic and the two detector output signals are taken from the drain terminals and respectively applied to inverting comparators Ci and C 2 of a quantizer Q', which compare the two detector output signals with a single threshold T' and invert the result of the comparison. It may be observed that the function of the two comparator thresholds T h and Ti of figure 1, namely the creation of a "dead zone" in which level variations of the detector output signals have no effect on the counting process of the counter F, is performed in the arrangement of figure 2 by the two different bias voltages V a and V b of the level-detectors P a and P b .
  • the different bias voltages create different thresholds for the two comparators and therewith the "dead zone".
  • the analog signal V 0 increases, the drain voltage of MOS-transistor la decreases and when this drain voltage decreases so far that the upper level of the "dead zone", defined by the bias voltage V a , is passed then the drain voltage of MOS-transistor la comes below the threshold T' and the output of the inverting comparator C' ⁇ becomes high.
  • the arrangement further contains a clock controlled counter F' with a counter output F' 0 and a reset input F' r that is connected through an OR-gate O' 2 to the output of the inverting comparator C 2 .
  • the count-value from the output F' 0 is applied to a digital comparator C 3 where it is compared with the threshold T a .
  • the output pulse of the digital comparator C 3 is applied to an "up"-input I u of a gain-step generator G' and steps this gain-step generator upwards by one step. Simultaneously this output pulse resets the counter through the OR-gate O' 2 .
  • the count-value reaches the digital threshold Ta.
  • the digital comparator C' 3 supplies a pulse to the "up"- input I u of the gain-step generator G' and the gain of the amplifier A is increased by one step. Simultaneously the pulse from comparator C 3 resets the counter to prepare it for a new count action.
  • the output signal of the comparator C' ⁇ is applied through an OR-gate O' ⁇ to a "dowif'-input I d of the gain-step generator G'. Therefore, as soon as the output signal of the detector P a surpasses the comparator level T' the gain-step generator is directly stepped downwards without any digital low-pass filtering. Thus, when for any reason the signal V 0 from the amplifier A is too large so that a danger of clipping exists, the gain of the amplifier is instantaneously reduced by one step.
  • the gain controlled amplifier A is followed by further stages Si and S 2 , e.g. an IF channel filter and a LF signal detector and it may be desirable to additionally control the gain of amplifier A in dependence upon the output signals of these further stages.
  • AGC-units Ui and U 2 which may be identical in construction to the power detectors P a , and P b and the comparators C' ⁇ and C 2 , serve this additional automatic gain control.
  • the OR-gate O' ⁇ combines the output signals of the comparators C' ⁇ of all the units and the OR-gate O' 2 combines the output signals of the comparators C' 2 of all the units. Consequently the counter F', the comparator C' 3 and the gain-step generator G' are driven by the combined signals from all the units.

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  • Control Of Amplification And Gain Control (AREA)

Abstract

Ce système CAG pour un amplificateur analogique à commande numérique comprend un détecteur analogique de niveau, un quantificateur qui quantifie la sortie du détecteur de niveau et génère des premier et deuxième signaux de sortie du quantificateur, un filtre numérique passe-bas qui filtre au moins un des deux signaux de sortie du quantificateur et un générateur de degrés de gain commandé par les impulsions du filtre numérique.
PCT/IB2004/050820 2003-06-10 2004-06-02 Systeme de commande automatique de gain WO2004109909A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03101670 2003-06-10
EP03101670.2 2003-06-10

Publications (1)

Publication Number Publication Date
WO2004109909A1 true WO2004109909A1 (fr) 2004-12-16

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Country Status (1)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008029114A1 (fr) * 2006-09-07 2008-03-13 Poem Technologies Company Limited Commande de gain numérique
WO2009150611A1 (fr) * 2008-06-09 2009-12-17 Nxp B.V. Détecteur numérique et système numérique de contrôle automatique du gain pour récepteurs radio
CN101132209B (zh) * 2007-10-15 2011-08-24 威盛电子股份有限公司 自动增益控制的装置和方法
US20120195297A1 (en) * 2011-01-28 2012-08-02 Kabushiki Kaisha Toshiba Wireless communication apparatus, information processing apparatus, and method for controlling antenna of information processing apparatus
US8396427B2 (en) 2008-10-23 2013-03-12 Nxp B.V. System and method for adaptive radio frequency filtering
WO2023037850A1 (fr) * 2021-09-07 2023-03-16 株式会社村田製作所 Circuit haute fréquence

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4910797A (en) * 1987-03-02 1990-03-20 Samsung Electronics Co., Ltd. Automatic Gain control system
US5117201A (en) * 1990-03-23 1992-05-26 Deutsche Itt Industries Gmbh Automatic gain control apparatus for digital variable-gain amplifier
US5659582A (en) * 1994-02-28 1997-08-19 Mitsubishi Denki Kabushiki Kaisha Receiver, automatic gain controller suitable for the receiver, control signal generator suitable for the automatic gain controller, reception power controller using the automatic gain controller and communication method using the receiver
US20020015458A1 (en) * 2000-07-11 2002-02-07 Jan Van Sinderen AGC circuit
US20020118779A1 (en) * 2000-12-21 2002-08-29 Qiang Wu Low latency for start of initial automatic gain control for data in digital signal processing
WO2002080399A1 (fr) * 2001-03-28 2002-10-10 Gct Semiconductor, Inc. Procede automatique de controle de gain pour recepteur de telecommunications a forte integration

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4910797A (en) * 1987-03-02 1990-03-20 Samsung Electronics Co., Ltd. Automatic Gain control system
US5117201A (en) * 1990-03-23 1992-05-26 Deutsche Itt Industries Gmbh Automatic gain control apparatus for digital variable-gain amplifier
US5659582A (en) * 1994-02-28 1997-08-19 Mitsubishi Denki Kabushiki Kaisha Receiver, automatic gain controller suitable for the receiver, control signal generator suitable for the automatic gain controller, reception power controller using the automatic gain controller and communication method using the receiver
US20020015458A1 (en) * 2000-07-11 2002-02-07 Jan Van Sinderen AGC circuit
US20020118779A1 (en) * 2000-12-21 2002-08-29 Qiang Wu Low latency for start of initial automatic gain control for data in digital signal processing
WO2002080399A1 (fr) * 2001-03-28 2002-10-10 Gct Semiconductor, Inc. Procede automatique de controle de gain pour recepteur de telecommunications a forte integration

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008029114A1 (fr) * 2006-09-07 2008-03-13 Poem Technologies Company Limited Commande de gain numérique
CN101132209B (zh) * 2007-10-15 2011-08-24 威盛电子股份有限公司 自动增益控制的装置和方法
WO2009150611A1 (fr) * 2008-06-09 2009-12-17 Nxp B.V. Détecteur numérique et système numérique de contrôle automatique du gain pour récepteurs radio
US8396427B2 (en) 2008-10-23 2013-03-12 Nxp B.V. System and method for adaptive radio frequency filtering
US20120195297A1 (en) * 2011-01-28 2012-08-02 Kabushiki Kaisha Toshiba Wireless communication apparatus, information processing apparatus, and method for controlling antenna of information processing apparatus
WO2023037850A1 (fr) * 2021-09-07 2023-03-16 株式会社村田製作所 Circuit haute fréquence

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