WO2004107163A1

WO2004107163A1 - Instruction control device having branching prediction mechanism and control method thereof

Info

Publication number: WO2004107163A1
Application number: PCT/JP2003/006668
Authority: WO
Inventors: Ryuichi Sunayama; Aiichirou Inoue; Masaki Ukai
Original assignee: Fujitsu Limited
Priority date: 2003-05-28
Filing date: 2003-05-28
Publication date: 2004-12-09
Also published as: JP3852782B2; JPWO2004107163A1

Abstract

An instruction control device and control method for suppressing or invalidating an erroneous instruction fetch request or operand request until a re-instruction fetch request is output to a memory when a branching prediction is made incorrectly. In order to achieve this object, an instruction control device fetches an instruction stored in a storage section and executes the instruction in the out-of-order method. The instruction control device includes a branching instruction prediction section for predicting an instruction branching and a branching prediction control section. When the branching prediction control section judges that the branching prediction made by the branching instruction prediction section has been incorrect, the instruction control device suppresses an instruction fetch request which has been output to the storage section and invalidates the instruction already output from the storage section during a period after the branching prediction control section has judged that the branching prediction made by the branching instruction prediction section has been incorrect until a correct instruction is re-fetched from the storage section.

Description

Life control with branch prediction mechanism ^^ Control method

The present invention generally relates to an instruction control device in a central processing unit of a computer, and more particularly, to an out-of-order instruction control device having a branch prediction mechanism, when a branch prediction is erroneous, a re-instruction fetch request is issued. Incorrect or invalid instruction fetch requests and operand requests until memory can be output to memory

This is related to the evolving order system.

Rice field

Background art

There are two types of processing for controlling the instruction control unit (instruction unit) in the central processing unit of the computer: the in-order method and the out-of-order processing method. In the in-order processing, instructions are stored in a memory and are executed in the order of execution.

On the other hand, in the out-of-order processing, a plurality of subsequent instructions are sequentially input to the pipeline without waiting for the execution of one instruction to be completed, and the instruction is saved. That is, in the new pipeline, the instructions are executed while changing the order of the instructions to be executed by a plurality of arithmetic units. Finally, the overall execution of the instruction is completed in-order. Thus, the input of instructions to the Kikusui pipeline and the completion from there are performed sequentially, but in the Kikusui pipeline, the instructions are actually changed while changing the order! ^ Ϊ́ Is done.

However, even in out-of-order processing, the execution result of the preceding instruction affects 後 of the following instruction; if the processing of the preceding instruction is not completed, Subsequent instructions cannot be executed. Therefore, it waits for the completion of the preceding instruction.

This is noticeable in the execution of this branch instruction, even though the preceding instruction is a branch instruction. Branch instructions include conditional branch instructions and unconditional branch instructions. You. Among these branch instructions, the conditional branch instruction is an instruction in a section earlier than itself that is about to change the branch condition. Until this is done, it is uncertain whether the branching power of the conditional branch instruction or not.

Therefore, since the instruction sequence following the conditional branch instruction cannot be determined, the subsequent instruction cannot be input to the node pipeline, and the processing stops. This results in reduced throughput.

The processing capability, that is, the reduction in performance, is the same in the order control device employing other processing methods, and is common to the instruction control devices. As a means for solving the performance degradation caused by the branch instruction, usually, a prediction mechanism for predicting the branch execution of the branch instruction is provided in the instruction control unit to speed up the execution of the branch instruction. I try to plan.

In the top-order processing method provided with the branch prediction mechanism, a plurality of branch instructions are input to the cut-off line based on the result of the branch prediction. The existence of a branch and the success or failure of branch prediction are determined sequentially from the branch instruction whose branch condition is determined.

If the branch prediction by the branch prediction mechanism is correct, the instruction following the predicted branch instruction is correctly input to the execution pipeline. However, if the branch prediction power S is incorrect, the instruction following the predicted branch instruction has an incorrect instruction sequence, so it is necessary to delete the instruction from the node pipeline and to correct it again with the correct instruction sequence. There is.

At the age when the branch prediction fails, it operates to fetch the instruction again. However, after the branch prediction by the branch prediction mechanism is found to have failed, before the instruction fetch is performed again, or until the wrong instruction sequence is erased from the execution pipeline. The time of the moss S is strong, and it is strong.

During this time, the instruction is actually placed on the pipeline, and requests for operands are generated from those instructions that are not actually executed. This is the same for the instruction fetch. That is, unnecessary requests for instruction sequences that are not actually used occur. When an operand or instruction fetch request that is not actually needed occurs, Unnecessary replacements in the cache occur or cause unnecessary consumption of instruction control resources such as exercises, which cause performance degradation.

That is, if it is determined that the branch instruction has failed and the branch prediction has failed, it is necessary to issue a re-instruction fetch request to the instruction fetch control unit. However, in order to issue a re-instruction fetch request, both the branch condition and the branch destination address must be determined. Furthermore, even if it is known that the branch condition has been determined and the branch prediction has failed, if the branch destination addressing power has not been determined, a re-instruction fetch request cannot be issued and the instruction fetch control unit is unnecessary during that time. There is a problem that it keeps issuing a large instruction fetch request.

Furthermore, the instruction entered into the Kikuzaki pipeline based on the incorrect branch prediction due to the failed branch prediction must be deleted from the pipeline. That must be. However, instruction completion is an in-order processing, so the instruction power before the branch instruction must be completed before the fire instruction 命令 The instruction input to the pipeline cannot be deleted from the pipeline. Therefore, if the completion of a branch instruction that fails to predict a branch is delayed, there is a problem in that an unnecessary operand request is issued from an instruction that is erroneously input to the pipeline. Disclosure of the invention

The present invention has been made in view of the above points, and suppresses or invalidates an erroneous instruction fetch request / operand request until a branch instruction is incorrectly predicted and a re-instruction fetch request is issued to a memory. An object of the present invention is to provide an instruction control method, an instruction fetch method, and an apparatus thereof.

In order to achieve this object, the present invention provides an instruction fetch control unit that controls instructions so as to fetch an edit instruction from a storage unit that stores instructions, which registers instructions in an out-order manner;

An instruction buffer for temporarily storing instructions supplied from the café's own storage unit,

An instruction decoder for decoding an instruction sent from the Sfjf own instruction buffer, a branch instruction prediction unit for predicting an instruction branch,

Knitting instruction fetch control unit, kinking instruction buffer, kinking instruction decoder, and In an instruction control apparatus having a branch prediction control unit for controlling a branch instruction prediction unit, the age at which the unknowing branch prediction control unit determines that the branch prediction power of the unknowing branch instruction prediction unit was S error was wrong. After the so-called self-branch prediction control unit determines that the branch predictive power S by the unpleasant branch instruction prediction unit was incorrect, the operation is continued until the instruction buffer re-fetches the correct instruction from the storage unit. The own branch prediction control unit outputs a signal for suppressing the instruction fetch request already output to the ffit self storage unit to the instruction fetch control unit, and outputs a signal for invalidating the own instruction buffer to the instruction buffer. To remove the equipment.

According to the present invention, as described above, the branch prediction failure power s is found, and when the other conditions for issuing a re-order fetch request are not determined, all the criterion forces for the re-order fetch request are equal. Up to this point, the cache control unit can be notified of a cancel signal for invalidating all instruction fetch requests, and can also be notified to the decoder unit to stop issuing instructions at the same time.

Further, in order to achieve this object, the present invention provides an instruction fetch control unit which controls an instruction to be fetched from a storage unit storing the instruction, wherein the instruction fetch control unit executes the instruction in an out-of-order manner

An instruction buffer for temporarily storing instructions from the hatred storage unit,

an instruction decoder for decoding an instruction sent from the iff self instruction buffer buffer; a branch instruction prediction unit for predicting a branch of the instruction;

iff self-instruction fetch control unit, ffif self-instruction z-buffer, {instruction decoder}, and l self-branch instruction prediction unit that controls a self-branch instruction prediction unit. To determine that the branch prediction by the iilH branch instruction prediction unit was incorrect, the tiif own branch prediction control unit determines that the branch prediction power by the tiff self branch instruction prediction unit was s error, and Until the hater instruction buffer re-fetches the correct instruction from the storage unit, the branch prediction control unit determines whether or not the instruction that is erroneously set due to an error in the branch prediction by the branch instruction prediction unit is incorrect. An instruction control device for outputting a signal for invalidating the operand request to the self-memory unit and outputting a signal for invalidating the obscene instruction decoder to the tiff own instruction decoder. According to the present invention, there is provided a cancel signal for disabling the above instruction At the same time, and can notify the cache control unit of a cancel signal for suppressing unnecessary operand fetch requests.

In addition, at this time, the cache controller is notified of the fjlj child of the instruction erroneously input to the pipeline at the same time, so that the operand fetch request requested by the cache controller is unnecessary or unnecessary. The request can be determined. As described above, in the present invention, the cancel instruction signal for suppressing unnecessary instruction fetch request and operand request is notified from the branch instruction ^ IJ control unit to the instruction fetch control unit and the cache control unit, respectively, and re-instruction fetch is performed. Since instruction input can be stopped until completion, unnecessary replacement in the cache section can be suppressed, and processor performance can be improved. BRIEF DESCRIPTION OF THE FIGURES

Other objects and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.

FIG. 1 is a block diagram showing an outline of a portion for executing a branch instruction control operation in an instruction control device in a central processing unit of a computer according to an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 3 is a diagram showing a part of a circuit diagram for generating a control signal according to the present invention.

FIG. 4 shows a part of a circuit diagram for generating a control signal according to the present invention.

FIG. 5 is a diagram showing a part of a circuit diagram for generating a control signal according to the present invention.

FIG. 6 is a diagram showing a part of a circuit diagram for generating a control signal according to the present invention.

FIG. 7 is a diagram showing a part of a circuit diagram for generating a control signal according to the present invention.

FIG. 8 is a diagram showing a part of a circuit diagram for generating a control signal according to the present invention. FIG. 9 is a diagram showing a part of a circuit diagram for generating a control signal according to the present invention.

FIG. 10 is a diagram showing a part of a circuit diagram for generating a control signal according to the present invention.

FIG. 11 is a diagram showing a part of a circuit diagram for generating a control signal according to the present invention.

FIG. 12 is a diagram showing a part of a circuit diagram for generating a control signal according to the present invention.

FIG. 13 is a diagram showing a timing chart of the conventional branch control.

FIG. 14 is a diagram showing a timing chart of a signal generated according to the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment for carrying out the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an outline of a portion for executing a branch instruction IJ control operation in an instruction control device 100 (instruction unit) in a central processing unit of a computer according to an embodiment of the present invention. The instruction control device 100 is connected to a storage unit 103 including a cache memory 101 and a cache control unit 102. The part that executes the branch operation in the instruction IJ control device (instruction unit) 100 is mainly composed of an instruction fetch control unit (Inst r uc ti on Fe t ch C

0 ntro 1 or IFCTL) 111, instruction buffer (Instructione Buffer or IBBUFER) 112, branch predictor (BranchHH)

1 story, BRHI S) 113, Branch instruction control unit (Reservation on Stand-by Link or RSBR) 114, Instruction decode unit (Decoder or DDECR) 115, Instruction completion control unit (Commit (Faciity or COMIT) 116. Then, the IJ controller 100 controls reading of the instructions from the cache memory 101 via the cache IJ controller 102. In the instruction control device 100, the instructions are processed according to the above-described art-over-order system. In the IJ controller 100 of this embodiment, chrysanthemum and a flag (Instruction ID or I ID) indicating the order of instructions on the pipeline are assigned to all instructions to be machined on the pipeline. Has been. Instructions are processed in the execution pipeline in accordance with out-of-order processing. When an instruction is completed, the instruction is completed in the above-mentioned in-line processing based on the ID.

First, the schematic operation of the block diagram of FIG. 1 will be described.

The instruction fetch control unit 111 sends an instruction fetch request (IF-REQ-VAL) such as an address to the cache control unit 102, for example. Thus, the instruction stored in the cache memory 101 is read out via the cache control unit 102. The instruction read in this way or the cache control unit 102 is stored in the instruction buffer 112.

The instruction fetch control unit 111 also sends the above address to the branch prediction unit 113 via a signal 120. When the instruction fetch is performed by the instruction fetch control unit 111, the branch prediction is performed in the BRHI S113 based on the instruction fetch address as described above. As a result of the branch prediction, the age at which the branch is predicted is determined by the instruction to the IFCL111 via the signal 121 by attaching a flag (+ BRHIS—HIT = l) indicating the predicted result of “branch” to the instruction. Then, it is supplied to DDE CR 115 via I FC LI 11 and I BBUFER 112. The instruction whose branch has been predicted in this way is stored in the instruction buffer 112 from the instruction fetch control unit 111.

The instruction buffer 112 sends the stored instruction to the instruction decoding unit 115. The instruction decoding unit 115 decodes the instruction sent from the instruction buffer 112.

When an instruction is decoded by the instruction decoding unit (DDECR) 115, an instruction determined as a “branch instruction” or an “instruction predicted to be known” is entered into the RSBR 114 and the COMIT 116 via a signal 122. Note that all instructions input to the pipeline are entered into the instruction completion control unit (COMIT) 116 irrespective of the decoding result in DDEC Rl15.

DDECR115 is designed to send instructions to the ^? Pipeline and Assigns a flag (Instruction ID or I ID) indicating the order of instructions on the pipeline.

The RSBR 114 outputs a re-instruction fetch request (RSBR-RE I FCH-REQ) to the instruction fetch control unit 111 when the branch determination and the branch prediction fail, and performs control. The RSBR114 can control and control a plurality of branching instructions (entries) on the pipeline, and each entry is a flag IID indicating the above-mentioned instruction on the Kikuya pipeline). Is managed. The instruction for which the control in RSB Rl14 has been completed is released from the RSBR114, and is controlled by the COMIT 116 until the instruction is completed. COM I T 116 controls the instruction completion of all instructions on the shear pipeline.全 All instructions on the pipeline are managed by I ID, and instructions are completed by in-order processing in order from the one that satisfies the instruction completion condition.

Next, the operation of the embodiment of the present invention will be described with reference to FIG. FIG. 2 is a flowchart showing the operation of the embodiment of the present invention.

In step 201 of FIG. 2, first, a branch instruction is issued from the instruction decode unit (D DECR) 115 to the branch instruction control unit (RSBR) 114 as described above.

Next, in step 202, the RSBR 114 registers a branch instruction, as described above. The RSBR 114 can register and control a plurality of branch instructions existing on the execution pipeline.

Next, in step 203, a branch is determined. If the determination of the branch prediction has failed, the process proceeds to step 204.

When the branch prediction is determined by the RSBR114, it is determined that the branch prediction by the BRHI S113 has failed if the following conditions from the first condition to the fourth condition are different or 1 The two conditions are satisfied.

The first condition is that the branch instruction predicted not to branch is known. The second condition is that the predicted branch instruction does not branch: ^. The third condition is that the branch destination address of a branch instruction predicted to branch is: ^. The fourth condition predicts that instructions that are not branch instructions will be seen as if they were branch instructions. It is.

The following is a logical expression that satisfies the first to fourth conditions.

+ RSB R_VAL ID & — R SBR R_B RH I S — HIT & + RSBR — RESOLVED & + RSBR-TAKE N is true: ^

The second condition is met: + RSBR—VAL I D & + RSBR— BRH I S— HIT & + RSBR- RESOLVED & — RSBR— TAKE N is true,

Meets the third condition 1 "^ is: + RSBR— VAL I D & + RSBR- BRH I S- HIT & + RSBR- TAV & — RSBR- TGTCP- MATCH is true,

If the fourth condition is met: + RSBR—PHANTOM—VAL ID is true.

Here, each signal is a signal having the following meaning.

(1) + RSBR—VAL ID indicates that the RSBR 114 entry is a branch instruction.

(2) + RSBR—BRHIS-HIT indicates that the entry was predicted to "branch" at BRHI S113.

(3) + RSBR_RESOLVED indicates that the branch condition of the entry has been determined.

(4) + RSBR_TAKEN indicates that the entry is 1 ^ 1 ".

(5) + RSBR—TAV indicates that the branch address of the entry has been determined.

(6) + RSBR—TGTCP-MATCH indicates that the predicted branch address of the entry is correct and is an address.

(7) + RSBR—PHANTOM—VAL ID indicates that an instruction that is not a branch instruction has been determined to branch as a branch instruction.

Here, a "+" sign added to the head of a signal name indicates positive logic, while a "-" sign added to a signal name indicates negative logic. That is, for example, For (1) + RSBR—VAL ID, the + RSBR—VAL ID is positive when the entry is “predicted” by BR RH IS 113. On the other hand, the entry + RSBR—VAL ID is negative when is predicted to be “know” by BRH IS 113. The symbol “&” indicates a logical AND operation. : In ^, the process proceeds to step 204. Next, in step 204, the following control is performed simultaneously.

Invalid instruction fetch request to cache control unit 102 via IFCTL 111 by RSBR114 force, signal 123 (RSBR—CANCEL—IF—ID—0, 1, 2, 3, 4, 5) (CANCEL-IF-ID- 0, 1, 2, 3, 4, 5, 5) is sent.

At this time, the data in all the IBBUFER112 (memory mechanism for temporarily storing the fetched data from the memory until the data is fetched from the memory to the DDECR 115. In this embodiment, the IFCL111 has 6 ports) To delete.

This signal is sent continuously until a re-instruction fetch request (RSBR-REIFCH-REQ) is issued from RSBR 114 to 111 at signal 123.

Furthermore, in order to suppress re-instruction fetch requests (RSBR-REIFCH-REQ) from the RSBR entry following the instruction (entry) for which branch prediction failed, the subsequent RSBR entry is deleted.

Then, a signal (INH_E_VAL ID) is sent to RSBR114 and DDECR115 to suppress the instruction input to the pipeline. This signal is used until the unnecessary instruction injected into the pipeline due to incorrect branch prediction is deleted from the pipeline (that is, until the branch instruction whose branch prediction fails is completed. , COMI Tl 1

The instruction FLUS H_RS is sent and the instruction on the execution pipeline is erased. ) Sent continuously.

At the same time, a signal (CANCEL-OP-IID-VALID) is sent from the RSBR 114 to the cache control unit 102 to notify that the unnecessary operand request is invalid. At the same time, incorrect branch prediction In order to distinguish operand requests from unnecessary instructions entered into the line from operand requests from instructions entered into the clause pipeline before the branch instruction, I IDs following the branch instruction for which branch prediction failed are distinguished. Is notified from the RSBR 114 to the cache control unit 102 (CANCEL-OP_I ID [5: 0]). This signal (CANCEL—OP_ID [5: 0]) is sent continuously until an unnecessary instruction input to the purple pipeline due to incorrect branch prediction is erased from the ^ ¹ pipeline. Can be

Next, the routine proceeds to step 205. In step 205, since control was performed so that one word was generated in step 204 described above, in the cache control unit, C ANC EL—IF_ID—0, 1, 2, 3, 4, and 5 were all 1 During this time, the instruction fetch request is invalid. While CANCEL-OP-I10_10 is 1, operand requests from instructions on the execution pipeline following IID indicated by CANCEL-OP-IIDC5: 0] are invalidated.

Next, in step 206, an instruction refetch request (RSBR_REIFCH_REQ) is issued from the RSBR 114 to the IFCL 111, and instruction refetching is resumed.

Then, the process proceeds to step 207, where the branch instruction control by the RSBR 114 ends.

If it is determined in step 203 that the branch prediction power is successful, the process proceeds from step 203 to step 207.

Finally, at step 208, the branch instruction is completed.

As described above, in the present invention, unnecessary instruction fetch requests and operand requests are suppressed until the correct instruction sequence is fetched after the failure of branch prediction is found, and the issue of meaningless instructions on the pipeline is stopped. As a result, unnecessary replacement of the cache and unnecessary consumption of instruction control resources such as arithmetic units can be prevented, and the performance of instruction processing can be improved.

Next, according to the present invention, the control signals RSBR—CANCEL—IF—ID—0, 1, 2, 3, 4, 5, RSBR—RE I FCH: one REQ, and INH—E—one VA L ID And CANCEL OP I ID VAL ID and CANCEL OP — Describe the circuit that generates I ID [5: 0].

FIG. 3 shows an embodiment of a circuit for generating the above-mentioned control signals according to the present invention. FIG. 13 shows a time chart of a control signal of the conventional RSBR 114, and FIG. 14 shows a time chart of a control signal of the RSBR 114 to which the above-mentioned control signal is added according to the present invention.

First, a circuit for generating the control signals shown in FIGS. 3 to 12 will be described. Figure 3 shows a signal that sets RSBR-CANCEL-IF—ID—0, 1, 2, 3, 4, 5 (+ SET—RSBR—CANCEL—IF_ID_0, 1, 2, 3, 4, 5 ) Is shown. In the circuit diagram, “ALL” indicates ID-0, 1, 2, 3, 4, 5.

FIG. 3 includes circuit blocks 310, 320, and 330 and a multi-input OR gate 340. The circuit block 310 includes a 4-input AND gate 311, a 4-input AND gate 312, a 4-input AND gate 313, a buffer 314, and a 4-input OR gate 315. The circuit blocks 320 and 330 have the same configuration as the circuit block 310. However, the input signal to each circuit block corresponds to each instruction (entry) assigned to RSBR 114. For example, circuit block 310 is a circuit for an instruction for an entry with an IID of 0, circuit block 320 is a circuit for an instruction for an entry with an IID of 1, and The circuit block 330 is a circuit for an instruction for an entry whose IID is n.

The four-input AND gate 311 of the circuit block 310 is a circuit that decodes the above first condition. To the 4-input AND gate 311 of the circuit block 310, + RSBRO—VALID, + RSBR 0_RE SOLVED, + RSBR—TA KEN, and one RSBR—BRHI S—HIT are input. When all inputs are, 1 'is output from the 4-input AND gate 311. This is equivalent to the first condition S being satisfied: ^.

The four-input AND gate 312 of the circuit block 310 is a circuit for decoding the above-described second condition. Circuit block 310 4-input AND gate 312 has + RSBR VAL ID, 10 RSBR RE SOLVED, 1 RSBR TAKE N and + RSBR-BRHI S- HIT are input. When all the inputs are 1, the 4-input AND gate 312 outputs '1'. This is equivalent to the second condition: ^.

The 4-input AND gate 313 of the circuit block 310 is a circuit that decodes the third condition described above. + RSBR-VALID, + RSBR-TAV, -RSBR-TGTCP-MATCH, and + RSBR-BRHIS-HIT are input to the 4-input AND gate 313 of the circuit block 310. When all inputs are 1 and, is output from the 4-input AND gate 313. This is equivalent to the third condition: ^.

The buffer 314 of the circuit block 310 is a circuit for decoding the above-described fourth condition. + RSBR_PHANTOM—VALID is input to the buffer 314 of the circuit block 310. When the input is 1, the output of the buffer 314 is output. This reminds us that the fourth condition holds.

If any of the outputs of the 4-input AND gate 311, the 4-input AND gate 312, the 4-input AND gate 313, and the buffer 314 of the circuit block 310 is “1,” the 4-input OR gate 315 outputs “1”. You.

The same applies to the circuit blocks 320 and 330. If the output of one of the circuit blocks 310, 320 or 330 is, then OR gate 340 power '1' is output and SET-RSBR-CANCEL-IF-AL L is Become.

Figure 4 has the same configuration as Figure 3 and generates (+ SET—CANCEL—OP—I ID—VAL ID), which sets CANCEL—OP—I ID—VAL ID.

FIG. 5 is composed of similar circuits 310 to 330, inverters 501 and 502, buffers 503 and AND gates 504 and 505 shown in FIG. Figure 5 generates the intermediate signals + CANCEL-OP-RSBR0, + CANCEL-OP-RSBR1, and + CANCEL-OP-RSBRn. These signals indicate the next instruction that failed the branch prediction. + CANCEL—OP—R SBR0 is equal to the output of circuit 310. + CANCEL OP RSBR1 The result of the AND operation performed by the AND gate 504 using the signal obtained by inverting the output of the circuit 310 by the inverter 501 and the output of the circuit 320 as inputs. Similarly, + CANCEL—OP—RSBRn is calculated by the AND gate 505 and output.

FIG. 6 shows a circuit consisting of an RS flip-flop 601 that generates the + RE I FCH—TRG signal. + REIFCH—TRG of the output of the RS flip-flop 601 is set by a re-instruction fetch request (+ RSBR-REIFCH-REQ) input to the set terminal (S) of the RS flip-flop 601. The signal is input to the reset terminal (R) of the RS flip-flop 601 and is reset by a + CLEAR-PIPELINE signal. + CLEAR — The PIPELINE signal is a section pipeline tally command signal output by COMIT116.

FIG. 7 shows a circuit comprising an RS flip-flop 701 that generates a + RSBR_CANCEL—IF—ALL signal. Here, the symbol "ALL" indicates ID-0, 1, 2, 3, 4, 5. The + R SBR_CANCEL_IF — ALL signal of the output of the RS flip-flop 701 is input to the set terminal (S) of the RS flip-flop 701, output from the OR gate 340 in FIG. CANCEL—set by IF—ALL. On the other hand, the OR gate 702 is connected to the reset terminal (R) of the RS flip-flop 701. The three inputs of the OR gate 702 include a re-instruction fetch request (+ RSBR—RE I FCH_REQ), the + REI FCH—TRG signal output from the RS flip-flop 601 in FIG. 6, and the + CLEAR_PIPEL INE signal. Is entered. Then, one of the re-instruction fetch request (+ RSBR—RE I FCH—REQ) or the + RE I FCH—TRG signal or the + CLEAR—PI PEL INE signal output from the RS flip-flop 601 in FIG. At the time of ', the reset signal from the OR gate 702 is input to the reset terminal (R) of the RS flip-flop 701, and the + RSBR-CANCEL-IF-ALL signal is reset.

Figure 8 shows a two-input OR gate 801 and a two-input AND gate 802, +1 NH_E_VAL Indicates a circuit that outputs ID. The OR gate 801 calculates the logical sum of the + RE I FCH— TRG signal output from the RS flip-flop 601 in FIG. 6 and the + R SB R— CANCEL— IF_AL L signal output from the RS flip-flop 701 in FIG. The AND of the output of the OR gate 801 and the FLU SH_RS signal output by the COMITl 16 is calculated by the AND gate 802 to output + I NH-E-VAL ID. One FLUSH-RS signal is a negative logic signal of the + FLUSH-RS signal output from COMITl 16 in FIG. FIG. 9 shows a circuit configured by an RS flip-flop 901 and a two-input AND gate 902 to output + D-VAL ID. The output of the two-input AND gate 902 is connected to the set terminal (S) of the RS flip-flop 901. The 2-input AND gate 902 outputs the logical product of the + I NH _E_VAL ID negative logic I NH—E—VAL ID signal and the + E—VAL ID signal output from the AND gate 802 in FIG. The + D—VAL ID signal of the output of the RS flip-flop 901 is set by the output signal of the AND gate 902. + D— The VAL ID signal is a signal indicating the start of a decoding cycle, and is output from the instruction decoding unit 115 to the RSBR 114 and the COMITl 16. The + E-VALID signal is a signal indicating the timing of setting from the IBBUFER 112 to the DDECR 115.

FIG. 10 shows a circuit for generating a set signal of CANCEL-OP_ID [5: 0] + 3 × NCEL_OP_ID_5 [0]. The circuit shown in FIG. 10 includes two-input AND gates 1001 to 1007, a five-input OR gate 1010, 1011, and a two-input OR gate 1020.

The 2-input AND gate 1001 receives + CANCEL—OP—RSBR0 output from the inverter 503 in FIG. 5 and + RSBR0—IID_PL1 [5: 0] of the instruction ID (I ID). The + CANCEL_OP—RSBR 1 output from the 2-input AND gate 504 in FIG. 5 and the instruction ID + RSBR1—II D_P L 1 [5: 0] are input to the 2-input AND gate 1002. You. Also, the 2-input AND gate 1007 has + CANCEL OP RSBRn output from the 2-input AND gate 505 in FIG. 5 and + RSBRn IID of the instruction ID. PLl [5: 0] is input. Then, from the two-input OR gate 1020, the instruction ID of the next instruction of the branch instruction whose branch prediction has failed is output.

FIG. 11 shows a circuit configured to generate + CANCEL—OP—I ID—VAL ID formed by the RS flip-flop 1101. The set input terminal (S) of the RS flip-flop 1101 receives the SET—CANCEL—OP—IID—VAL ID output from the OR gate 340 in FIG. 4, and the + CANCEL—OP—IID — VAL ID signal is set. The + CLEAR-PIPE LINE signal is input to the reset input terminal (R) of the RS flip-flop 1101, and the + CANCEL-OP-IID-VALID signal is reset by this signal. + CLEAR—PIPELINE signal is a clear instruction signal of the ^ ff pipeline output by COMIT116.

FIG. 12 shows a circuit configured by the RS flip-flop 1201 and outputting + CANCEL_OP_ID [5: 0]. The SET—CANCEL—OP_I ID [5: 0] signal output from the OR gate 1020 in FIG. 10 is connected to the set terminal (S) of the RS flip-flop 1201. Thus, + CANC EL_0 P_IID [5 : 0] signal is set.

As described above, the control signals RSBR_CANCEL_IF—ID_0, 1, 2, 3, 4, 5, RSBR—RE I FCH—REQ, INH_E_VAL ID, CANCEL—OP—I ID—VAL ID, CANCEL-OP—I can generate I ID [5: 0].

Next, the timing of a signal generated according to the present invention will be described.

FIG. 13 is a diagram showing a timing chart of the conventional branch control. FIG. 14 is a diagram showing a timing chart of a signal generated according to the present invention. In FIG. 13, this signal indicates the start of a decoding cycle, and is output to the instruction decoding unit 115, the RSBR 114 and the COMITl 16, and (1) the cycle starts with the D-VAL ID signal. Then, as shown by the numbers (2) and (12), the above-mentioned signals for controlling the respective parts in FIG. 1 are generated.

In FIG. 14, signals denoted by the same reference numerals as those in FIG. 13 indicate the same signals. The signals indicated by the numbers (101) and (108) generated in accordance with the present invention correspond to those in FIG. 12 shows the signals generated by the circuit of the embodiment shown in FIGS.

From the above, the control signals R SBR_ CANCEL—IF—ID—0, 1, 2, 3, 4, 5, RSBR—REIFC H—REQ, and I NPi One E—VAL ID, CANCEL—OP—IID—VA LID, and CANCEL—OP—I ID [5: 0] can be generated. As a result, erroneous instruction fetch requests and operand requests can be suppressed or invalidated until a branch instruction is erroneously predicted and a re-instruction fetch request is issued to the memory.

Claims

Scope of request

1. an instruction fetch control unit that controls instructions so as to fetch an obscene instruction from a storage unit storing instructions,

An instruction buffer for temporarily storing an instruction supplied from the knitting memory;

An instruction decoder for decoding an instruction sent from the obscene instruction buffer, a branch instruction prediction unit for predicting an instruction branch,

A self-instruction fetch control unit, an it self-instruction buffer, a ttrt self-instruction decoder, and a stff self-branch prediction unit having a branch prediction control unit for controlling the self-branch instruction prediction unit. In order for the control unit to determine that the branch prediction by the self-branch instruction predicting unit is incorrect, the control unit determines that the branch prediction power by the branch instruction predicting unit is erroneous. Until the instruction buffer re-fetches the correct instruction from the self-storage unit, the self-branch prediction control unit outputs a signal for suppressing the instruction fetch request already output to the tiff self-storage unit to the iff self-instruction fetch. Output to the control unit and output a signal for invalidating the 151 own instruction buffer to the own instruction buffer.

2. The self-branch prediction control unit does not branch if the branch instruction predicted to branch by the self-branch instruction prediction unit does not branch, or if the branch instruction predicted to not branch by the unpleasant branch instruction prediction unit branches. The branch instruction prediction unit predicts that an instruction that is not a branch instruction will branch as if it were a branch instruction, or in the case of the branch instruction prediction, the branch prediction by the self-branch instruction prediction unit; The instruction control device according to claim 1, wherein the judgment is made as a single floor.

3. an instruction fetch control unit that executes instructions in an out-of-order manner, controls to fetch instructions from a storage unit that stores the instructions,

An instruction buffer for storing an instruction from the Ml self memory unit, an instruction decoder for decoding an instruction sent from the tfft self-instruction buffer buffer; a branch instruction prediction unit for predicting an instruction branch;

In a command device having a Slit self-instruction fetch control unit, a self-instruction buffer, a self-instruction decoder, and a branch prediction control unit for controlling a tiff self-branch instruction prediction unit,

には At the age at which the branch prediction control unit determines that the branch prediction by the key-self branch instruction prediction unit is incorrect, the unknowing branch prediction control unit determines that the unknowable branch instruction prediction unit Until the instruction buffer re-fetches the correct instruction from the self-storage unit after judging that the erroneous branch instruction prediction unit re-fetches the correct A signal for invalidating an operand request from an instruction to be executed is output to the edit memory unit, and a signal for disabling the edit instruction decoder is output to the disgusting instruction decoder. ^ Control devices.

4. The self-branch branch prediction control unit predicts that the branch instruction predicted to be known by the unpleasant branch instruction prediction unit will not branch, or that it will not branch by the unpleasant branch instruction prediction unit. The branch instruction predicted to branch or the branch instruction prediction unit predicts that the instruction is not a branch instruction, and the instruction predicts that the instruction will branch as if it were a branch instruction. 4. The instruction control device according to claim 3, wherein a branch destination address is erroneous, and it is determined that the branch prediction by the flit self-branch instruction predicting unit is erroneous for any of ^.

5. A method for fetching an instruction from a storage unit storing the instruction and controlling the instruction control device having a branch instruction prediction unit for predicting the branch of the instruction and a branch prediction control unit for performing the instruction in an out-of-order manner. And

The tiff self-branch prediction control unit has determined that the branch prediction by the key self-branch instruction prediction unit was incorrect ^ indicates that the tfft self-branch prediction control unit was incorrect in the branch prediction by the unpleasant branch instruction prediction unit. A step of suppressing an instruction fetch request that has already been output to the tfflS storage unit until the correct lay instruction is re-fetched from the tiff self storage unit after the determination, and invalidating the instruction already output from the storage unit. And controlling the instruction control device.

6. The return branch prediction control unit determines the age at which the branch instruction predicted to branch by the return branch instruction prediction unit does not branch, or branches the branch instruction predicted not to branch by the return branch instruction prediction unit. ^^ Or, if the instruction which is not a branch instruction is divided by the branch instruction prediction unit as if it is a branch instruction u ^, or tin the branch instruction predicted to be identified by the branch instruction prediction unit 6. The control method of the instruction control device according to claim 5, wherein, when the branch destination address is erroneous, it is determined that the branch prediction by the selfish branch instruction prediction unit is erroneous.

7. A method of fetching a disgusting instruction from a storage unit storing instructions and executing the instruction in an out-of-order manner, and controlling an instruction control device having a branch instruction prediction unit for predicting a branch of an instruction and a branch prediction control unit. So,

If the self-branch branch prediction control unit determines that the branch prediction by the unknowing branch instruction prediction unit was incorrect, then the unknowing branch prediction control unit determines that the branch prediction power by the leaky branch instruction prediction unit is incorrect. Between re-fetching the correct instruction from the hatred storage unit after determining that the operand request is invalid, and invalidating the operand request from the instruction that is about to be erroneously executed, and invalidating the instruction input to the execution pipeline. A method for controlling a life control device, comprising:

8. The unknowing branch prediction control unit determines whether the branch instruction predicted to branch by the self-branch instruction prediction unit does not branch, ^ ", or the branch instruction predicted not to branch by the tiff self-branch instruction prediction unit. Branch or the branch instruction prediction unit predicts that the instruction will not be a branch instruction, or that the instruction will branch as if it were a branch instruction, or that the self-branch branch instruction prediction, 8. The control method of the instruction control device according to claim 7, wherein a judgment is made that the prediction power is S error.