WO2004098052A1

WO2004098052A1 - Receiver circuit with adjustable if amplifier gain

Info

Publication number: WO2004098052A1
Application number: PCT/IB2004/001219
Authority: WO
Inventors: Alan Chin Leong Yeo; Adeline Chuu Ling Tan
Original assignee: Koninklijke Philips Electronics N. V.
Priority date: 2003-04-29
Filing date: 2004-04-22
Publication date: 2004-11-11

Abstract

The invention relates to a receiver circuit, a method for receiving a radio frequency signal and a tuner circuit for use in a receiver circuit. In the receiver circuit, a radio frequency signal is amplified by a first amplifier (20) of variable gain, controlled by an AGC voltage. The intermediate is then mixed in a mixer (22) down to an intermediate frequency. The intermediate frequency signal is amplified by a second amplifier assembly (24) and is then filtered by a SAW bandpass filter (26, 28) and demodulated by a demodulator circuit (30). To avoid detrimental effect on noise figure caused by high gain reduction in first amplifier (20), second amplifier assembly (24) can be switched between at least two states of different gain.

Description

Receiver circuit with adjustable IF amplifier gain

The invention relates to a receiver circuit, a tuner circuit and a method for receiving a radio frequency signal. More particularly, the invention relates to a receiver circuit adapted to receive radio frequency signals of both strong and weak signal level. Receiver circuits serve to receive radio frequency signals and to extract baseband signals contained therein. Such receiver circuits are used in all sorts of radio devices, specifically in TV applications.

TV receivers generally comprise a tuner circuit for receiving a radio frequency signal and for providing an intermediate frequency signal, a bandpass filter (typically an SAW filter, surface acoustic wave) and a demodulator circuit for providing a baseband signal. The tuner circuit comprises a pre-amplifier for amplifying the received radio frequency signal, a mixer for mixing the radio frequency signal to an intermediate frequency signal, and a second amplifier to amplify said intermediate frequency signal.

In order to process radio frequency signals of different signal levels, an AGC (Automatic Gain Control) mechanism is known. The demodulator circuit provides an AGC voltage to the tuner. The pre-amplifier within the tuner has a gain which is controllable by said AGC voltage. Thus, for a radio frequency signal of weak signal level, the pre-amplifier in the tuner is operated at full gain. For a signal of strong signal level, the demodulator circuit provides an AGC voltage which reduces the pre-amplifier gain.

US 4,209,805 shows a TV receiver circuit. Here, a radio frequency signal is received by a first unit designated as a tuner. This unit outputs an intermediate frequency signal, which is subsequently amplified in a unit designated IF amplifier. The signal output by the IF amplifier is processed in a video detection circuit of synchronous type. From the signal output, an AGC unit provides two AGC signals, one AGC signal to adjust the gain of the IF amplifier, and a second RS AGC signal to adjust the gain of the tuner. It is not explained where bandpass filtering is effected in this chain, if at all.

While the automatic gain control mechanism integrated in today's receiver circuits allows processing of signals with both strong and week signal level, there are also problems associated with automatic gain control. The inventors have recognized that for a signal of high signal level, where gain reduction is effected in pre-amplifier of tuner, the effect on noise figure is highly detrimental.

It is therefore the object of the invention to provide a receiver circuit and method for receiving radio frequency signals of both higher and lower signal levels, where the noise figure is low in both case.

This object is achieved by a receiver circuit according to claim 1, a tuner circuit according to claim 8 and a method according to claim 8. Dependent claims refer to preferred embodiments of the invention.

In the tuner and receiver circuits according to the invention, there is a second amplifier assembly that is switchable between at least two states of different gain. This amplifier assembly is arranged in the signal chain preferably directly after the mixer. Also, preferably, it is arranged directly before the bandpass filter which is typically implemented as a SAW filter.

The second amplifier assembly according to the invention has switchable gain. The amplifier assembly can be switchable between a plurality of states, where the gain of said states preferably differs by at least 3 dB. In a case with only two stages, the gain difference is preferably more than 6 dB. Switching the second amplifier assembly between states of different gain can be used in parallel with the AGC mechanism controlling the gain of the first amplifier. In the case of strong signals, it has proven to be advantageous to reduce the total gain within the receiver circuit at the second amplifier assembly, rather than employing high gain reduction at the first amplifier. In this way, the total noise figure is lower. There are several ways how switching can be controlled. The signal level can be determined at one of multiple locations (e. g. before or after the mixer, before or after the second amplifier assembly, before or after the bandpass filter) and switching can then be effected accordingly.

According to a preferred embodiment of the invention, the filtered intermediate frequency signal exiting from the bandpass filter is provided to a demodulator circuit.

This demodulator circuit demodulates the signal and provides a baseband signal. The demodulator circuit comprises means for determining a signal level of the received signal, and for providing a switching signal to the second amplifier assembly. In case of a high signal level, a signal is provided to switch the second amplifier assembly to a state of lower gain. In case of a low signal level, the second amplifier assembly is switched to a state of higher gain. In case there are more than two states switchable for the second amplifier assembly, the demodulator circuit provides a corresponding switch signal in accordance with the signal level. It should be noted that the signal level referred to here is preferably determined by taking into account the present levels of

AGC voltage as well as the present switching state of the second amplifier assembly.

Actually, the means for determining a signal level can exclusively rely on AGC voltage, such that switching of the second amplifier assembly to a state of lower gain is effected if the AGC voltage is below a predetermined threshold (i. e. if gain reduction in the first amplifier is above a predetermined threshold).

The switch signal provided to the second amplifier assembly is preferably an I C signal provided to an I²C transceiver that is part of the second amplifier assembly. This is advantageous in cases where tuner ICs or demodulator ICs are used which already include I²C capability. Alternatively, however, it is also possible to use a logic pin to control switching state of the second amplifier assembly.

Preferably, switching of the second amplifier assembly is effected once when the channel is changed. It is possible to control switching by storing in advance, for each channel, the amplifier assembly state adapted to the signal strength of the particular channel.

According to an embodiment of the invention, the first amplifier, the mixer and the second amplifier assembly are part of an integrated circuit. For TV receiver applications it is known to provide a tuner circuit, which is a hybrid integrated circuit comprising a pre-amplifier, mixer-oscillator-PLL and second (IF) amplifier as well as, preferably, input filters, bandpass filters and further circuitry. The switchable gain second amplifier assembly can be implemented as part of such an integrated tuner circuit.

It is possible to implement the second amplifier assembly as a constant gain amplifier and as switchable gain reduction unit. In a preferred embodiment of the invention, the second amplifier is a constant gain amplifier which is part of an integrated tuner circuit, and the gain reduction unit is a circuit comprised of discrete parts, which can selectively attenuate the signal delivered by the integrated tuner circuit.

The tuner circuit according to the invention comprises a second amplifier assembly switchable between at least two states of different gain. The tuner circuit can be implemented with one or more integrated circuits. In the following, embodiments of the invention will be explained with reference to the drawings. In the drawings,

fig. 1 shows a symbolic schematic drawing of a receiver circuit; fig. 2 is as symbolic schematic drawing of a tuner circuit; fig. 3 is a symbolic schematic drawing of a demodulator; fig. 4 is a diagram showing the dependence of noise figure on gain reduction; fig. 5 is a diagram showing the dependence of S/N ratio on gain reduction; fig. 6 is a schematic drawing of a tuner circuit and a first embodiment of a gain reduction unit; fig. 7 is a schematic drawing of tuner circuit and a second embodiment of a gain reduction unit; fig. 8 is a schematic drawing of a third embodiment of a tuner circuit and a gain reduction unit; fig. 9 is a flow diagram.

In fig. 1, there is shown a schematic representation of a receiver circuit. The receiver circuit receives a radio frequency (RF) signal, e.g. from an antenna 14, at an input terminal 12. At output terminals 16, the receiver circuit outputs baseband signals, namely a CVBS (composite video baseband signal) and a baseband mono audio signal.

It should be clear to the skilled person that the receiver circuit of fig. 1 is only shown here as an example. Of course, receiver circuits can be implemented differently. Also, a circuit may comprise additional circuiting not shown here.

The main components of the receiver circuit 10 are a pre-amplifier 20 of adjustable gain, a mixer/oscillator 22, an IF amplifier assembly 24, SAW bandpass filters 26, 28 and a PLL IF demodulator 30. Further, receiver 10 comprises a high-pass filter 32, an IF trap 34, an input filter 36 and a bandpass filter 38. With the exception of IF amplifier assembly 24 these components are known per se in the context of TV receivers. Therefore, the specific implementation of the units will not be discussed.

The signal chain is such that a RF signal received at input terminal 12 is first filtered by high-pass filter 32, IF trap 34 and input filter 36.

The signal is than amplified by pre-amplifier 20, which is implemented using FETs. The gain of pre-amplifier 20 is controllable via an automatic gain control (AGC) voltage provided by PLL IF demodulator 30.

The pre-amplified signal, after being filtered by bandpass filter 38, is then in mixer/oscillator PLL 22 mixed down to an intermediate frequency (IF) signal. The IF signal is amplified by IF amplifier assembly 24 and then filtered by video SAW 26 and sound SAW 28. This implementation with two SAW filters 26, 28 in parallel corresponds to the Quasi Split-Sound (QSS) concept. Alternatively, a receiver circuit can be implemented as an inter-carrier structure with only one SAW filter. The filtered sound and video IF signal is fed to PLL IF demodulator 30 to be demodulated to output basement signals at output terminal 16. PLL IF demodulator 30, which is explained before in greater detail, provides an AGC voltage signal to pre-amplifier 20 to adjust the gain of pre-amplifier 20. In the example shown, the AGC voltage has negative polarity. To drive pre-amplifier 20 to maximum gain, the AGC voltage will be at a maximum. To reduce gain, lower AGC voltages are applied.

The AGC mechanism allows for PLL IF demodulator to process signals at a nominal signal level, regardless of the actual signal level received. However, there are some drawbacks to this mechanism. The variable gain stage 20 provides a relatively low noise figure and moderate gain under nominal setting. In the case of a weak signal, when amplifier 20 operates at maximum gain, the S/N (signal-to-noise) ratio is determined largely by the noise figure of the tuner, and only to a small extend by the gain. Put in a simple way, if the noise figure is poor, no amount of gain will improve the S/N ratio of the modulated signal.

When a strong signal is received and the PLL IF demodulator 30 provides a corresponding low AGC voltage, such that a large gain reduction is effected in amplifier 20, the effect on noise figure is highly detrimental.

Fig. 4 and fig. 5 show the effect of gain reduction on noise figure (fig. 4) and S/N ratio (fig. 5). While at full gain of amplifier 20, the noise figure is at only about 7 dB, already 10 dB of gain reduction raise the noise figure to 16 dB. As shown in fig. 4, for a specific signal the S/N ratio degrades rapidly with increased gain reduction. The above noted effects lead to the problem, that when receiving weak signals, tuner gain should be as high as possible. However, for signals of higher signal level, a tuner with higher gain will have to effect more gain reduction. Since gain reduction results in a rapidly worsening noise figure, this in turn results in poor S/N performance of the demodulated signal. Therefore, in receiver 10 of fig. 1, second amplifier assembly 24 is switchable between two states. PLL IF demodulator 30 provides a switching signal SW to amplifier assembly 24. Via the switching signal SW, amplifier assembly 24 can be switched between two states, where the gain between the two states differs by at least 3 dB. For example, the first state would include a fixed gain of 25 dB, and the second state would include a fixed gain of 15 dB.

Fig. 3 shows demodulator circuit 30 in greater detail. Demodulator circuit 30 comprises a signal level detection unit 46 and a demodulator unit 44. Demodulation unit 44 demodulates the IF signal and provides baseband signals. The signal level detection unit 46 detects the level of the incoming IF signal. If the signal level is above a talce- over point (TOP), an AGC voltage is generated such that gain of pre-amplifier 20 is reduced. For example, if TOP is at 105 dBμ, any signal level above this value leads to gain reduction in pre-amplifier 20. Also unit 46 provides a switching signal to tuner 40 corresponding to the signal level, the actual switching state of amplifier assembly 24 and the present AGC voltage. An example for the function of unit 46 will be discussed in detail with reference to fig. 9.

If a weak signal is received at antenna 14, demodulator 30 provides an AGC voltage signal to amplifier 20 so that it operates at maximum gain. Also, a switch signal SW is provided to IF amplifier assembly 24, so that it is switched into the first state, which has a higher gain. Thus, in the case of a week signal, no gain reduction is effected and there is no adverse effect on noise figure.

In the case of reception of a strong signal, IF receiver 30 would normally effect a large amount of gain reduction. Instead, a switch signal S W is provided to IF amplifier assembly 24 so that it is switched into the second state. In the second state, IF amplifier 24 has a lower gain. Thus, the signal received at demodulator 30 has a lower signal level. Only a small amount of gain reduction needs to be effected in amplifier 20, thus, the highly detrimental effect of high gain reduction (fig. 4, fig. 5) is avoided. In the example shown, unit 46 provides the switch signal according to AGC voltage. In this case is proposed to only set the switching state of IF amplifier assembly 24 once after changing to a specific channel. Otherwise, the result could be constant switching between states. The algorithm implemented by unit 46 to determine the appropriate switching state is shown in Fig. 9: The algorithm is started upon channel charge. First, the IF amplifier assembly is set to a first switching state with higher gain. The AGC mechanism then, in a manner known per se, provides an AGC voltage adapted to receive the IF signal at nominal level. The AGC voltage signal V_AGC is read back and compared to a threshold value V_AGC,_TII- If V_AGC < V_AGC, _TI_I , i-e. if gain reduction in pre-amplifier 20 is effected beyond a predetermined threshold, then a switch signal is created to switch IF amplifier assembly to a second switching state with reduced gain.

In an alternative embodiment (not shown in the figures), the appropriate switching state of IF amplifier assembly 24 is in advance determined for each channel, stored in a memory, and recalled upon channel switching. In this alternative embodiment, during installation, an automatic search of every available channel is performed. Such an "auto search" function is know per se, where every channel is tuned. According to the embodiment, auto search is done with IF amplifier assembly 24 set to first state (higher gain). As every channel is tuned to, the resulting AGC voltage level is measured and compared to a pre-determined threshold V_AGC._TII- A flag is set indicating if the AGC voltage is above or below the threshold. This flag corresponds to the appropriate switching state of the second amplifier assembly 24 (e.g. 0=first state, higher gain; l=second state, lower gain). The channel data, including the flag which only uses one bit, is stored in the TV set Non-Volatile-Memory (NVM). Then, in operation of the TV set, when a channel is recalled, the IF gain is set based on the bit value stored in the NVM.

In fig. 1 the subsystems of receiver circuit 10 are shown as functional blocks only. Fig. 2 shows a tuner circuit 40, which is a hybrid integrated circuit incorporating some of the units from fig. 1. Tuner circuit 40 comprises pre-filters 32, 34, tracking filters 36, 38, pre-amplifier 20, mixer/oscillator 23 and IF amplifier assembly 24. IF amplifier assembly 24 can be switched between the different states via a switching signal provided as an I²C signal provided to a terminal of integrated circuit 40. As shown in fig. 2, tuner 40 further comprises a PLL circuit 42 to drive tracking filters 36, 38. Since the corresponding tuner design is known per se to the skilled person, the details of tuner 40 will not be further explained. It should be noted, however, that IF amplifier assembly 24, switchable between two states, is part of integrated circuit 40.

In the above embodiment of fig. 2, IF amplifier assembly 24 was shown as part of integrated tuner circuit 40. Alternatively, IF amplifier assembly 24 can be implemented as shown in fig. 6, 7 and 8. In these embodiments, IF amplifier assembly 24 includes an IF amplifier 66 of fixed gain. This amplifier is part of an integrated tuner circuit 60. Such tuner circuits with fixed-gain IF amplifier are available today.

As a second part of IF amplifier assembly 24 according to the embodiments of fig. 6, 7 and 8, there is provided a switchable gain reduction unit 62. The gain reduction unit 62 comprises an I²C transceiver 64, which controls a switch according to commands received via an I²C bus.

In the second embodiment according to fig. 6, gain reduction unit 62 comprises a capacity CI and an inductance LI connected in series to IF output of tuner circuit 60. A resistor Rl connected to ground can be selectively connected or disconnected to the junction between CI and LI by a switch SI.

In the first state of gain reduction unit 62, SI is open. The series circuit of CI and LI leads to no gain reduction of the IF signal.

In the second state of gain reduction unit 62, SI is closed. The connection to ground via Rl leads to attenuation of the IF signal, and therefore to a reduction of the total gain from the fixed gain amplifier within integrated circuit 60 and gain reduction unit 62. In the third embodiment according to fig. 7, the gain reduction unit 62 comprises a resistor R2 connected within the signal chain. R2 is connected in series with a capacity C2 and an inductance L2. R2 can be selectively bridged by a switch S2. In the first state of gain reduction unit 62 according to fig. 7, S2 is closed and R2 therefore has no effect. In the second state, S2 is open and R2 leads to attenuation, effecting reduced gain of the amplifier assembly.

In the third embodiment according to fig. 8, tuner circuit 60 has a balanced output, where two IF signals are available which are 180° out of phase, IFoutl and IFout2. If the resulting voltage taken differentially between IFoutl and IFout2 is, say, V then the individual voltages of IFoutl and IFout2 with reference to ground would be Vi V and -^lΛ V, respectively.

Outputs IF out 1 and IF out 2 are coupled via capacities C3, C4 to the coils L3, L4 of a transformer. Coil L4 of the transformer is grounded. The transformer has its windings turned in a way such that the current flowing through L4 in response to the applied voltage -Vτ V at IFout2 will induce a voltage almost equal to Vz V in L3.

Connection of IFout2 to coil L4 switchable via switch S3. IF S3 is closed, the balanced output is converted to an unbalanced output at the other terminal of coil L3 by adding up the signal voltages of IFoutl and IFout2. So in this state, no gain reduction is effected. IF S3 is open, no voltage will be induced in L3 from output IFout2. This leads to a theoretical halving of signal voltage (-6 dB). In reality, because of intrinsic capacitances, gain reduction will be about -4 dB.

In the above shown embodiments, the gain reduction unit 62 is switchable between only two states. In an alternative embodiment (not shown), there can be three or more states. The states each covers steps of about 3 dB. With a corresponding switching signal from demodulator 30, the maximum values for AGC voltage, and therefore gain reduction, can be further reduced.

Claims

CLAIMS:

1. Receiver circuit (10), comprising a radio frequency input (12) to provide a radio frequency signal, a first amplifier (20) to amplify said radio frequency signal and to provide an amplified radio frequency signal, said first amplifier (20) having variable gain, a mixer (22) for mixing said amplified radio frequency signal to an intermediate frequency signal, and a second amplifier assembly (24) to amplify said intermediate frequency signal and to provide an amplified intermediate frequency signal, said second amplifier assembly (24) being switchable between at least two states of different gain, and at least one bandpass filter (26, 28) to filter said amplified intermediate frequency signal and to provide a filtered intermediate frequency signal.

2. Circuit according to claim 1, further comprising - a demodulator circuit (30) to demodulate said filtered intermediate frequency signal to provide a baseband signal, said demodulator circuit (30) comprising means (46) for determining a signal level, where said demodulator circuit (30) provides a switch signal (SW) to said second amplifier assembly (24), such that said second amplifier assembly is switched to a state of lower gain if the signal level is high, and to a state of higher gain, if the signal level is low.

3. Circuit according to one of the preceding claims, where said first amplifier (20), said mixer (22) and said second amplifier assembly (24) are part of an integrated circuit.

4. Circuit according to one ofthe preceding claims, where said second amplifier assembly (24) comprises a constant gain amplifier, and a gain reduction unit (62), said gain reduction unit (62) being electronically switchable between at least two states, where the gain reduction in the two states is different.

5. Circuit according to claim 4, where said first amplifier (20), said constant gain amplifier and said mixer (22) are part of an integrated circuit (60), - and said gain reduction unit (62) is comprised of discrete parts.

6. Circuit according to one ofthe preceding claims, where said second amplifier assembly (24) includes an I²C-transceiver (64), configured such that responsive to commands at an I²C input, switching between said states of different gain is effected.

7. Circuit according to one ofthe preceding claims, where said second amplifier assembly (24) is switchable between a plurality of states of different gain, - where the gain of said states differs by at least 3dB between said states.

8. Tuner circuit (40) for use in the above receiver circuit, comprising a radio frequency input to provide a radio frequency signal a first amplifier (20) to amplify said radio frequency signal and to provide an amplified radio frequency signal, said first amplifier (20) having variable gain, a mixer (22) for mixing said amplified radio frequency signal to an intermediate frequency signal, and a second amplifier assembly (24) to amplify said intermediate frequency signal and to provide an amplified intermediate frequency signal, said second amplifier assembly (24) being switchable between at least two states of different gain.

9. Method for receiving a radio frequency signal, where said radio frequency signal is amplified by a first amplifier (20), - and is then mixed down to an intermediate frequency, and is then further amplified by a second amplifier assembly (24), and is then filtered by at least one bandpass filter (26, 28), where said second amplifier assembly (24) is switched between at least two states, such that for a signal of a higher signal level the second amplifier assembly (24) is in a state with lower gain, and that for a signal of lower signal level, the second amplifier assembly is in a state with higher gain.