WO2004097689A1 - Profilage d'activite permettant de controler le fonctionnement d'un circuit integre - Google Patents

Profilage d'activite permettant de controler le fonctionnement d'un circuit integre Download PDF

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Publication number
WO2004097689A1
WO2004097689A1 PCT/IB2004/050514 IB2004050514W WO2004097689A1 WO 2004097689 A1 WO2004097689 A1 WO 2004097689A1 IB 2004050514 W IB2004050514 W IB 2004050514W WO 2004097689 A1 WO2004097689 A1 WO 2004097689A1
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WO
WIPO (PCT)
Prior art keywords
activity
simulated
estimated
integrated circuit
difference
Prior art date
Application number
PCT/IB2004/050514
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English (en)
Inventor
Francesco Pessolano
Jose D. J. Pineda De Gyvez
Rohini Krishnan
Original Assignee
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Publication of WO2004097689A1 publication Critical patent/WO2004097689A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power

Definitions

  • This invention relates to activity profiling for use in the control of working conditions of an integrated circuit, or part of it, in order to optimize its performance.
  • SoC system on a chip
  • Power is dissipated in a circuit whenever a cell instance switches a signal from one voltage level to another.
  • This switch in voltage level causes charging or discharging of capacitances which include pin capacitances, interconnect capacitances, and transistor capacitances (e.g. coupling capacitances distributed between the gate and source/drain terminals).
  • capacitances include pin capacitances, interconnect capacitances, and transistor capacitances (e.g. coupling capacitances distributed between the gate and source/drain terminals).
  • capacitive feedthrough effects also impact power loss.
  • due to level shifters, leakage currents, pull-ups and pull-downs power also dissipates statically when the circuit is in quiescent mode.
  • simple power consumption models which consider only the charging and discharging of the gate output capacitance, have been used.
  • this information can be used to modify the chip operating conditions (i.e. voltage and frequency) so as to ensure that the chip (module) is always working with the minimum required performance, thereby enabling power consumption to be optimized and tailored to whatever application is currently running on the chip.
  • the hardware itself monitors its activity and performs the control. In this case, however, the control action is based on what has already happened on the chip (or module) and may bear no relation to what is happening in real-time.
  • These power-coefficients provide a mechanism to capture the different power consumption dependencies under varying state-vector conditions, input ramp and output load for different types of cells.
  • the coefficients are used during simulation to compute the power consumed by the cell under applicable state-vector and circuit-conditions to which each cell instance is subjected in the circuit.
  • control action is never actually based on the real behavior of the chip (module), only the simulated, estimated or expected behavior thereof.
  • apparatus for controlling integrated circuit operation comprising: i) means for receiving data representative of simulated or estimated integrated circuit activity for an operation thereof; ii) control means for controlling one or more parameters of an operation of said integrated circuit based on said simulated or estimated activity; the apparatus being characterized by: iii) means for measuring integrated circuit activity during operation thereof; and iv) means for comparing said measured activity with said simulated or estimated activity and, and if a difference therebetween (or a difference greater than or equal to a predetermined threshold value) is detected, adjusting or replacing said simulated or estimated activity accordingly, to produce an operation control activity signal; said control means being arranged to control one or more parameters of an operation of said integrated circuit based on said operation control activity signal.
  • a method for controlling integrated circuit operation comprising the steps of: i) generating or receiving simulated or estimated integrated circuit activity for an operation thereof; and ii) controlling one or more parameters of an operation of said integrated circuit based on said simulated or estimated activity; the method being characterized by the steps of: iii) measuring integrated circuit activity during an operation thereof; iv) comparing said simulated or estimated activity with said measured activity, and, if a difference therebetween (or a difference greater than or equal to a predetermined threshold value) is detected, adjusting or replacing said simulated or estimated activity accordingly to produce an operation control activity signal; and v) controlling one or more parameters of an operation of said integrated circuit based on said operation control activity signal.
  • the present invention further extends to an operation control activity signal created using the above-defined apparatus or method.
  • the present invention combines the use of control hardware and simulation software to achieve improved control over the prior art arrangements.
  • the software may provide estimated information to the hardware.
  • the hardware compares the estimated information with information it has measured, and the result of the comparison could then be used to adjust the estimated information before the adjusted estimated information (i.e. the resultant operation control activity signal) is used to effect chip control.
  • the apparatus may include means for generating the simulated or estimated integrated circuit activity.
  • Such means is preferably provided as software (e.g. a CAD tool) separate from the integrated circuit.
  • the control means is preferably provided as hardware on the integrated circuit itself. In the case where the simulated or estimated activity is adjusted to produce the operation control activity circuit, such adjustment may be achieved by adding an offset value which may be equal to or proportional to the difference between the simulated or estimated activity and the measured activity.
  • the simulated or estimated activity may be replaced by the measured activity or a value proportional or derived therefrom.
  • the simulated or estimated activity may be replaced or adjusted according to an entry in a look-up table.
  • Means may be provided for storing the simulated or estimated activity, and means may also be provided for encoding the simulated or estimated activity prior to storage thereof.
  • Figure 1 is a schematic flow chart representative of a method of estimating chip activity for use in an exemplary embodiment of the present invention
  • Figure 2 is a schematic flow diagram representative of a method of chip control according to an exemplary embodiment of the present invention
  • Figure 3 is a schematic block diagram of control hardware according to an exemplary embodiment of the present invention
  • Figure 4 is a schematic block diagram of control hardware according to another exemplary embodiment of the present invention.
  • Figure 5 is schematic block diagram of control hardware according to yet another exemplary embodiment of the present invention.
  • FIG. 1 of the drawings there is illustrated an exemplary method of generating simulated or estimated switching activity for use in an embodiment of the present invention.
  • a method would be familiar to a person skilled in the art and will not be described in great detail herein.
  • software can be provided to generate estimation activity, in which, first, the application and hardware description language (HDL) description of the chip (module) after synthesis are compiled (at steps 100, 102 respectively).
  • the chip (module) is then simulated (at step 104) with this application, and a profile generated.
  • Such profile is subsequently used by (known) power estimation tools to provide information about the switching activity for every operation of which the application is composed (step 106).
  • This information is then encoded at step 108 (in any known manner, such as, for example, by means of a numeric value) and stored (at step 110) such that it can be retrieved by the hardware (for example, in the application itself).
  • the above-described process can be modified in a number of different ways to achieve the same outcome, namely an activity estimation that can be retrieved by the hardware.
  • a group of operations may be used for the estimation, instead of the estimation step being performed for each individual operation.
  • the resultant value may be attached to each operation of the group or to just the group itself. This may affect the scope of control as well, in the sense that control may be effected in respect of each individual operation or in respect of a group of operations.
  • the estimation activity can be encoded, in the sense that its numerical value can be used, or a value relative thereto (for example, a previous value), or solutions such as fuzzy logic may be employed.
  • Storage of the information may be effected. For example, by attaching the activity estimation to each instruction with a dedicated instruction field, or to a group with a dedicated instruction, or with a separate parallel program, or otherwise.
  • the activity estimation may involve repetitive simulations with different applications and/or input patterns to generate a weighted estimation, if desired.
  • Many other permutations and variations will be apparent to a person skilled in the art, provided the end result is that the software has produced an activity estimation that the hardware can retrieve.
  • the hardware of such an exemplary embodiment may operate as illustrated in the flow diagram of Figure 2 of the drawings. For every clock period (or cycle), the hardware retrieves (at step 200) the activity estimation for the next operation. This value may be adjusted (at step 202) with an offset previously calculated which is intended to correct the estimation so as to correspond with real, monitored activity of the chip. This value (i.e.
  • the estimation value with the offset is used (at step 204) to control the chip (module) as it is considered to better represent the activity of the next operation.
  • the activity of the chip is also measured at step 206, and this value is then used to generate an average of the activity of all previous operations (step 208).
  • the measured average and the estimated one are compared so as to determine how accurate the estimate was, and an adjusting offset may be generated (at step 212) which is the difference between the two compared values.
  • the above-described hardware embodiment may be modified in a number of ways, including, for example, performing each step for a group of operations instead of for each individual operation.
  • FIG. 3 of the drawings a schematic block diagram of an exemplary embodiment of hardware for performing a method, such as that described with reference to Figure 2 of the drawings, is illustrated.
  • the hardware comprises a controller 300 for receiving the activity code (from the software), a core 302 (of the chip or module) for receiving input signals and generating output signals upon application of a set of signals forming an operation, and average activity monitor 304 for monitoring the real-time activity of the core 302 and generating an average thereof, an analogue-to-digital converter 306 for converting the output of the average activity monitor 304 into a digital signal for application to a comparator 308.
  • the comparator 308 compares the average activity value with the average estimated activity value and generates an offset corresponding to the difference therebetween. The offset is then fed back to the controller 300.
  • An activity monitor is basically a unit that measures the difference between the previous state of a system and the current one for the same system. The larger the difference, the greater is the system activity.
  • Another possibility is to monitor the input and output of every flip-flop in the system. When inputs and outputs differ, there is activity.
  • An activity monitor could also be built from here in a way that is obvious to the skilled in the art.
  • the present invention can be used to augment the static profile mechanism (i.e. the use of simulation software to produce estimated activity values for use in controlling a chip or module) by using activity monitoring information (obtained in real time).
  • activity monitoring information obtained in real time.
  • the system is being controlled by information statically provided by the application to the hardware. Such information is a representation of how much activity is involved in the operation of the hardware units of the chip (module).
  • the hardware itself measures the average activity and checks that this value corresponds (possibly within certain limits) with the value provided by the application. If this is not the case, the profile information used to control the hardware may be discarded, augmented or replaced.
  • the statistical information is disregarded and average measured activity is used instead to control the chip (module).
  • the statistical information may be augmented - i.e. the difference between the average measured activity and estimated profile information may be used as an offset to all subsequent profile information until a new error is detected.
  • a correspondence (look-up) table may be provided for use in the event that the estimated activity value does not correspond with the measured activity value.
  • the look-up table may contain a new activity value for a given application point (in respect of a given scenario) for use in controlling the chip or module (for example, such a new value may comprise the average measured activity).
  • This type of table may also be used for instruction types instead of application points, as required.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

L'invention concerne un appareil et un procédé permettant de contrôler le fonctionnement d'un circuit intégré, comportant un logiciel pour générer une activité simulée ou estimée, et des moyens de contrôle matériel pour contrôler l'activité en temps réel du circuit intégré. Pour chaque période d'horloge, le matériel recherche (200) l'estimation d'activité pour l'opération suivante. Cette valeur peut être ajustée (202) avec un décalage préalablement calculé qui est destiné à corriger l'estimation de manière à la faire concorder avec l'activité contrôlée réelle de la puce. Cette valeur, (c'est-à-dire la valeur d'estimation avec le décalage), sert (204) à contrôler la puce (module) car elle est censée mieux représenter l'activité de l'opération suivante. Lorsque l'opération suivante est en cours d'exécution, l'activité de la puce est également mesurée (206), et cette valeur sert ensuite à générer une moyenne de l'activité de toutes les opérations précédentes (208). La moyenne mesurée et la moyenne estimée sont comparées (210) de manière à déterminer le degré de précision de l'estimation, et un décalage d'ajustement peut être généré (212), ce décalage représentant la différence entre les deux valeurs comparées.
PCT/IB2004/050514 2003-04-28 2004-04-26 Profilage d'activite permettant de controler le fonctionnement d'un circuit integre WO2004097689A1 (fr)

Applications Claiming Priority (2)

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EP03101155 2003-04-28
EA03101155.4 2003-04-28

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006024747A1 (de) * 2006-05-26 2007-11-29 Offis E.V. Verfahren und Vorrichtung zur Optimierung des Stromverbrauchs einer Datenverarbeitungseinrichtung
EP1677175A3 (fr) * 2004-12-31 2011-05-04 STMicroelectronics Pvt. Ltd. Gestion d énergie dynamique dans un système sur une puce

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838947A (en) * 1996-04-02 1998-11-17 Synopsys, Inc. Modeling, characterization and simulation of integrated circuit power behavior
US5887179A (en) * 1996-06-11 1999-03-23 Motorola, Inc. System power saving means and method
EP1182556A2 (fr) * 2000-08-21 2002-02-27 Texas Instruments France Etablissement de profil et débogage adaptatif basés sur des tâches
US20020194515A1 (en) * 1991-12-17 2002-12-19 Compaq Information Technologies Group, L.P. A Delaware Corporation Utilization-based power management of a clocked device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020194515A1 (en) * 1991-12-17 2002-12-19 Compaq Information Technologies Group, L.P. A Delaware Corporation Utilization-based power management of a clocked device
US5838947A (en) * 1996-04-02 1998-11-17 Synopsys, Inc. Modeling, characterization and simulation of integrated circuit power behavior
US5887179A (en) * 1996-06-11 1999-03-23 Motorola, Inc. System power saving means and method
EP1182556A2 (fr) * 2000-08-21 2002-02-27 Texas Instruments France Etablissement de profil et débogage adaptatif basés sur des tâches

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1677175A3 (fr) * 2004-12-31 2011-05-04 STMicroelectronics Pvt. Ltd. Gestion d énergie dynamique dans un système sur une puce
DE102006024747A1 (de) * 2006-05-26 2007-11-29 Offis E.V. Verfahren und Vorrichtung zur Optimierung des Stromverbrauchs einer Datenverarbeitungseinrichtung
DE102006024747B4 (de) * 2006-05-26 2011-07-28 OFFIS e.V., 26121 Verfahren und Vorrichtung zur Optimierung des Stromverbrauchs einer Datenverarbeitungseinrichtung

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