WO2004095565A1 - Semiconductor device comprising extensions produced from material with a low melting point - Google Patents
Semiconductor device comprising extensions produced from material with a low melting point Download PDFInfo
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- WO2004095565A1 WO2004095565A1 PCT/IB2004/001254 IB2004001254W WO2004095565A1 WO 2004095565 A1 WO2004095565 A1 WO 2004095565A1 IB 2004001254 W IB2004001254 W IB 2004001254W WO 2004095565 A1 WO2004095565 A1 WO 2004095565A1
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- WIPO (PCT)
- Prior art keywords
- substrate
- portions
- gate electrode
- melting point
- insulating layer
- Prior art date
Links
- 239000000463 material Substances 0.000 title claims abstract description 76
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 230000008018 melting Effects 0.000 title claims abstract description 20
- 238000002844 melting Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 125000006850 spacer group Chemical group 0.000 claims abstract description 22
- 239000000969 carrier Substances 0.000 claims description 21
- 238000005538 encapsulation Methods 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 7
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- 230000005855 radiation Effects 0.000 claims description 4
- 229910000927 Ge alloy Inorganic materials 0.000 claims description 3
- 229910000676 Si alloy Inorganic materials 0.000 claims description 3
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 claims 1
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 238000010438 heat treatment Methods 0.000 description 10
- 238000002513 implantation Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 239000003153 chemical reaction reagent Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000021615 conjugation Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000001534 heteroepitaxy Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Definitions
- the present invention relates to a semiconductor device produced on the surface of a substrate, comprising extensions of a special type. It applies in particular to a field effect transistor, produced according to MOS ("Metal Oxide Semiconductor") technology.
- MOS Metal Oxide Semiconductor
- tip regions in English
- LDD Low Doped Drain
- LDD Low Doped Drain
- LDD Low Doped Drain
- They are parts of the source and drain regions of an MOS transistor, situated close to the respective ends of a channel disposed between the source and the drain. They extend to a shallow depth below the surface of the substrate which carries the transistor, as far as approximately 50 nanometers. They are in general implanted during a specific step, performed with a low-energy implantation beam. They have a conduction type identical to that of the source and drain regions, with concentrations of electrical carriers which are lower than those of the source and drain regions.
- the tip regions allow precise control of the electrical conduction of the source and drain regions at the ends of the channel. It is then possible to obtain a high level of reproducibility of the operating characteristics of mass- produced MOS transistors.
- These portions are used as sources of doping elements for the formation of the tip regions.
- These doping elements diffuse in the substrate during a specific heating in order to confer the required electrical behavior on the tip regions.
- the temperature during heating must be between 800°C and 1000°C in order to cause effective diffusion of these doping elements and thus confer on the tip regions the required concentration of electrical carriers.
- this high temperature causes locally a melting of the materials at the interface between the silicon substrate and insulating parts disposed around each transistor, known by the acronym STI (standing for "Shallow Trench Insulator") in the jargon of persons skilled in the art. It also causes a deformation of the gate electrode of the MOS transistors.
- One aim of the present invention is to propose a semiconductor device of a novel type, comprising tip regions compatible with a high level of integration, and which does not have the aforementioned drawbacks.
- the invention relates to a semiconductor device comprising a gate electrode and a gate insulating layer produced on part of the surface of a substrate in a first semiconductor material.
- the gate electrode and the gate insulating layer are surrounded, in a plane parallel to the surface of the substrate, by an insulant known as a spacer.
- the gate insulating layer is disposed between the substrate and the gate electrode.
- the device also comprises a source region and a drain region situated below the surface of the substrate, at a level of two opposite sides of the gate electrode, respectively.
- the source region and the drain region each contain electrical carriers of the same given type, with respect to first concentrations.
- each portion of second semiconductor material also each comprise a portion of a second semiconductor material disposed on the substrate below the level of the gate insulating layer in a direction perpendicular to the surface of the substrate.
- Each portion of second material extends at least partially between the substrate and the spacer, substantially as far as a limit coming into line, in said pe ⁇ endicular direction, with one of the opposite sides of the gate electrode.
- Said portions of second material are doped with doping elements in order to create electrical carriers of said given type, with second concentrations less than said first concentrations.
- the portions of second material have a melting point lower than the melting point of said first material. According to the invention, each portion of second semiconductor material at least partially fulfills a function of extension of the semiconductor device.
- the portions of second material advantageously have an ability to absorb a light radiation greater than the abso ⁇ tion ability of the first material for the same light radiation.
- the second material can be based on germanium or based on an alloy of silicon and germanium (of the SixGel-x type, where x is a number between 0 and 1). This is because the melting points of silicon and germanium are respectively 900°C and 500°C approximately.
- the invention also relates to a method of manufacturing a semiconductor device of the above type.
- Fig. 1 is a view in section of an MOS transistor produced according to a first variant of the invention
- Figs. 2 and 3 illustrate two steps of manufacturing an MOS transistor according to Fig. 1;
- Figs. 4-7 illustrate steps of manufacturing an MOS transistor according to a second variant of the invention.
- An MOS transistor is produced on the surface of a substrate 100 which may, for example, be made from monocrystalline silicon.
- a substrate 100 which may, for example, be made from monocrystalline silicon.
- it comprises a source region 4 and a drain region 5 produced by doping in the substrate 10, on each side of a conduction channel 10.
- the regions 4 and 5 have electrical conduction of the same type, n or p, distinct from that of the channel 10. They contain for this pm ose electrical carriers with a concentration of approximately 2.10 18 carriers per cubic centimeter.
- a gate insulating layer 2 is disposed on the surface S of the substrate 100.
- a gate electrode 1 makes it possible to control the channel 10 through the layer 2.
- the layer 2 is made from silica (SiO 2 ), tantalum oxide (Ta 2 O 5 ) or hafnium oxide (HfO 2 ), for example, and the electrode 1 is made from polysilicon for example.
- the substrate 100 is covered, respectively above the regions 4 and 5, with two portions of a layer of germanium 6 and 7, themselves covered respectively with two portions of a layer of silicon 8 and 9.
- the portions 6 and 7 are situated below the level of the surface S present above the channel 10.
- the material of the layers 8 and 9 is, for example, conductive silicon.
- the portions 8 and 9 protect the portions 6 and 7 against any oxidation liable to impair the electrical properties of the latter.
- the portions 6-8 are extended to a limit in line with the opposite sides Cl and C2 of the electrode 1, between the spacer 3 and the substrate 100.
- Two supplementary portions 6bis and 8bis, respectively in the same materials as the portions 6 and 7 on the one hand and 8 and 9 on the other hand, can also be present above the electrode 1.
- the portions 8, 8bis and 9 can help to form metallic silicide parts for producing electrical contacts on respectively the region 4, the electrode 1 and the region 5.
- the portions 6 and 7 are doped so as to create, within these portions, n or p electrical carriers, of the same type as those in the regions 4 and 5.
- the concentration of these electrical carriers in the portions 6 and 7 is for example around 5.10 17 carriers per cubic centimeter.
- the portions 6 and 7 then constitute tip regions of the MOS transistor.
- the silicon substrate 100 initially comprises a doping well, of the n or p type, depending on the type of transistor envisaged.
- the layer 2 is formed on a part PI of the surface S of the substrate 100.
- the electrode 1 is next formed above the layer 2, and the spacer 3 is disposed around the layer 2 and electrode 1, parallel to the surface S, according to one of the methods normally used for manufacturing MOS transistors.
- Two surface films of the material of the substrate 100 are then removed (figure 3) respectively in two lateral parts P2 and P3 of the surface of the substrate, situated on two opposite sides of the part PI .
- Each part P2 or P3 extends between the substrate 100 and the spacer 3, substantially as far as a limit coming in line, with the direction D, with one of the sides Cl or C2 of the electrode 2.
- the two films are removed, for example, by selective dissolving of the material of the substrate 100 in a solution containing chemical reagents selected so as to form soluble compounds with the atoms of the substrate.
- an upper part P4 of the electrode 1 can be removed simultaneously.
- the source 4 and drain 5 regions situated below the surface S of the substrate 100, at a level of two lateral parts P2 and P3, respectively, are formed.
- the regions 4 and 5 are formed by ion implantation, in a way which is referred to as "autoaligned" with respect to the sides Cl and C2 of the spacer 3. Molecules of diborane B 2 H 4 or phosphine PH 3 can be used for the implantation of the regions 4 and 5, in order to form a p or n type MOS transistor, respectively.
- the regions 4 and 5 then each contain electrical carriers of the same given type, for example with the concentration cited above in relation to figure 1.
- the regions 4 and 5 may be implanted before the removal of the surface films in the lateral parts P2 and P3.
- each lateral part P2 and P3 a portion 6 or respectively 7 of a semiconductor extension material distinct from the material of the substrate 100 is formed.
- This extension material possesses a melting point lower than the melting point of the material of the substrate 100.
- the extension material is for example germanium.
- Each portion 6 or 7 is extended substantially as far as a location coming in line, in the direction Dl, with the side Cl or C2 of the electrode 1 corresponding to said lateral part.
- the portions 6 and 7 contain doping elements, such as atoms of boron or phosphorus, so as to create electrical carriers of the same given type as the regions 4 and 5.
- the doping elements of the portions 6 and 7 can be present initially in the extension material when it is formed, or be added subsequently during a step of implantation of the extension material.
- the portions 6 and 7 are formed, for example, using a chemical vapor deposition (CVD) process, using organometallic precursors containing atoms of the extension material.
- a continuous layer of the extension material is then obtained, which covers the whole of the substrate 100, the spacer 3 and the electrode 1. By combining masking and etching, parts of this layer are removed so as to leave only the portions 6, 6bis and 7.
- the portions 6 and 7 are next heated to a temperature intermediate between the respective melting points of the material of the substrate 100 and the extension material.
- a laser beam can be used for this heating, which makes it possible to heat regions of the transistor comprising the portions 6 and 7 respectively.
- the extension material is advantageously chosen so that it has an ability to absorb the laser beam greater than the ability of the material of the substrate 100 to absorb the laser beam.
- the portions 6 and 7 are thus melted. Once cooled, they contain electrical carriers at a substantially uniform concentration, and less than the concentration of electrical carriers in the regions 4 and 5. This heating of the portions 6 and 7 may possibly serve simultaneously as a heating activation for the electrical carriers in the regions 4 and 5.
- the encapsulation portions 8 and 9 are deposited respectively on top of the portions 6 and 7.
- the material of the portions 8 and 9 is for example silicon.
- a process similar to that of the formation of the portions 6 and 7 can be used, adapted to the encapsulation material used.
- An encapsulation portion 8bis can possibly be formed simultaneously above the portion 6bis.
- the portions 6 and 7 are formed so that a free interstice remains between the upper surface of each portion 6, 7 and the lower surface of the spacer 3 on the same side of the electrode 1.
- the encapsulation portions 8, 9 are then deposited so that each encapsulation portion 8, 9 extends in the interstice between the spacer 3 and the portion 6 or 7 above which it is deposited. It extends substantially as far as a limit situated in line, in the direction D, with the side Cl or C2 of the electrode 1 corresponding to the encapsulation portion in question.
- Figures 4-6 correspond to a second variant of the invention.
- the spacer 3 is removed selectively, for example by dissolving of the material of the spacer 3 in a solution comprising specially selected chemical reagents.
- the configuration of the transistor depicted in figure 4 is then obtained.
- the function of the spacer 3 is to limit the implantation of the regions 4 and 5 at a distance from each side of the layer 2.
- a fine layer 30 of a protective material is then deposited isotropically, for example silicon nitride (Si 3 N 4 ), on the substrate 100, on the ends of the layer 2 and on the uncovered sides Cl and C2 and the top face of the electrode 1.
- the layer 30 has a thickness of 10 nanometers for example.
- the layer 30 can effect a separation between electrical contacts taken on the region 4 and on the electrode 1 and, in the same way, between electrical contacts taken on the region 3 and on the electrode 1. For this reason, and because it is situated in place of the spacer 3, the layer 30 is also called a spacer.
- the layer 30 is next exposed, through its upper surface, to a directional etching plasma whose direction of bombardment is parallel to the direction D.
- the layer 9 is thus eliminated in its parts oriented pe ⁇ endicular to the direction D.
- the configuration of the transistor according to figure 5 is thus obtained.
- Surface films of the material of the substrate 10 are then removed in the parts
- the thickness of the films removed, in the direction D is greater than the thickness of the layer 30, measured parallel to the surface S.
- the method of manufacturing the MOS transistor is then continued as described above.
- a doping implantation of the portions 6 and 7 is carried out if these do not intrinsically comprise sufficient quantities of electrical carriers.
- the portions 6 and 7 are heated to a temperature greater than the melting point of the extension material.
- Encapsulation portions 8 and 9 can then be disposed on the portions 6 and 7.
- portions of a fine layer of a silicon and germanium alloy is deposited in the lateral parts P2 and P3. This deposition is made between the removal of the surface films of material of the substrate 100 and the formation of the portions 6 and 7.
- Such portions of an alloy having a chemical composition intermediate between the respective compositions of the materials of the substrate 100 and the portions 6 and 7 reduces the interface stresses between these materials. They in particular facilitate the growth of the extension material under conditions of heteroepitaxy.
- the invention has been described in the context of the production of an MOS transistor. It can be applied likewise to any semiconductor device comprising a surface junction, referred to as USJ (standing for "Ultra Shallow Junction" in English), which requires the use of an extension.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006506522A JP2006524428A (en) | 2003-04-24 | 2004-04-16 | Semiconductor device having an extension formed of a low melting point material |
US10/554,067 US7521740B2 (en) | 2003-04-24 | 2004-04-16 | Semiconductor device comprising extensions produced from material with a low melting point |
EP04727959A EP1620887A1 (en) | 2003-04-24 | 2004-04-16 | Semiconductor device comprising extensions produced from material with a low melting point |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0350127 | 2003-04-24 | ||
FR0350127A FR2854276A1 (en) | 2003-04-24 | 2003-04-24 | Semiconductor device useful as a transistor comprises source and drain tip regions with a lower melting point than the semiconductor substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004095565A1 true WO2004095565A1 (en) | 2004-11-04 |
Family
ID=33104522
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2004/001254 WO2004095565A1 (en) | 2003-04-24 | 2004-04-16 | Semiconductor device comprising extensions produced from material with a low melting point |
Country Status (7)
Country | Link |
---|---|
US (1) | US7521740B2 (en) |
EP (1) | EP1620887A1 (en) |
JP (1) | JP2006524428A (en) |
CN (1) | CN100431117C (en) |
FR (1) | FR2854276A1 (en) |
TW (1) | TW200507263A (en) |
WO (1) | WO2004095565A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006074438A1 (en) * | 2005-01-06 | 2006-07-13 | Intel Corporation | Device with stepped source/drain region profile |
US7541239B2 (en) | 2006-06-30 | 2009-06-02 | Intel Corporation | Selective spacer formation on transistors of different classes on the same device |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105470134B (en) * | 2014-09-09 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method, electronic device |
US9911849B2 (en) * | 2015-12-03 | 2018-03-06 | International Business Machines Corporation | Transistor and method of forming same |
Citations (9)
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US4838993A (en) * | 1986-12-04 | 1989-06-13 | Seiko Instruments Inc. | Method of fabricating MOS field effect transistor |
US5710450A (en) * | 1994-12-23 | 1998-01-20 | Intel Corporation | Transistor with ultra shallow tip and method of fabrication |
WO2000030169A1 (en) * | 1998-11-12 | 2000-05-25 | Intel Corporation | Field effect transistor structure with abrupt source/drain junctions |
US6187641B1 (en) * | 1997-12-05 | 2001-02-13 | Texas Instruments Incorporated | Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region |
US6214679B1 (en) * | 1999-12-30 | 2001-04-10 | Intel Corporation | Cobalt salicidation method on a silicon germanium film |
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US6358806B1 (en) * | 2001-06-29 | 2002-03-19 | Lsi Logic Corporation | Silicon carbide CMOS channel |
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2003
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- 2004-04-16 CN CNB2004800109422A patent/CN100431117C/en not_active Expired - Fee Related
- 2004-04-16 JP JP2006506522A patent/JP2006524428A/en not_active Withdrawn
- 2004-04-16 EP EP04727959A patent/EP1620887A1/en not_active Withdrawn
- 2004-04-16 US US10/554,067 patent/US7521740B2/en active Active
- 2004-04-16 WO PCT/IB2004/001254 patent/WO2004095565A1/en active Application Filing
- 2004-04-21 TW TW093111141A patent/TW200507263A/en unknown
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006074438A1 (en) * | 2005-01-06 | 2006-07-13 | Intel Corporation | Device with stepped source/drain region profile |
US7335959B2 (en) | 2005-01-06 | 2008-02-26 | Intel Corporation | Device with stepped source/drain region profile |
US7541239B2 (en) | 2006-06-30 | 2009-06-02 | Intel Corporation | Selective spacer formation on transistors of different classes on the same device |
US8154067B2 (en) | 2006-06-30 | 2012-04-10 | Intel Corporation | Selective spacer formation on transistors of different classes on the same device |
US8174060B2 (en) | 2006-06-30 | 2012-05-08 | Intel Corporation | Selective spacer formation on transistors of different classes on the same device |
Also Published As
Publication number | Publication date |
---|---|
TW200507263A (en) | 2005-02-16 |
CN1777981A (en) | 2006-05-24 |
CN100431117C (en) | 2008-11-05 |
US20060246673A1 (en) | 2006-11-02 |
JP2006524428A (en) | 2006-10-26 |
EP1620887A1 (en) | 2006-02-01 |
US7521740B2 (en) | 2009-04-21 |
FR2854276A1 (en) | 2004-10-29 |
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