WO2004090980A3 - Overlay metrology mark - Google Patents

Overlay metrology mark Download PDF

Info

Publication number
WO2004090980A3
WO2004090980A3 PCT/GB2004/001577 GB2004001577W WO2004090980A3 WO 2004090980 A3 WO2004090980 A3 WO 2004090980A3 GB 2004001577 W GB2004001577 W GB 2004001577W WO 2004090980 A3 WO2004090980 A3 WO 2004090980A3
Authority
WO
WIPO (PCT)
Prior art keywords
mark
mark portion
layer
overlap region
overlay metrology
Prior art date
Application number
PCT/GB2004/001577
Other languages
French (fr)
Other versions
WO2004090980A2 (en
Inventor
Michael John Hammond
Gregory Allyn Kaiser
Nigel Peter Smith
Original Assignee
Aoti Operating Co Inc
Michael John Hammond
Gregory Allyn Kaiser
Nigel Peter Smith
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB0308085A external-priority patent/GB0308085D0/en
Priority claimed from GB0308086A external-priority patent/GB0308086D0/en
Application filed by Aoti Operating Co Inc, Michael John Hammond, Gregory Allyn Kaiser, Nigel Peter Smith filed Critical Aoti Operating Co Inc
Publication of WO2004090980A2 publication Critical patent/WO2004090980A2/en
Publication of WO2004090980A3 publication Critical patent/WO2004090980A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An overlay metrology mark for determining the relative position between two or more layers of an integrated circuit structure comprising a first mark portion associated with a first layer and a second mark portion associated with a second layer, wherein the first and second mark portions comprise geometrically similar periodic arrays of mark structures laid down such that the mark portions have patterns exhibiting rotational symmetry with the axes coincident when the mark is in correct alignment whereby the first mark portion overlays the second mark portion when in correct alignment to create an overlap region, but wherein the periodic array of the first mark portion is systematically shifted relative to the periodic array of the second mark portion to generate a Moiré fringe effect in at least a part of the overlap region. A method of marking and a method of determining overlay error are also described.
PCT/GB2004/001577 2003-04-08 2004-04-08 Overlay metrology mark WO2004090980A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB0308085.0 2003-04-08
GB0308085A GB0308085D0 (en) 2003-04-08 2003-04-08 Overlay alignment mark
GB0308086A GB0308086D0 (en) 2003-04-08 2003-04-08 Overlay alignment mark
GB0308086.8 2003-04-08

Publications (2)

Publication Number Publication Date
WO2004090980A2 WO2004090980A2 (en) 2004-10-21
WO2004090980A3 true WO2004090980A3 (en) 2005-01-20

Family

ID=33161217

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2004/001577 WO2004090980A2 (en) 2003-04-08 2004-04-08 Overlay metrology mark

Country Status (2)

Country Link
TW (1) TW200509355A (en)
WO (1) WO2004090980A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9754895B1 (en) 2016-03-07 2017-09-05 Micron Technology, Inc. Methods of forming semiconductor devices including determining misregistration between semiconductor levels and related apparatuses
US10474040B2 (en) * 2017-12-07 2019-11-12 Kla-Tencor Corporation Systems and methods for device-correlated overlay metrology
EP3931865A4 (en) * 2019-02-14 2023-02-15 KLA Corporation System and method for measuring misregistration of semiconductor device wafers utilizing induced topography
CN112201645B (en) * 2020-09-18 2024-04-12 武汉新芯集成电路制造有限公司 Overlay mark, overlay error measurement method of wafers and stacking method of wafers

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3690881A (en) * 1970-09-28 1972-09-12 Bell Telephone Labor Inc Moire pattern aligning of photolithographic mask
US4343878A (en) * 1981-01-02 1982-08-10 Amdahl Corporation System for providing photomask alignment keys in semiconductor integrated circuit processing
US4664524A (en) * 1983-09-24 1987-05-12 The President Of Nagoya University Optical self-alignment system
US5216257A (en) * 1990-07-09 1993-06-01 Brueck Steven R J Method and apparatus for alignment and overlay of submicron lithographic features
EP0965889A2 (en) * 1998-06-15 1999-12-22 Siemens Aktiengesellschaft Overlay measurement technique using moire patterns
US20010019401A1 (en) * 2000-02-29 2001-09-06 Nobuyuki Irie Exposure apparatus, microdevice, photomask, and exposure method
US20020080364A1 (en) * 2000-12-27 2002-06-27 Koninklijke Philips Electronics N.V. Method of measuring overlay
US20020158193A1 (en) * 2001-02-12 2002-10-31 Abdurrahman Sezginer Overlay alignment metrology using diffraction gratings

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3690881A (en) * 1970-09-28 1972-09-12 Bell Telephone Labor Inc Moire pattern aligning of photolithographic mask
US4343878A (en) * 1981-01-02 1982-08-10 Amdahl Corporation System for providing photomask alignment keys in semiconductor integrated circuit processing
US4664524A (en) * 1983-09-24 1987-05-12 The President Of Nagoya University Optical self-alignment system
US5216257A (en) * 1990-07-09 1993-06-01 Brueck Steven R J Method and apparatus for alignment and overlay of submicron lithographic features
EP0965889A2 (en) * 1998-06-15 1999-12-22 Siemens Aktiengesellschaft Overlay measurement technique using moire patterns
US20010019401A1 (en) * 2000-02-29 2001-09-06 Nobuyuki Irie Exposure apparatus, microdevice, photomask, and exposure method
US20020080364A1 (en) * 2000-12-27 2002-06-27 Koninklijke Philips Electronics N.V. Method of measuring overlay
US20020158193A1 (en) * 2001-02-12 2002-10-31 Abdurrahman Sezginer Overlay alignment metrology using diffraction gratings

Also Published As

Publication number Publication date
WO2004090980A2 (en) 2004-10-21
TW200509355A (en) 2005-03-01

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