WO2004090949A1 - Suppression of electrode re-crystallisation in a ferrocapacitor - Google Patents

Suppression of electrode re-crystallisation in a ferrocapacitor Download PDF

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Publication number
WO2004090949A1
WO2004090949A1 PCT/SG2004/000086 SG2004000086W WO2004090949A1 WO 2004090949 A1 WO2004090949 A1 WO 2004090949A1 SG 2004000086 W SG2004000086 W SG 2004000086W WO 2004090949 A1 WO2004090949 A1 WO 2004090949A1
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Prior art keywords
electrode
ferrocapacitor
size
crystal domains
layer
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Application number
PCT/SG2004/000086
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French (fr)
Inventor
Stefan Gernhardt
Jingyu Lian
Rainer Bruchhaus
Andreas Hilliger
Nicolas Nagel
Uwe Wellhausen
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Infineon Technologies AG
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Infineon Technologies AG
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Publication of WO2004090949A1 publication Critical patent/WO2004090949A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes

Definitions

  • the present invention relates to fabrication processes for ferroelectric devices which include one or more ferrocapacitors, and to ferroelectric devices produced by the fabrication processes.
  • ferroelectric devices such as FeRAM devices and high k DRAM devices including ferroelectric capacitors produced by depositing the following layers onto a substructure: a bottom electrode layer, a ferroelectric layer, and a top electrode layer.
  • Hardmask elements typically formed Tetraethyl Orthosilicate (TEOS)
  • TEOS Tetraethyl Orthosilicate
  • the etching separates the top electrode layer into top electrodes, the bottom electrode layer into bottom electrodes, and the ferroelectric layer into ferroelectric elements sandwiched by respective pairs of top electrodes and bottom electrodes.
  • an insulating material such as TEOS is deposited over the completed ferrocapacitors.
  • the ferroelectric material is generally subject to a crystallization step which is typically performed at temperatures of about 600°C in an oxygen ambient atmosphere.
  • the ferrocapacitor is encapsulated under a cover layer, which is typically alumina, but may be other materials which block hydrogen diffusion.
  • Fig. 1 (a) The structure of part of the ferrocapacitor is shown schematically in Fig. 1 (a) in cross-section.
  • a side portion of a layer 1 of a conductive layer material is shown.
  • This layer 1 is either the top electrode or the bottom electrode of the ferrocapacitor. It carries on its side walls a cover layer 3.
  • the layer 1 as indicated includes multiple crystal domains 5, separated by domain boundaries 6, 7, 8.
  • a subsequent heat treatment step (which may be the crystallisation of the ferroelectric layer of the ferrocapacitor of which the electrode 1 is a part, or may be any thermal post-treatment after the capacitor has been finished), the crystal domains 5 tend to grow ("recrystallisation").
  • Fig. 1 (b) in which the former position of a domain boundary is shown dashed and again marked as 7.
  • the former position of the cover layer is shown dashed and marked as 3, and the new position of the cover marked as 13.
  • the crystals 5 have grown in a manner dependent on the starting conditions, such as the initial size of the crystals 5 and their locations (called the "texture" of the region 11 ), stress, temperature and time, in Fig.
  • the cover layer 13 is stretched by the recrystallisation. If this stretching becomes too great (due to the unfortunate characteristics of the initial texture of the electrode 1 of a certain ferrocapacitor), the cover layer 13 will suffer damage, reducing its capacity to protect the layer 1 in subsequent processing steps. For example, the cover layer 13 may tear, allowing hydrogen to diffuse into the layer 1. In the worst case this can lead to failure of the ferrocapacitor, a problem known as "single cell fail".
  • the present invention aims to address the above problem, and to provide a new and useful technique for ferrocapacitor fabrication.
  • the invention proposes that in the fabrication process of a ferrocapacitor, prior to the deposit of a cover layer over a side wall of an electrode layer of the ferrocapacitor, a step should be performed of reducing the size of crystal domains in a side portion of the electrode layer.
  • the method has the advantage that, due to the reduced size of the crystal domains, the growth of the side regions of the electrode is more homogenous, and causes reduced stresses in the cover layer, leading to a reduced risk of the cover layer failing to protect the ferrocapacitor. In particular, there is a reduced chance that the cover layer will be damaged due to an unfortunate initial texture of the electrode, leading to a reduced risk of the ferrocapacitor failing.
  • the step of reducing the crystal domains may for example be performed by oxygen implantation on the sidewalls of the electrode.
  • the oxygen atoms have no harmful effect on the electrode layer (although if desired it would be possible to remove the oxygen atoms by an annealing step).
  • nitrogen or Argon molecules may be used in place of oxygen molecules.
  • the "size" of the crystal domains may be defined as their mean maximum dimension, or by any other appropriate measure.
  • the invention provides a method of fabricating a ferrocapacitor device, the method including forming a ferrocapacitor structure comprising an upper electrode and a lower electrode sandwiching a ferroelectric element; reducing the size of crystal domains in a side portion of at least one of the upper electrode and lower electrode; and depositing a cover layer over the side wall of the electrode.
  • the method includes reducing the size of crystal domains to less than 5nm.
  • the invention also includes a ferrocapacitor device formed by such a fabrication process.
  • Fig. 1 which is composed of Fig. 1 (a) and 1 (b), shows a process observed during a conventional ferrocapacitor fabrication process
  • Fig. 2 which is composed of Figs. 2(a) to 2(d), shows process steps of an embodiment of the present invention.
  • an electrode 1 (which may be either of the top electrode element or bottom electrode of a ferrocapacitor) is shown following the conventional etching step in which the electrode is formed, and prior to the deposit of a cover layer on the side wall 9 of the electrode.
  • the electrode 1 includes crystal domains 5 having crystal boundaries, such as boundaries 6, 7, 8.
  • ferroelectric elements are sandwiched by respective pairs of top electrodes and bottom electrodes (represented by the electrode 1 ).
  • an oxygen implantation step is performed in which the side wall 9 is bombarded with oxygen molecules.
  • oxygen molecules To accelerate the O 2 molecules they have to be ionized (which is performed in the implanter). After the ions arrive at their target they are mostly neutralised. Note that in some embodiments N 2 or Ar may be used in place of O 2 molecules.
  • the domains 5 in a side region 11 of the electrode 1 are reduced in size in this operation.
  • the initial width of the electrode domains is more than 10nm, and a typical width of 20-50nm
  • the embodiment aims to make the maximum width of the particles. less than 5nm, and the average width about 2nm.
  • the previous positions of the domain boundaries 7, 8 of Fig. 2(a), are shown as dashed lines in Fig. 2(b), again marked as 7, 8.
  • the domain boundaries of the newly created domains 15 are shown as 17.
  • the crystal boundary 6 of Fig. 2(a) still remains in the structure of Fig. 2(b) since it is at the edge of the side region 11 of the electrode 1.
  • the size of the crystal domains is reduced by the oxygen implantation after the step of sandwiching the ferroelectric element between the upper electrode and the lower electrode.
  • a cover layer 3 is deposited over the side wall 9 of the electrode 1 , by the conventional technique.
  • the structure will be subject to heat treatment steps (which may be the crystallisation of the ferroelectric layer of the ferrocapacitor of which the layer 1 is a part, or may be the crystallisation of a ferroelectric layer of a ferrocapacitor higher in the structure), but during these steps the portion of the structure shown in Fig. 2(c) is changed into the structure shown in Fig. 2(d).
  • the problem of uneven domain growth in electrodes which is addressed by the embodiment, does not occur in the ferroelectric layer, and therefore no treatment step is necessary there.
  • the ferroelectric layer will experience the oxygen implantation also, but this does not create a problem. If in other embodiments oxygen implantation into the ferroelectric (or other) layer did have some undesired effect, it would be straightforward to protect the ferroelectric (or other) layers from the oxygen implantation using a masking material, such as TEOS.

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  • Semiconductor Memories (AREA)

Abstract

An electrode (1) of a ferrocapacitor formed by an etching process is treated by oxygen implantation to reduce the size of crystal domains (15) in side regions (11) of the electrode (1). Subsequently a cover layer (3) is deposited over the side wall of the electrode to protect the ferrocapacitor in subsequent process steps. Later in the fabrication process the ferrocapacitor is subject to heat treatments, but due to the reduced size of the crystal domains (15) the growth of the crystal domains in the side regions (11) of the electrode is more homogenous, and causes reduced stresses in the cover layer (3), leading to a reduced risk of the cover layer (3) failing to protect the ferrocapacitor.

Description

Suppression of electrode re-crystallisation in a ferrocapacitor
Field of the invention
The present invention relates to fabrication processes for ferroelectric devices which include one or more ferrocapacitors, and to ferroelectric devices produced by the fabrication processes.
Background of Invention
It is known to produce ferroelectric devices such as FeRAM devices and high k DRAM devices including ferroelectric capacitors produced by depositing the following layers onto a substructure: a bottom electrode layer, a ferroelectric layer, and a top electrode layer. Hardmask elements, typically formed Tetraethyl Orthosilicate (TEOS), are deposited over the top electrode layer, and used to etch the structure so as to remove portions of the bottom electrode layer, ferroelectric layer, and top electrode layer which are not under the hardmask elements. The etching separates the top electrode layer into top electrodes, the bottom electrode layer into bottom electrodes, and the ferroelectric layer into ferroelectric elements sandwiched by respective pairs of top electrodes and bottom electrodes. Subsequently, an insulating material such as TEOS is deposited over the completed ferrocapacitors. By repeating the above steps a multi-layer structure can be formed, comprising ferrocapacitors at each of a number of levels of the structure.
During the fabrication process of each ferrocapacitor, the ferroelectric material is generally subject to a crystallization step which is typically performed at temperatures of about 600°C in an oxygen ambient atmosphere.
To reduce damage to the ferrocapacitor during subsequent process steps (such as the fabrication of higher layers of the device, and/or electrical connections through the device), the ferrocapacitor is encapsulated under a cover layer, which is typically alumina, but may be other materials which block hydrogen diffusion.
The structure of part of the ferrocapacitor is shown schematically in Fig. 1 (a) in cross-section. A side portion of a layer 1 of a conductive layer material is shown. This layer 1 is either the top electrode or the bottom electrode of the ferrocapacitor. It carries on its side walls a cover layer 3. The layer 1 as indicated includes multiple crystal domains 5, separated by domain boundaries 6, 7, 8.
During a subsequent heat treatment step (which may be the crystallisation of the ferroelectric layer of the ferrocapacitor of which the electrode 1 is a part, or may be any thermal post-treatment after the capacitor has been finished), the crystal domains 5 tend to grow ("recrystallisation"). This is shown in Fig. 1 (b), in which the former position of a domain boundary is shown dashed and again marked as 7. The former position of the cover layer is shown dashed and marked as 3, and the new position of the cover marked as 13. The crystals 5 have grown in a manner dependent on the starting conditions, such as the initial size of the crystals 5 and their locations (called the "texture" of the region 11 ), stress, temperature and time, in Fig. 1 (b), it can easily be seen that the cover layer 13 is stretched by the recrystallisation. If this stretching becomes too great (due to the unfortunate characteristics of the initial texture of the electrode 1 of a certain ferrocapacitor), the cover layer 13 will suffer damage, reducing its capacity to protect the layer 1 in subsequent processing steps. For example, the cover layer 13 may tear, allowing hydrogen to diffuse into the layer 1. In the worst case this can lead to failure of the ferrocapacitor, a problem known as "single cell fail".
Summary of the Invention
The present invention aims to address the above problem, and to provide a new and useful technique for ferrocapacitor fabrication. In general terms, the invention proposes that in the fabrication process of a ferrocapacitor, prior to the deposit of a cover layer over a side wall of an electrode layer of the ferrocapacitor, a step should be performed of reducing the size of crystal domains in a side portion of the electrode layer.
The method has the advantage that, due to the reduced size of the crystal domains, the growth of the side regions of the electrode is more homogenous, and causes reduced stresses in the cover layer, leading to a reduced risk of the cover layer failing to protect the ferrocapacitor. In particular, there is a reduced chance that the cover layer will be damaged due to an unfortunate initial texture of the electrode, leading to a reduced risk of the ferrocapacitor failing.
The step of reducing the crystal domains may for example be performed by oxygen implantation on the sidewalls of the electrode. The oxygen atoms have no harmful effect on the electrode layer (although if desired it would be possible to remove the oxygen atoms by an annealing step). Note that in some embodiments nitrogen or Argon molecules may be used in place of oxygen molecules.
The "size" of the crystal domains may be defined as their mean maximum dimension, or by any other appropriate measure.
In general terms, the invention provides a method of fabricating a ferrocapacitor device, the method including forming a ferrocapacitor structure comprising an upper electrode and a lower electrode sandwiching a ferroelectric element; reducing the size of crystal domains in a side portion of at least one of the upper electrode and lower electrode; and depositing a cover layer over the side wall of the electrode. Preferably the method includes reducing the size of crystal domains to less than 5nm. The invention also includes a ferrocapacitor device formed by such a fabrication process. Brief Description of The Figures
Preferred features of the invention will now be described, for the sake of illustration only, with reference to the following figures in which:
Fig. 1 , which is composed of Fig. 1 (a) and 1 (b), shows a process observed during a conventional ferrocapacitor fabrication process; and
Fig. 2, which is composed of Figs. 2(a) to 2(d), shows process steps of an embodiment of the present invention.
Detailed Description of the embodiments
A method which is an embodiment of the invention will now be explained with reference to Figs. 2(a) to 2(d). The reference numerals employed in Figs. 1(a) and 1 (b) are used in Figs. 2(a) to 2(d) to indicate items having equivalent meaning.
Referring firstly to Fig. 2(a), the structure of an electrode 1 (which may be either of the top electrode element or bottom electrode of a ferrocapacitor) is shown following the conventional etching step in which the electrode is formed, and prior to the deposit of a cover layer on the side wall 9 of the electrode. As in Fig. 1 (a), the electrode 1 includes crystal domains 5 having crystal boundaries, such as boundaries 6, 7, 8.
As explained above in the section entitled "Background of Invention", ferroelectric elements are sandwiched by respective pairs of top electrodes and bottom electrodes (represented by the electrode 1 ).
As shown in Fig. 2(b), an oxygen implantation step is performed in which the side wall 9 is bombarded with oxygen molecules. To accelerate the O2 molecules they have to be ionized (which is performed in the implanter). After the ions arrive at their target they are mostly neutralised. Note that in some embodiments N2 or Ar may be used in place of O2 molecules.
As indicated in the figure the domains 5 in a side region 11 of the electrode 1 are reduced in size in this operation. Whereas the initial width of the electrode domains is more than 10nm, and a typical width of 20-50nm, the embodiment aims to make the maximum width of the particles. less than 5nm, and the average width about 2nm. The previous positions of the domain boundaries 7, 8 of Fig. 2(a), are shown as dashed lines in Fig. 2(b), again marked as 7, 8. The domain boundaries of the newly created domains 15 are shown as 17. The crystal boundary 6 of Fig. 2(a) still remains in the structure of Fig. 2(b) since it is at the edge of the side region 11 of the electrode 1.
Preferably, the size of the crystal domains is reduced by the oxygen implantation after the step of sandwiching the ferroelectric element between the upper electrode and the lower electrode.
The further steps of the fabrication method are as in conventional methods. Specifically, in the next process step, as shown in Fig. 2(c), a cover layer 3 is deposited over the side wall 9 of the electrode 1 , by the conventional technique. Later in the fabrication process the structure will be subject to heat treatment steps (which may be the crystallisation of the ferroelectric layer of the ferrocapacitor of which the layer 1 is a part, or may be the crystallisation of a ferroelectric layer of a ferrocapacitor higher in the structure), but during these steps the portion of the structure shown in Fig. 2(c) is changed into the structure shown in Fig. 2(d). Due to the reduced size of the crystals 15, and their homogenous distribution, the effects of the initial texture of the electrode 1 are suppressed, and the process window is widened dramatically. Although the invention has been described above in relation to a single embodiment, many variations are possible within the scope of the invention as will be clear to a skilled reader. For example, instead of oxygen implantation, other chemical treatment processes may be employed to reduce the crystal domain size of the domains in the side region 11 proximate the side wall 9.
Note that the problem of uneven domain growth in electrodes which is addressed by the embodiment, does not occur in the ferroelectric layer, and therefore no treatment step is necessary there. In practice, in the embodiment the ferroelectric layer will experience the oxygen implantation also, but this does not create a problem. If in other embodiments oxygen implantation into the ferroelectric (or other) layer did have some undesired effect, it would be straightforward to protect the ferroelectric (or other) layers from the oxygen implantation using a masking material, such as TEOS.

Claims

Claims
1. A method of fabricating a ferrocapacitor device, the method including:
forming a ferrocapacitor structure comprising an upper electrode and a lower electrode sandwiching a ferroelectric element;
reducing the size of crystal domains to less than 5nm in a side portion of at least one of the upper electrode and lower electrode; and
depositing a cover layer over the side wall of the electrode.
2. A method according to claim 1 in which the size of the crystal domains is reduced by oxygen implantation.
3. A method according to claim 1 in which the size of the crystal domains is reduced by oxygen implantation after sandwiching the ferroelectric element between the upper electrode and the lower electrode.
4. A method according to claim 1 in which the size of the crystal domains is reduced such that their average domains is about 2nm.
5. A method according to claim 1 in which the size of the crystal domains is reduced in both the top and bottom electrode.
6. A ferrocapacitor device formed by a fabrication process according to claim 1.
7. A device according to claim 6 which is an FeRAM memory device.
PCT/SG2004/000086 2003-04-11 2004-04-08 Suppression of electrode re-crystallisation in a ferrocapacitor Ceased WO2004090949A1 (en)

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US10/413,465 2003-04-11
US10/413,465 US20040201049A1 (en) 2003-04-11 2003-04-11 Suppression of electrode re-crystallisation in a ferrocapacitor

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05343616A (en) * 1992-06-09 1993-12-24 Seiko Epson Corp Dielectric element and manufacturing method thereof
GB2330004A (en) * 1995-01-25 1999-04-07 Nec Corp Stacked capacitor electrode fabrication
US6078072A (en) * 1997-10-01 2000-06-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a capacitor
US6110531A (en) * 1991-02-25 2000-08-29 Symetrix Corporation Method and apparatus for preparing integrated circuit thin films by chemical vapor deposition
EP1077478A2 (en) * 1999-08-18 2001-02-21 Matsushita Electronics Corporation Method of making ferroelectric thin film, ferroelectric capacitor, ferroelectric memory and method for fabricating ferroelectric memory
US20010019874A1 (en) * 1994-12-28 2001-09-06 Matsushita Electronics Corporation Capacitor for integrated circuit and its fabrication method
US20030011012A1 (en) * 2001-07-11 2003-01-16 Rhodes Howard E. Capacitor with oxygenated metal electrodes and high dielectric constant materials
US6531726B1 (en) * 1999-10-26 2003-03-11 Fujitsu Limited Ferroelectric capacitor with electrode formed in separate oxidizing conditions

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5358889A (en) * 1993-04-29 1994-10-25 Northern Telecom Limited Formation of ruthenium oxide for integrated circuits
US5696014A (en) * 1994-03-11 1997-12-09 Micron Semiconductor, Inc. Method for increasing capacitance of an HSG rugged capacitor using a phosphine rich oxidation and subsequent wet etch

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6110531A (en) * 1991-02-25 2000-08-29 Symetrix Corporation Method and apparatus for preparing integrated circuit thin films by chemical vapor deposition
JPH05343616A (en) * 1992-06-09 1993-12-24 Seiko Epson Corp Dielectric element and manufacturing method thereof
US20010019874A1 (en) * 1994-12-28 2001-09-06 Matsushita Electronics Corporation Capacitor for integrated circuit and its fabrication method
GB2330004A (en) * 1995-01-25 1999-04-07 Nec Corp Stacked capacitor electrode fabrication
US6078072A (en) * 1997-10-01 2000-06-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a capacitor
EP1077478A2 (en) * 1999-08-18 2001-02-21 Matsushita Electronics Corporation Method of making ferroelectric thin film, ferroelectric capacitor, ferroelectric memory and method for fabricating ferroelectric memory
US6531726B1 (en) * 1999-10-26 2003-03-11 Fujitsu Limited Ferroelectric capacitor with electrode formed in separate oxidizing conditions
US20030011012A1 (en) * 2001-07-11 2003-01-16 Rhodes Howard E. Capacitor with oxygenated metal electrodes and high dielectric constant materials

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 018, no. 171 (E - 1529) 23 March 1994 (1994-03-23) *

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