WO2004086236A3 - Anordnung und verfahren zum austausch von massenspeichern - Google Patents

Anordnung und verfahren zum austausch von massenspeichern Download PDF

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Publication number
WO2004086236A3
WO2004086236A3 PCT/DE2004/000584 DE2004000584W WO2004086236A3 WO 2004086236 A3 WO2004086236 A3 WO 2004086236A3 DE 2004000584 W DE2004000584 W DE 2004000584W WO 2004086236 A3 WO2004086236 A3 WO 2004086236A3
Authority
WO
WIPO (PCT)
Prior art keywords
mass storage
data bus
arrangement
storage device
storage devices
Prior art date
Application number
PCT/DE2004/000584
Other languages
English (en)
French (fr)
Other versions
WO2004086236A2 (de
Inventor
Robert Depta
Original Assignee
Fujitsu Siemens Computers Gmbh
Robert Depta
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Siemens Computers Gmbh, Robert Depta filed Critical Fujitsu Siemens Computers Gmbh
Publication of WO2004086236A2 publication Critical patent/WO2004086236A2/de
Publication of WO2004086236A3 publication Critical patent/WO2004086236A3/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4081—Live connection to bus, e.g. hot-plugging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2053—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant
    • G06F11/2094—Redundant storage or storage space

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Bus Control (AREA)

Abstract

Anordnung und Verfahren zum Austausch von Massenspeichern Anordnung mit einem Datenbusinterface (B), das mit einem Datenbuskontroller (BC) verbunden ist, mit zumindest einem Hauptmassenspeicher (MP1), der über das Datenbusinterface (B) mit dem Datenbuskontroller (BC) physikalisch und logisch verbunden ist und mit zumindest einem Reservemassenspeicher (RP1), der über das Datenbusinterface (B) mit dem Datenbuskontroller (BC) physikalisch verbunden ist. Die Anordnung weist eine Kontrollvorrichtung (EP) auf, durch die nach einem Ausfall eines Hauptmassenspeichers (MP1) dieser logisch vom Datenbuskontroller (BC) trennbar ist und durch die zumindest ein Reservemassenspeicher (RP1) logisch mit dem Buskontroller (BC) verbindbar ist.
PCT/DE2004/000584 2003-03-27 2004-03-22 Anordnung und verfahren zum austausch von massenspeichern WO2004086236A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10313892.7 2003-03-27
DE2003113892 DE10313892B4 (de) 2003-03-27 2003-03-27 Anordnung und Verfahren zum Austausch von Massenspeichern

Publications (2)

Publication Number Publication Date
WO2004086236A2 WO2004086236A2 (de) 2004-10-07
WO2004086236A3 true WO2004086236A3 (de) 2005-03-03

Family

ID=33016029

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2004/000584 WO2004086236A2 (de) 2003-03-27 2004-03-22 Anordnung und verfahren zum austausch von massenspeichern

Country Status (3)

Country Link
DE (1) DE10313892B4 (de)
TW (1) TWI316663B (de)
WO (1) WO2004086236A2 (de)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5687089A (en) * 1992-09-24 1997-11-11 Data General Corporation Drive regulator circuit board for a 3.50 inch disk drive
US5915081A (en) * 1993-05-21 1999-06-22 Mitsubishi Denki Kabushiki Kaisha Arrayed recording apparatus with selectably connectable spare disks
US20020162048A1 (en) * 2001-02-23 2002-10-31 Ackaret Gary R. Storage-device activation control for a high-availability storage system

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4914656A (en) * 1988-06-28 1990-04-03 Storage Technology Corporation Disk drive memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5687089A (en) * 1992-09-24 1997-11-11 Data General Corporation Drive regulator circuit board for a 3.50 inch disk drive
US5915081A (en) * 1993-05-21 1999-06-22 Mitsubishi Denki Kabushiki Kaisha Arrayed recording apparatus with selectably connectable spare disks
US20020162048A1 (en) * 2001-02-23 2002-10-31 Ackaret Gary R. Storage-device activation control for a high-availability storage system

Also Published As

Publication number Publication date
TWI316663B (en) 2009-11-01
TW200424865A (en) 2004-11-16
DE10313892B4 (de) 2007-04-19
DE10313892A1 (de) 2004-10-21
WO2004086236A2 (de) 2004-10-07

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