WO2004081950A1

WO2004081950A1 - Semiconductor integrated circuit and method for testing built-in memory mounted on semiconductor integrated circuit

Info

Publication number: WO2004081950A1
Application number: PCT/JP2003/002843
Authority: WO
Inventors: Yasuhiro Kitagawa
Original assignee: Fujitsu Limited
Priority date: 2003-03-11
Filing date: 2003-03-11
Publication date: 2004-09-23

Abstract

A cycle control section reads first data from a memory cell in an access cycle in which data is reliably read. A holding section temporarily holds the first data as expectation value data. The cycle control section, in a different access cycle from the first data access cycle, secondarily reads second data from the memory cell from which the first data is read. A comparing section compares the first data held in a holding circuit with the second data. When the result of the comparison shows that they are different from each other, a memory array is judged defective. The data read from the memory cell can be used as expectation data, the second data needs not to be compared with an expectation value outside the semiconductor integrated circuit. As a result, an expensive test device such as an LSI tester is not needed, reducing the built-in memory test cost.

Description

TECHNICAL FIELD Test method for semiconductor integrated circuit and built-in memory mounted on semiconductor integrated circuit

The present invention relates to a semiconductor integrated circuit having a built-in memory, and more particularly to a semiconductor integrated circuit having a test circuit for testing the built-in memory. Branch art

In single-chip microcomputers equipped with peripheral functions and built-in memory together with a CPU core, the number of elements mounted on a chip is increasing year by year due to the miniaturization of the device structure. Accompanying this, the storage capacity of the internal memory has also increased.

The built-in memory is tested in a test process after the manufacture of the microcomputer chip. The test time is increasing as the storage capacity of the built-in memory increases. A test method of the built-in memory is disclosed in, for example, Japanese Patent Application Laid-Open No. 11-660000. In this test method, a test circuit is formed in a semiconductor integrated circuit. The test circuit has a circuit for comparing data of a plurality of bits read from the built-in memory with expected value data, and a circuit for wired-ORing all the comparison results. By performing a wired-OR operation on the comparison result, the switching frequency of the transistors and the like in the test circuit is reduced, and the test time is reduced. However, this method requires an external terminal to supply the expected value from outside the chip. In addition, expected value data must be prepared in advance.

Generally, the test of the built-in memory includes a high-speed read test with a short access cycle and a low-speed read test with a long access cycle. In the high-speed read test, for example, a timing failure of the built-in memory is detected. In the low-speed read test, for example, a defect due to an abnormal leak of a signal path or a memory cell in the built-in memory is detected. Normally, the high-speed read test and the low-speed read test are performed using an LSI test. As described above, the test time of the built-in memory tends to increase as the storage capacity increases. In particular, the test time for the low-speed read test is originally long. Therefore, the effect on test cost is large. For this reason, it is desirable to conduct a low-speed read test of the built-in memory without using LSI test equipment.

There is a test method that detects the leak failure of the built-in memory at low speed operation by measuring the power supply current during the standby mode of the microcomputer chip. However, if the leakage current is small, failure cannot be detected.

In order to prevent the failure itself, it is conceivable to raise the minimum operating frequency (product specification) of the internal memory. However, this is not a fundamental measure.

Hereinafter, prior art documents related to the present invention are listed.

(Patent Document)

(1) Japanese Patent Application Laid-Open No. 11-66090 Disclosure of the Invention

An object of the present invention is to reduce the test cost of a built-in memory mounted on a semiconductor integrated circuit. In particular, it is to reduce the cost of low-speed read-out testing of internal memory.

Another object of the present invention is to automatically perform a test inside a semiconductor integrated circuit by internally generating an expected value data for testing a built-in memory.

In one embodiment of the present invention, the cycle control unit reads the first data from the memory cell in an access cycle in which the data can be reliably read. The holding unit temporarily holds the first data read from the memory cell as expected value data. The cycle controller reads the second data again from the memory cell from which the first data was read in an access cycle different from the access cycle of the first data. The comparing section compares the first data stored in the holding circuit with the second data. When the comparison results are different, the memory array is determined to be defective. Since the data read from the memory cell can be set to the expected value, there is no need to compare the second data with the expected value outside the semiconductor integrated circuit. As a result, expensive test equipment such as an LSI tester is not required, and the test cost of the built-in memory can be reduced.

In another embodiment of the present invention, the access cycle for reading the second data is set longer than the access cycle for reading the first data. For example, memory cell reload A network failure can be detected by performing a low-speed read test with a long access cycle. On the other hand, even if there is a leak in the memory cell, no error occurs if the data is read in a short access cycle. That is, the first data can be read correctly even if there is a leak in the memory cell. As a result, the low-speed read test can be easily performed, and the test cost of the low-speed read test can be reduced.

In another embodiment of the present invention, the memory unit, the holding unit, and the comparing unit are formed for each data terminal, so that the test time can be shortened even when the number of bits of the data terminal is large. In another embodiment of the present invention, the outputs of the comparison circuits respectively corresponding to the data terminals are wire-OR connected to each other and connected to the comparison result terminal of the built-in memory. If any of the memory cells are defective, the chip is classified as defective. For this reason, a defective chip can be selected by performing an OR operation on the comparison result. In particular, the wired-OR connection eliminates the need to form a logic circuit after the comparison circuit. In addition, even when there are a plurality of comparison circuits, the presence / absence of a defect can be transmitted to the outside with one comparison result terminal. As a result, the layout size of the internal memory can be reduced. In another embodiment of the present invention, the built-in ROM includes a first program for performing a high-speed access operation for reading the first data from the memory cell, and a low-speed program for reading the second data from the memory cell. It stores a second program for executing an access operation and a third program for determining a comparison result between the first and second data. The controller is a processor that executes the first, second, and third programs sequentially during the test mode. By using the built-in processor and built-in ROM, a read test of the built-in memory can be performed with the minimum hardware.

According to another aspect of the present invention, the pattern generation circuit of the cycle control unit formed in the built-in memory operates in response to a test start signal output from the controller during the test mode, and operates the memory array. Generate a test pattern for testing. Therefore, the controller can execute another functional block test or the like during the memory array test independently of the test. Since a plurality of processes can be performed in parallel, the test time of the semiconductor integrated circuit can be reduced. For example, a read test of a memory array can be performed in a burn-in process of a semiconductor integrated circuit.

In another embodiment of the present invention, the cycle control unit operates in synchronization with a clock. The cycle control unit sets the number of clock cycles for reading the second data to be greater than the number of clock cycles for reading the first data. The cycle control unit generates, for example, a clock cycle for reading the second data by adding a dummy clock cycle to a clock cycle for reading the first data. Therefore, many of the logic circuits for generating a high-speed read cycle can also be used for generating a low-speed read cycle. As a result, the circuit scale of the cycle control unit can be reduced. In another embodiment of the present invention, the number of dummy clock cycles to be added can be externally set in the register of the cycle control unit. Therefore, the optimum number of clock cycles for reading the second data can be set according to the environmental conditions such as temperature and voltage. Also, by gradually changing the number of clock cycles in the trial production of semiconductor integrated circuits, etc., the amount of leaks in the memory array can be indirectly evaluated.

In another embodiment of the present invention, the memory array has a plurality of bit lines connected to the memory cells for transmitting the first and second data. The plurality of first selection switches respectively connected to the bit lines connect one of the bit lines to the first node according to the address.

The input of the holding circuit of the holding unit is connected to the first node via a write switch that is turned on during reading of the first data. Therefore, one of the first data read from the simultaneously accessed memory cells to the bit line is held in the holding circuit via the first node.

The comparison circuit of the comparison unit compares the second data transmitted to the first node with the first data output from the holding circuit. Then, a defect of the memory array is determined. Thereafter, the first switch is switched, the new first data is held in the holding circuit, and the new first data is compared with the second data by the comparing circuit. That is, data retention and data comparison are performed alternately.

In this embodiment, the first data held in the holding circuit is output irrespective of the selection operation of the first selection switch for reading out the second data. That is, the ON operation of the first selection switch when transmitting the first data to the holding circuit and the ON operation of the first selection switch when transmitting the second data to the comparison circuit are independent of each other. . For this reason, selection of the first selection switch such as failure due to multiple selection of the first selection switch Defects can be detected. More specifically, the deco control that turns on and off the first selection switch

—Detection of defects in control circuits such as damper.

Further, the sense amplifier of the memory unit is arranged between the first selection switch and the first node. For this reason, the first data amplified by the sense amplifier can be reliably held in the holding unit, and the second data amplified by the sense amplifier can be reliably held in the first data held in the holding unit. Can be compared to

'In another aspect of the present invention, the memory array has a plurality of bit lines respectively connected to the memory cells for transmitting the first and second data. The plurality of first selection switches respectively connected to the bit lines connect one of the bit lines to the first node according to an address. The first node is connected to the second node via the write switch during reading of the first data.

The plurality of holding circuits of the holding unit are formed respectively corresponding to the bit lines. The input of each holding circuit is connected to the second node via a second selection switch that is turned on during the reading of the first data. For example, a pair of first and second selection switches corresponding to each bit line are simultaneously turned on.

Since the holding circuit is formed corresponding to the bit line, the first data read out from the simultaneously accessed memory cells to the bit line, respectively, is held via the first and second nodes. Are sequentially held. That is, the first data can be read continuously by repeating a predetermined access cycle.

The comparing circuit of the comparing section compares the second data sequentially transmitted to the first node with the first data sequentially transmitted from the holding circuit to the second node. That is, the second data can be read continuously by repeating a predetermined access cycle, and can be compared with the first data. Since the frequency of switching access cycles can be reduced, the load on the cycle control unit can be reduced.

The sense amplifier of the memory unit is arranged between the first node and the write switch. Therefore, the first data amplified by the sense amplifier can be reliably held in the holding unit, and the second data amplified by the sense amplifier can be reliably compared with the first data stored in the holding unit. it can.

In another aspect of the invention, the memory array transmits the first and second data. For this purpose, it has a plurality of bit lines connected to the memory cells, respectively. A plurality of first selection switches respectively connected to the bit lines connect any of the bit lines to the first node according to the address.

The plurality of holding circuits of the holding unit are formed corresponding to the bit lines, respectively. The input of each holding circuit is connected to a bit line via a plurality of write switches that are turned on during reading of the first data. Therefore, the plurality of bits of the first data read from the simultaneously accessed memory cells to the bit lines are simultaneously held in the holding circuit.

The plurality of comparison circuits of the comparison unit are formed corresponding to the bit lines, respectively. The comparison circuit compares the second data of the plurality of bits transmitted from the bit line to the first selection switch simultaneously with the first data output from the holding circuit. Therefore, the first data read out to the bit lines can be held at the same time, and the second data read out to the bit lines can be compared at the same time with the first data. As a result, test time can be significantly reduced.

Each write switch and each first selection switch are connected to each bit line via a transmission node. The sense amplifier of the memory unit is arranged between the bit line and the transmission node. Therefore, the first data amplified by the sense amplifier can be securely held in the holding unit, and the second data amplified by the sense amplifier 7 can be reliably compared with the first data held in the holding unit.

[A brief description of the ^ surface

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a memory map of the central processing unit shown in FIG.

FIG. 3 is a flowchart showing an outline of an internal memory read test performed by the central processing unit in the first embodiment.

FIG. 4 is a flowchart showing details of the low-speed read test shown in FIG. FIG. 5 is a flowchart showing a bit line decoder test in the first embodiment.

FIG. 6 is a block diagram showing a second embodiment of the present invention. FIG. 7 is a memory map of the central processing unit shown in FIG.

FIG. 8 is a flowchart illustrating an outline of a read test of a built-in memory performed by the central processing unit in the second embodiment.

FIG. 9 is a flowchart showing details of the low-speed read test shown in FIG. FIG. 10 is a block diagram showing a third embodiment of the present invention.

FIG. 11 is a block diagram showing a fourth embodiment of the present invention.

FIG. 12 is a memory map of the central processing unit shown in FIG.

FIG. 13 is a flowchart showing an outline of a read test of the built-in memory performed by the central processing unit and the test timing generation circuit in the fourth embodiment. C FIG. 14 shows the low-speed read test shown in FIG. 6 is a flowchart showing details of the process.

FIG. 15 is a timing chart showing an operation of the test timing generation circuit shown in FIG.

FIG. 16 is an evening timing diagram illustrating another operation example of the test timing generation circuit illustrated in FIG. 11. Violent form bear to launch and administer

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the figure, the signal lines indicated by bold lines are composed of a plurality of bits.

FIG. 1 shows a first embodiment of the present invention. This semiconductor integrated circuit is formed on a silicon substrate as a single-chip microcontroller using a CMOS process.

The single-chip microcomputer has a central processing unit CPU (controller, processor), built-in memory MEM (SRAM), EPR0M (not shown), peripheral circuits, and the like. In FIG. 1, for simplicity, only signals related to the read operation of the internal memory MEM are shown.

The central processing unit CPU operates by executing the program written in EPH0M and controls peripheral circuits and the like. The central processing unit CPU has a function for performing an operation test (read test) of the built-in memory MEM. The built-in memory MEM has a predecoder PDEC, a line decoder WDEC, and 16 memory units I / 00-I / 015 corresponding to the data terminals D0-D15. The data terminals D0 to D15 may be an internal bus wired in a single-chip microcomputer or an external bus connected to the outside of the single-chip microcomputer.

The predecoder. The PDEC predecodes an address signal AD output when the central processing unit CPU accesses the built-in memory MEM, and outputs a predecode signal corresponding to an upper bit of the address signal AD to a read line decoder WDEC. And outputs a predecode signal corresponding to the lower bit of the address signal AD to the bit line decoder BDEC of each memory unit 1 / 00-1 / 015.

The read line decoder WDEC selects one of the read lines WL according to the predecode signal, and changes the selected read line WL from a low level to a high level. When the word line WL changes to a high level, the memory cell MC connected to the word line WL is connected to the bit line BL.

The memory unit 1/00 includes a memory array ARY, a selector SEL1, a sense amplifier AMP, a write gate WG, a comparison unit having a comparison circuit CMP1, a holding unit having a holding circuit HLD1, a bit line decoder BDEC, and an output buffer 0BF. Have. The configuration of the memory unit 1 / 01-1 / 015 is the same as that of the memory unit 1/00, and is not shown. The memory array ARY includes a plurality of volatile memory cells MC arranged in a matrix, a plurality of word lines WL connected to the memory cells MC arranged in the horizontal direction in the figure, and a plurality of memory cells MC arranged in the vertical direction in the figure. It has a plurality of connected bit lines BL. Although not shown, the memory cell MC has a latch for storing data, a gate connected to a word line, a source-drain latch, and a transfer gate connected to a bit line BL. I have. That is, it is composed of memory cells of the memory array ARY and SRAM.

The selector SEL1 has a plurality of column switches (first selection switches) formed corresponding to the bit lines BL. The column switch is formed of nMOS transistors. One of the column switches SW1 is turned on in response to a switch control signal output from the bit line decoder BDEC. Turn on column switch SW1 Therefore, one of the bit lines BL is selectively connected to the input of the sense amplifier AMP.

The bit line decoder BDEC outputs a switch control signal for selecting one of the column switches SW1 according to the predecode signal. Note that the bit line decoder BDEC may be provided commonly to the data terminals 1 / 00-15, like the gate line decoder WDEC.

The sense amplifier AMP amplifies the read decoder (the voltage value of the bit line BL) supplied via the column switch SW1, and outputs the amplified decoder to the output buffer 0BF.

The write gate WG (write switch) composed of nMOS transistors turns on in response to the store signal ST (high level) output from the central processing unit CPU during the test mode, and turns on the sense amplifier AMP. Connect the output to the input of the holding circuit HLD1. For this reason, the read data (first data) is held in the holding circuit HLD1 by the central processing unit CPU changing the store signal ST to a high level for a predetermined period during the read operation.

The holding circuit HLD1 is configured by a 1-bit latch. The holding circuit HLD1 stores the read data amplified by the sense amplifier AMP and transmitted via the write gate WG, and outputs the stored data to the comparison circuit CMP1. As will be described later, the data read by the high-speed read operation performed before the low-speed read test during the test mode is held in the holding circuit HLD1 as an expected value of the low-speed read test.

The comparison circuit CMP1 is composed of an E0R circuit whose input is connected to the output of the sense amplifier AMP and the output of the holding circuit HLD1, respectively. The comparator CMP1 compares the logical value of the read data (second data) output from the sense amplifier AMP with the logical value of the data (first data) held in the holding circuit HLD1. The comparison circuit CMP1 outputs logic "0" when both logic values are the same, and outputs logic "1" when both logic values are different. The output of the comparison circuit CMP1 of the memory unit 1 / 00-1 / 015 is connected by wire-or, and connected to the comparison result terminal CMP of the central processing unit CPU.

The output buffer 0BF is used by the central processing unit CPU when reading the internal memory MEM. When the read signal RD output from is high, the output of the sense amplifier AMP is output to the central processing unit CPU as the data signal DO (or D1-D15). FIG. 2 shows a memory map of the central processing unit CPU.

The memory map has a normal bank accessed mainly during operation of the user system (normal operation mode) and a back bank accessed during testing of the single-chip microcomputer (test mode). In the normal bank, I / O area, SRAM area and EP-ROM area are allocated from lower address to higher address. Peripheral circuits such as timers and communication circuits built into the single-chip microcomputer are assigned to the I / O area. The internal memory MEM shown in Fig. 1 is allocated to the SRAM area. In the EP-R0M area, the EP-R0M built in the single-chip-open-mouth computer is assigned.

The EP-R0M area switches to the back bank for testing single-chip microcomputers during the test mode. The back bank is composed of a built-in ROM (for example, another EP-ROM), in which a test program for testing the built-in memory MEM is written.

FIG. 3 shows an outline of a read test of the built-in memory MEM (SRAM) performed by the central processing unit CPU.

The read test is performed by transitioning the central processing unit CPU from the normal operation mode to the test mode. For example, the central processing unit CPU performs a read test of the internal memory MEM when a specific bit (a bit indicating a read test of the internal memory MEM) is set at the time of transition to the test mode. Start.

Specifically, the central processing unit CPU executes a test program for a read test written in the back bank. Here, only the low-speed readout test which is a feature of the present invention will be described. The low-speed read test is a test that executes a read operation with a slow operation cycle in order to detect a failure due to abnormal leakage in the internal memory MEM. In the actual read test, a high-speed read test with a faster operation cycle is also performed. The high-speed read test is performed before performing the low-speed read test. Then, only the chips that pass the high-speed read test are subjected to the low-speed read test. First, the central processing unit CPU writes initial data in the built-in memory MEM (step S11).

Next, the central processing unit CPU performs a low-speed read test (step S12). The low-speed read test will be described later with reference to FIG.

Next, the central processing unit CPU writes the data obtained by inverting the initial data into the built-in memory MEM) (step S13).

Next, the central processing unit CPU performs a low-speed read test on the inverted data (step S14).

FIG. 4 shows details of the low-speed readout test shown in FIG. The slow read test is performed by the central processing unit CPU fetching the program. Steps S22 to S25 are a first program for reading data from a memory cell at high speed. Steps S26 to S28 are a second program for reading data from the memory cells at a low speed. Steps S29 to S30 are a third program for comparing data read at low speed with data read at high speed.

First, in step S21, the central processing unit CPU outputs an address signal AD (upper bit) in order to sequentially select the word lines WL connected to the memory cells MC to be tested. The internal memory MEM reads data from the plurality of memory cells MC connected to the selected word line WL onto the bit line BL. That is, the memory cells MC connected to each word line WL are accessed simultaneously. The selection order of the lead lines WL is previously written in a test program (table, etc.) according to the structure of the memory array ARY.

In step S22, the central processing unit CPU sets the access cycle to “high-speed access (first access cycle)”. In step S26 described later, the central processing unit CPU sets the access cycle to “low-speed access”. Thus, the central processing unit CPU also functions as a cycle control unit that changes the access cycle for reading data.

In step S23, the central processing unit CPU outputs an address signal AD (lower bit) to connect the bit line BL connected to the memory cell MC to be tested to the sense amplifier AMP, and Turn on one of the switches SW1. The center The processing unit CPU simultaneously outputs the upper bit and the lower bit of the address signal AD.

In step S24, the data on the selected bit line BL is transmitted to the sense amplifier AMP via the turned-on column switch SW1, and amplified. That is, the data (the i-th data) is read from the memory cell MC to be tested. Data is read in a short access cycle (high-speed reading). The high-speed readout test is performed before the low-speed readout test. For this reason, the data read out is correct data without any errors (expected value data).

In step S25, the central processing unit CPU changes the store signal ST to a high level for a predetermined period during the amplification operation of the sense amplifier AMP, and turns on the write gate .WG. The data amplified by the sense amplifier AMP is written to the holding circuit HLD1 via the write gate. That is, the data (expected value) read from the memory cell MC to be tested is stored.

In step S26, the central processing unit CPU sets the access cycle to “slow access (second access cycle)”. At this time, the word line WL remains selected in step S22 described above. .

In step S27, the central processing unit CPU again selects the bit line BL selected during "high-speed access" ^{5. One of the} column switches SW1 is turned on in response to the address signal AD.

In step S28, the data on the bit line BL connected to the memory cell MC to be tested is transmitted to the sense amplifier AMP via the turned-on column switch SW1, and the data (second data) is read. It is.

In step S29, the comparison circuit CMP1 compares the data read from the memory cell MC at a low speed with the data (expected value) read at a high speed and held in the holding circuit HLD1. That is, according to the present invention, the acceptability of the built-in memory MEM can be determined without receiving an expected value from the outside. In other words, there is no need to prepare the expected value in advance. The central processing unit CPU receives the comparison result signal CMP output from the comparison circuit CMP1.

In step S30, the central processing unit CPU determines based on the comparison result signal CMP. Then, it is determined whether or not the data read at a low speed from the memory cell MC matches the expected value. If the data does not match, the internal memory MEM is determined to be defective and the test ends. Specifically, a flag indicating a failure of the internal memory MEM is set at a predetermined register of the central processing unit CPU. If it is determined that the internal memory MEM is normal, the process proceeds to step S32.

In step S31, the central processing unit CPU changes the lower bit of the address signal AD and switches the selected bit line BL to test the next memory cell MC.

In step S32, the central processing unit CPU determines whether all the memory cells MC (bit line BL) connected to one word line 試験 have been tested. If all the bit lines BL have been selected, the process proceeds to step S33. If there is any unselected bit line BL, the process returns to step S22, and steps S21 to S32 are executed.

In step S33, the central processing unit CPU changes the address signal AD in order to switch the selected lead line WL.

In step S34, the central processing unit CPU determines whether or not all the memory cells MC. (Word lines WL) of the internal memory MEM have been tested. If all the word lines WL are selected, the test ends. If there is an unselected lead line WL, the process proceeds to step S21 again, and the above-described test is repeated.

Thus, the low-speed readout test can be performed automatically (self-check) in a single-chip microcomputer without using expensive equipment such as LSI test equipment. In other words, the low-speed readout test can be performed by mounting many single-chip microcomputer chips that have passed the high-speed readout test on a simple evaluation board. For this reason, the test cost for the low-speed read test is significantly lower than when using LSI test equipment. Also, during the burn-in test performed on the evaluation board, a low-speed read test can be performed. As a result, the test time for the low-speed read test is substantially zero.

Figure 5 shows a bit line decoder test as an application example of the test of the built-in memory MEM. The bit line decoder test is performed by the central processing unit CPU. In this flow, step S41 is inserted between steps S24 and S25 in FIG. 4, steps S42 and S43 are inserted between steps S25 and S27 in FIG. 4, and step S26 in FIG. 4 is deleted. Step S44 is inserted between steps S28 and S29 in FIG. Other than that, it is as shown in Fig. 4 except for the operating frequency and the selection order of the word line WL and bit line BL. The same processes as those in FIG. 4 are assigned the same step numbers, and detailed descriptions are omitted. ■

In the bit line decoder test, the access cycle is set short (high-speed access) and the test is performed. By setting high-speed access, the test time can be shortened.

First, in the first step, the central processing unit CPU holds only the data of the target memory cell MC (bit line BL) while selecting the bit lines BL in a predetermined order (first order). Write to the circuit HLD1 (steps S41, S42).

Next, in the second step, the central processing unit CPU selects the bit line BL in a different order (second order) from the above (step S44). Then, only the data of the target memory cell MC (bit line BL) is compared with the data held in the holding circuit HLD1 (steps S44, S29 to S32). In step S44, if the read data is read from the memory cell MC to be tested, the process proceeds to step S29. If the read data is read from a memory cell other than the memory cell MC to be tested, the process proceeds to step S31. The first order and the second order are, for example, the order of selecting the bit lines BL when changing the address signal AD in ascending order and descending order, respectively. The selection order of the bit lines BL is written in a test program (table or the like) in advance according to the structure of the memory array ARY.

By the above-described processing, it is possible to detect a defect such as the multiple selection of the bit line BL when the change order of the address signal AD is different (a defect of the bit line decoder BDEC).

In the first and second steps, the selection order of the word lines WL, not the selection order of the bit lines BL, is made different from each other, thereby making it possible to detect a defect in the word line decoder WDEC. is there. Also in the second to fourth embodiments to be described later, the selection order of the word lines WL is different from each other, so that the Good can be detected.

As described above, in the present embodiment, the first data read from the memory cell MC in the access cycle in which the data can be reliably read is temporarily held in the holding unit HLD1, and is used as expected value data. Therefore, it is not necessary to supply the expected value from outside the single-chip microcomputer. Therefore, a read test of the internal memory MEM can be performed without using expensive test equipment such as an LSI tester. As a result, the test cost of the built-in memory MEM can be reduced.

By setting the first data read at high speed as the expected value and comparing the second data read at low speed with the expected value, a leak failure of the memory cell can be detected. In other words, by using the high-speed read data as the expected value of the low-speed read test, the low-speed read test can be performed easily, and the test cost can be reduced.

By forming the holding unit HLD1 and the comparison unit CMP1 for each data terminal, the test time can be shortened even when the number of bits at the data terminal is large. The wired-OR connection of the output of the comparator CMP1 corresponding to each data terminal eliminates the need to form a logic circuit after the comparator CMP1. Also, the comparison result can be output to the central processing unit CPU via one comparison result terminal CMP. As a result, the layout size of the internal memory MEM can be reduced.

The central processing unit CPU performs a reading test using a test program stored in the built-in ROM. Therefore, a read test of the internal memory MEM can be performed with the minimum hardware.

The first data held in the holding circuit HLD1 is output to the comparison circuit CMP1 regardless of the operation of selecting the column switch SW1 for reading the second data. That is, the comparison circuit CMP1 compares the ON operation of the column switch SW1 when holding the data on the predetermined bit line BL in the holding circuit HLD1 among the high-speed reading data and the low-speed reading data. The ON operation of the column switch SW1 when transmitting to the switch is independent of each other. For this reason, it is possible to detect a defect of the bit line decoder BDEC such as the multiple selection of the bit line BL.

The first data and the second data are amplified by the sense amplifier AMP arranged at the output of the column switch SW1. For this reason, the first data is securely stored in the holding unit HLD1. The second data can be reliably compared with the first data held in the holding unit HLD1. FIG. 6 shows a second embodiment of the present invention. The same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, a test program executed by a built-in memory MEM and a central processing unit CPU (controller, cycle control unit) formed in a single-chip micro-computer is different from the first embodiment. I have. Other configurations are almost the same as those of the first embodiment.

The internal memory MEM has a holding circuit HLD2 corresponding to each of the bit lines BL. A holding unit is formed by the plurality of holding circuits HLD2. Each holding circuit HLD2 is the same as the holding circuit HLD1 of the first embodiment. The holding circuit HLD2 is connected to a write gate WG (write switch) via a selection switch SW2 (second selection switch) of the selector SEL2. The selection switch SW2 is formed by an nMOS transistor. Each selection switch SW is turned on in response to a switch control signal output from the bit line decoder BDEC. The switch control signal is supplied to a gate of a pair of selection switches SW1 and SW2 corresponding to the bit line BL. Therefore, the selection switch pair SW1 and S2 are simultaneously turned on.

One input of a comparison circuit CMP2 constituting the comparison unit receives an output of the sense amplifier AMP. The other input of the comparison circuit CMP2 is connected to the holding circuit HLD via the selection switch SW2. That is, the comparison circuit CMP2 reads the read data (first data) on the bit line BL selected by the switch control signal and the data (second data) held by the holding circuit HLD2 corresponding to the selected bit line. (Overnight, expected value data) and outputs the comparison result to the central processing unit CPU. The comparison circuit CMP2 is the same as the comparison circuit CMP1 of the first embodiment. The output of the comparison circuit GMP2 of the memory unit 1 / 00-1 / 015 is wired-OR connected and connected to the comparison result terminal CMP of the central processing unit CPU.

The memory array AHY of the internal memory MEM is formed as a mask ROM. The basic configuration of the mask ROM memory array ARY is the same as the SRAM memory array ARY of the first embodiment. That is, the memory arrays ARY are arranged in a matrix. Non-volatile memory cells MC, multiple memory cell lines MC connected horizontally in the figure, multiple word lines WL connected to memory cells MC arranged vertically, and multiple bit lines connected to the memory cells MC arranged vertically in the figure Has BL.

FIG. 7 shows a memory map of the central processing unit CPU.

In this embodiment, an I / O area, an SRAM area, and a mask ROM area are allocated to a normal bank from a lower address to a higher address. The internal memory MEM shown in Fig. 1 is allocated to the mask ROM area. In the RAM area, the SRAM incorporated in the single-chip microcomputer is allocated. The back bank is composed of a built-in ROM (for example, another EP-ROM), and has a test program area and a program loader area for transferring this test program to the RAM area. .

Figure 8 shows the outline of the read test of the built-in memory MEM (mask ROM) performed by the central processing unit CPU.

The read test is performed by transitioning the central processing unit CPU from the normal operation mode to the test mode. For example, the central processing unit CPU performs a read test of the internal memory MEM when a specific bit (a bit indicating a read test of the internal memory MEM) is set at the time of transition to the test mode. Start o

Specifically, the central processing unit CPU executes the program loader (program) written in the back bank to transfer the test program to the RAM area (step S51). Next, the central processing unit CPU executes the test program transferred to the RAM area to perform a read test of the mask ROM area (step S52). Also, the central processing unit CPU switches from the back bank to the normal bank (step S53). Then, similarly to the first embodiment, a low-speed read test is performed (step S54).

FIG. 9 shows the details of the low-speed read test shown in FIG.

In this flow, steps S61 and S62 are inserted between steps S25 and S26 in FIG. The other differences are only those that result from accessing SHAM or mask ROM. The same processes as those in FIG. 4 are denoted by the same step numbers, and detailed description is omitted. In this embodiment, a plurality of holding circuits HLD2 are formed corresponding to the bit lines BL. For this reason, the central processing unit CPU sequentially holds the data held in the plurality of memory cells MC connected to one word line WL in the holding circuit HLD2. This processing is performed in steps S61 and S62. In step S61, the central processing unit CPU changes the lower bits of the address signal AD to switch the selected bit line BL. In step S62, the central processing unit CPU determines whether all the bit lines BL of the internal memory MEM have been selected. If all the bit lines BL have been selected, the process proceeds to step S26. If there is an unselected bit line BL, the process returns to step S23.

In this embodiment, the data (first data) of all the memory cells MC connected to one word line WL is sequentially held in the holding circuit HLD during the period set for “high-speed access”. . Similarly, during the period set for “slow access”, the data (second data) of all the memory cells MC connected to one read line WL is compared with the first data by the comparator CMP2. They are compared sequentially. For this reason, the frequency of switching between “high-speed access” and “low-speed access” is significantly lower than in the first embodiment. As a result, the load on the central processing unit CPU can be reduced.

In this embodiment, the same effects as in the first embodiment can be obtained. Further, in this embodiment, a plurality of holding circuits HLD2 are formed corresponding to the respective bit lines. Therefore, by repeating the "high-speed access cycle", the first data from the memory cell MC can be read continuously, and can be sequentially stored in the holding circuit HLD2. That is, the first data can be read continuously. Similarly, by repeating the “slow access cycle”, the first data held in the holding circuit HLD2 can be sequentially compared with the second data from the memory cell MC. As a result, the frequency of access cycle switching can be reduced, and the load on the central processing unit CPU can be reduced.

FIG. 10 shows a third embodiment of the present invention. The same elements as those described in the first and second embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted.

The single-chip microcomputer of this embodiment is the same as that of the first embodiment. It has a test function and a test function of the second embodiment. That is, in each memory unit 1 / 00-1 / 015, a holding circuit HLD1 common to the bit line BL and a holding circuit HLD2 corresponding to the bit line BL are formed. Further, a comparison circuit CMP1 corresponding to the holding circuit HLD1 and a comparison circuit CMP2 corresponding to the holding circuit HLD2 are not formed. The outputs of the comparison circuits CMP1 and CMP2 are wire-or connected and connected to the comparison result terminal CMP of the central processing unit CPU. The memory array ARY is formed as SRAM.

The central processing unit CPU executes at least one of the test program of the first embodiment and the test program of the second embodiment during the test mode. Which test is performed is determined based on whether or not a specific bit in the register of the central processing unit CPU is set.

In this embodiment, the same effects as those of the first and second embodiments can be obtained.

FIG. 11 shows a fourth embodiment of the present invention. Elements that are the same as the elements described in the first embodiment are given the same reference numerals, and detailed descriptions thereof are omitted.

In this embodiment, a built-in memory MEM and a central processing unit CPU (processor) formed in a single-chip microcomputer are different from those of the first embodiment. Further, the single-chip microcomputer has a test timing generation circuit TGEN instead of the predecoder PDEC of the first embodiment. The test timing generation circuit TGEN operates as a cycle control unit that changes the access cycle during the test mode, and as a pattern generation circuit that generates test patterns. Other configurations are almost the same as those of the first embodiment.

The test timing generation circuit TGEN operates as the pre-decoder PDEC of the first embodiment during the normal operation mode. Further, the test timing generation circuit TGEN has a control function of a test, such as generation of a test pattern, which is performed by the central processing unit CPU in the first and second embodiments. Therefore, the central processing unit CPU only activates the test mode signal TM (test start signal), and the test of the internal memory MEM is started. The test timing generator TGEN responds to the test mode signal TM Performs a low-speed read test of the internal memory MEM and notifies the central processing unit CPU of the test result (pass or file) as a test result signal TR. Therefore, the central processing unit CPU can execute another function block test or the like during the low-speed read test. ·

The built-in memory MEM has a memory array ARY of flash memory. The memory array ARY is composed of a plurality of non-volatile memory cells MC arranged in a matrix; a plurality of word lines WL connected to the memory cells MC arranged in the horizontal direction in the figure, and a plurality of memory cells MC arranged in the vertical direction in the figure. It has a plurality of bit lines BL connected to the end memory cell MC. The memory cells MC connected to each word line are accessed simultaneously. The sense amplifier AMP, write gate WG (write switch), holding circuit HLD3, and comparison circuit CMP3 are formed corresponding to the bit lines BL. Specifically, the sense amplifier AMP is arranged between the bit line BL and the column switch SW1 (first selection switch). The write gate WG is arranged between the output (transmission node) of the sense amplifier AMP and the input of the holding circuit HLD3. One input of the comparison circuit CMP3 receives the output of the sense amplifier AMP. The other input of the comparison circuit CMP3 is connected to the output of the holding circuit HLD3. The holding unit is configured by a plurality of holding circuits HLD3. A comparison unit is constituted by the plurality of comparison circuits CMP3.

In this embodiment, the test timing generating circuit TGEN receives a test mode signal TM from the central processing unit CPU and starts a test operation. The test evening generation circuit TGEN outputs the store signal ST in accordance with the evening when the data read from the memory cell MC is amplified by the sense amplifier AMP, and writes the readout data to the holding circuit HLD3. With this operation, all data on the bit line BL is written to the holding circuit HLD3 at once.

Each comparison circuit CMP3 compares the data read separately from the memory cell MC with the data (expected value) held in the holding circuit HLD3, and outputs a comparison result. The comparison circuit CMP3 outputs logic "0" when both logic values are the same, and outputs logic "1" when both logic values are different. The output of the comparison circuit CMP3 is wire-or-connected, and connected to the comparison result terminal CMP of the test timing generation circuit TGEN via the test result switch SW3. The test timing generation circuit TGEN adjusts the test timing according to the output timing of the comparison result. Change the comparison output signal COUT to high level to turn on the test result switch SW3, and receive the comparison result signal CMP. '

When any of the comparison circuits CMP3 in the memory section 1 / 00-1 / 015 outputs logic "1", the test timing generation circuit TGEN receives a high level at the comparison result terminal CMP and the built-in memory MEM is defective. Recognize that there is. The test timing generation circuit TGEN outputs the test result to the central processing unit CPU as a test result signal TR. FIG. 12 shows the memory map of the central processing unit CPU.

The memory map of this embodiment is the same as that of the second embodiment (FIG. 7) except that the mask ROM area is changed to a flash memory area. Figure 13 shows the outline of the read test of the built-in memory MEM (flash memory) performed by the central processing unit CPU and the test timing generation circuit TGEN. The read test is started when the central processing unit CPU outputs the test mode signal TM to the test timing generation circuit TGEN. For example, when the test timing generation circuit TGEN sets a specific bit (a bit indicating a read test of the built-in memory MEM) of a register that is formed in the test timing generation circuit TGEN at the time of transition to the test mode, Next, a read test of the internal memory MEM is started.

Steps S71 and S7 are the same as steps S51 and S52 of the above-described second embodiment (FIG. 8), and are processed by the central processing unit CPU. Next, the central processing unit CPU switches from the back bank to the normal bank (step S73).

Next, the test timing generation circuit TGEN collectively erases the data programmed in the flash memory (step S74). Next, the test timing generation circuit TGEN writes the initial data to the flash memory (step S75).

Next, the test timing generation circuit TGEN performs a low-speed read test (step S76).

Next, the test timing generation circuit TGEN erases the data programmed in the flash memory all at once (step S77). Next, the test timing generation circuit TGEN writes the inverted data into the flash memory (step S78).

Next, the test timing generation circuit TGEN performs a low-speed read test on the inverted data (step S79). Finally, the test timing generation circuit TGEN All data programmed in the flash memory is erased (step S80). FIG. 14 shows details of the low-speed read test shown in FIG.

This flow is configured such that steps S23, S27, S31, and S32 in FIG. 4 are deleted. The other differences are only those that result from accessing SRAM or flash memory. The same processes as those in FIG. 4 are denoted by the same step numbers, and the detailed description is omitted.

In this embodiment, a plurality of sense amplifiers AMP, a holding circuit HLD3, and a comparing circuit CMP3 are respectively formed corresponding to the bit lines BL. Therefore, the data of the memory cell MC connected to the selected mode line WL can be held in the holding circuit HLD3 at a time, and the data read from the memory cell MC newly (second data ) Can be compared once with the data stored in the holding circuit HLD3. Therefore, the operation of selecting the bit line BL becomes unnecessary. In other words, all the memory cells MC connected to the word line can be tested at the same time while one word line WL is selected (while steps S21 to S35 are processed once). As a result, when the number of bit lines BL of each memory unit 1 / 00-1 / 015 is set to ' ⁵ m', the test time of the low-speed read test is reduced to about 1 / m of that of the first embodiment. Become.

FIG. 15 shows the operation (low-speed read test) of the test timing generation circuit TGEN shown in FIG.

The test mode signal TM is held at high level during the low-speed read test (Fig. 15 (a)). The test timing generator TGEN operates in synchronization with the clock signal CLK (Fig. 15 (b)). Here, the clock signal CLK is a clock supplied to the central processing unit CPU or a clock output from the central processing unit CPU.

The test timing generation circuit TGEN keeps selecting the word line WL (WL0, WLls...) During one read test (FIG. 15 (c)). The bit line BL enters a floating state while the precharge signal PRE is at a low level. The data written in the memory cell MC is read out during the floating period of the bit line BL (FIG. 15 (d)). In the next clock cycle, the sense amplifier AMP operates to amplify the read data RD0 on the bit line BL (Fig. 15 (e)). "High-speed access (first access cycle) Is executed in two clock cycles. In the next clock cycle, the store signal ST is output, and the data RD0 amplified by each sense amplifier AMP is written to the holding circuit HLD3 (see FIG. 1). 5 (f)).

"Low-speed access (second access cycle)" is realized by inserting a predetermined number of dummy clock cycles after the second clock cycle in "high-speed access" (Fig. 15 (g)). The number of clock cycles to be inserted can be set to any value from outside the built-in memory MEM by using the mode register MR formed in the test timing generation circuit TGEN. For example, by using the 10: bit of the mode register, 0 to 123 clock cycles can be arbitrarily inserted.

The test timing generation circuit TGEN changes the comparison output signal. C0UT to high level and receives the comparison result signal CMP in the clock cycle after "low-speed access" (Fig. 15 (h)). O The comparison result signal CMP If indicates an error, the test generation timing generation circuit TGEN outputs a high-level test result signal TR to the central processing unit CPU and interrupts the test. If no error occurs, the test timing generation circuit TGEN performs "high-speed access" on the next lead line WL1 to perform a low-speed read test (FIG. 15 (i)).

In this embodiment, the same effects as in the first embodiment can be obtained. Further, in this embodiment, the plurality of holding circuits HLD3 and the plurality of comparison circuits CMP3 are formed corresponding to the bit lines BL, respectively. Therefore, the read data (first data) read to the bit line can be held at the same time, and the read data (second data) read to the bit line can be compared with the first data at a time. As a result, the test time can be significantly reduced.

The test timing generation circuit TGEN operates in response to the test mode signal MD output from the central processing unit CPU during the test mode, and generates a test pattern for testing the memory array ARY. Therefore, the load on the central processing unit CPU for the test of the memory array ARY can be reduced. The central processing unit CPU can perform another function block test or the like during the test of the memory array ARY. Since multiple processes can be performed in parallel, the test time for a single-chip microcomputer can be reduced.

The test evening generation circuit TGEN switches the clock cycle to read the first data. By adding a new clock cycle, a clock cycle to read out the second data is generated. Therefore, many of the logic circuits for generating the high-speed read cycle can be used for generating the low-speed read cycle, and the circuit size of the test timing generation circuit TGEN can be reduced.

Since a test register and a mode register MR are formed in the test generation and mining generation circuit TGEN, the number of dummy clock cycles to be added can be set from outside the internal memory MEM. Therefore, the optimum number of clock cycles for reading the second data can be set according to the environmental conditions such as temperature and voltage. Also, by gradually changing the number of clock cycles, the leak amount of the memory array can be indirectly evaluated.

In the above-described fourth embodiment, an example has been described in which the “low-speed access” cycle is generated by extending the clock cycle according to the setting value of the mode register. The present invention is not limited to such an embodiment. For example, when the built-in memory MEM is a mask ROM or SRAM, as shown in Fig. 16, an internal wait signal WAIT is generated inside the test timing generation circuit TGEN according to the set value of the mode register. The access cycle may be extended while the internal wait signal WAIT is high. During the wait insertion period, read data continues to be output from the memory cell MC to the bit line BL. Therefore, it is easy to detect a leak failure of the memory cell MC.

In the fourth embodiment described above, an example has been described in which the test timing generation circuit TGEN is formed in the built-in memory MEM, and the built-in memory MEM itself performs a low-speed read test. The present invention is not limited to such an embodiment. For example, in the first and second embodiments, a test timing generation circuit TGEN is formed instead of the predecoder PDEC, and the internal memory MEM itself responds to the test mode signal TM from the central processing unit CPU. Then, a low-speed reading test may be performed.

As described above, the present invention has been described in detail. However, the above-described embodiment and its modifications are merely examples of the present invention, and the present invention is not limited thereto. Obviously, modifications can be made without departing from the present invention.禾 Ι'Φ

Test of semiconductor integrated circuit of the present invention and built-in memory mounted on semiconductor integrated circuit In the method, since the data read from the memory cell can be set to the expected value, it is not necessary to compare the second data with the expected value outside the semiconductor integrated circuit. As a result, expensive test equipment such as LSI test equipment is not required, and the test cost of the built-in memory can be reduced. According to the semiconductor integrated circuit of the present invention and the test method of the built-in memory mounted on the semiconductor integrated circuit, the low-speed read test can be easily performed, and the test cost of the low-speed read test can be reduced.

In the semiconductor integrated circuit of the present invention, the test time can be shortened even when the number of bits of the data terminal is large.

In the semiconductor integrated circuit of the present invention, the wired-OR connection eliminates the need to form a logic circuit after the comparison circuit. Even if there are multiple comparison circuits, the presence or absence of a defect can be transmitted to the outside using one comparison result terminal. As a result, the layout size of the internal memory can be reduced.

In the semiconductor integrated circuit of the present invention, by using the built-in processor and the built-in ROM, a read test of the built-in memory can be performed with minimum hardware.

In the semiconductor integrated circuit of the present invention, the controller can execute another function block test or the like during the test of the memory array irrespective of the test. Since a plurality of processes can be performed in parallel, the test time of the semiconductor integrated circuit can be reduced.

In the semiconductor integrated circuit of the present invention, many of the logic circuits for generating the high-speed read cycle can be used for generating the low-speed read cycle. As a result, the circuit scale of the cycle control unit can be reduced. In the semiconductor integrated circuit of the present invention, the optimal number of clock cycles for reading the second data can be set according to the environmental conditions such as temperature and voltage. Also, in the trial production of semiconductor integrated circuits, etc., the amount of memory array leakage can be indirectly evaluated by gradually changing the number of clock cycles.

In the semiconductor integrated circuit of the present invention, a selection failure of the first selection switch, such as a failure due to multiple selection of the first selection switch, can be detected. Also, the first data amplified by the sense amplifier can be securely held in the holding unit, and the second data amplified by the sense amplifier can be reliably compared with the first data held in the holding unit.

In the semiconductor integrated circuit according to the present invention, the first access cycle is repeated by repeating a predetermined access cycle. Data can be read continuously. By repeating a predetermined access cycle, the second data can be continuously read and compared with the first data. Since the frequency of switching access cycles can be reduced, the load on the cycle control unit can be reduced. Also, the first data amplified by the sense amplifier can be securely held in the holding unit, and the second data amplified by the sense amplifier can be reliably compared with the first data held in the holding unit.

In the semiconductor integrated circuit of the present invention, the first data of a plurality of bits read out to the bit line can be held at the same time, and the second data of the plurality of bits read out to the bit line is then stored in the second line. One day can be compared at a time. As a result, the test time can be significantly reduced. In addition, the first data amplified by the sense amplifier can be securely held in the holding unit, and the second data amplified by the sense amplifier can be reliably compared with the first data held in the holding unit. . .

Claims

The scope of the claims

(1) A semiconductor integrated circuit comprising: a built-in memory; and a controller that controls an operation of the built-in memory,

The internal memory is

A memory unit having a memory array composed of a plurality of memory cells;

A holding unit that holds the first data read from the memory cell as an expected value data;

A comparing unit for comparing the first data held in the holding circuit with a second data read again from a memory cell from which the first data has been read; , said a § access cycle of the memory array, wherein the semiconductor integrated circuit _c, characterized in that it comprises a cycle control unit for changing between when the when the first read data read out said second de Isseki

(2) In the semiconductor integrated circuit of Claim 1,

The semiconductor integrated circuit, wherein the cycle control section sets an access cycle for reading the second data longer than an access cycle for reading the first data.

(3) In the semiconductor integrated circuit of Claim 1,

The internal memory includes a plurality of data terminals that output data read from the memory cells,

The semiconductor integrated circuit, wherein the memory unit, the holding unit, and the comparison unit are formed for each of the data terminals.

(4) In the semiconductor integrated circuit of claim 3,

The semiconductor integrated circuit according to claim 1, wherein outputs of the comparison circuits respectively corresponding to the data terminals are connected to each other in a wire-doed manner and connected to a comparison result terminal of the built-in memory.

(5) In the semiconductor integrated circuit of claim 1,

A first program for executing a high-speed access operation for reading the first data from the memory cell, for reading the second data from the memory cell And a built-in ROM for storing a second program for executing the low-speed access operation of the first and second programs, and a third program for judging the comparison result of the first and second data.

The semiconductor integrated circuit according to claim 1, wherein the controller is a processor that sequentially executes the first, second, and third programs during a test mode.

(6) In the semiconductor integrated circuit of Claim 1,

The controller has the normal operation mode and the test mode, and outputs a test start signal during the test mode;

The cycle control unit formed in the internal memory includes a pattern generation circuit that operates in response to the test start signal and generates a test pattern for testing the memory array. Semiconductor integrated circuit. :

(7) In the semiconductor integrated circuit of claim 6,

The cycle control unit operates in synchronization with a clock, and sets the number of clock cycles for reading the second data to be greater than the number of clock cycles for reading the first data. Characteristic semiconductor integrated circuit.

(8) In the semiconductor integrated circuit of claim 7,

The semiconductor integrated circuit, wherein the cycle control unit generates a clock cycle for reading the second data by adding a dummy clock cycle to a clock cycle for reading the first data.

(9) In the semiconductor integrated circuit of claim 8,

The semiconductor integrated circuit according to claim 1, wherein the cycle control unit includes a register capable of externally setting the number of the dummy clock cycles to be added.

(10) In the semiconductor integrated circuit of Claim 1,

The semiconductor integrated circuit, wherein the cycle control unit operates during a test mode of the semiconductor integrated circuit.

(11) In the semiconductor integrated circuit of Claim 1,

The memory array comprises:

A plurality of bit lines respectively connected to the memory cells for transmitting the first and second data; The holding unit includes a holding circuit that holds one of the first data read from the memory cells accessed simultaneously to the bit line,

The memory unit,

A plurality of first selection switches respectively connected to the bit lines, and connecting any of the bit lines to a first node according to an address;

A write switch for connecting the first node to an input of the holding circuit during reading of the first data;

A semiconductor integrated circuit comprising: a comparing circuit configured to compare the second data transmitted to the first node with the first data output from the holding circuit. circuit.

(1 2) In the semiconductor integrated circuit of claim 11,

The semiconductor integrated circuit according to claim 1, wherein the memory unit includes a sense amplifier arranged between the first selection switch and the first node.

(13) In the semiconductor integrated circuit of claim 11,

The memory array includes a plurality of lead lines connected to the memory cells and selected according to an address,

The semiconductor integrated circuit according to claim 1, wherein the memory cells connected to the respective code lines are simultaneously accessed.

(14) In the semiconductor integrated circuit of Claim 1,

The memory array comprises:

A plurality of bit lines respectively connected to the memory cells for transmitting the first and second data;

The holding unit includes a plurality of holding circuits respectively corresponding to the bit lines and holding the first data read from the memory cells accessed at the same time to the bit lines,

The memory unit,

A plurality of first selection switches respectively connected to the bit lines and connecting any of the bit lines to a first node according to an address;

Any one of the holding circuits is connected to the holding circuit, depending on an address. A plurality of second selection switches connecting the second selection switch to the second node;

A write switch for connecting the first node to the second node during reading of the second data;

The comparison unit includes a comparison circuit that compares the second data transmitted to the first node with the first data transmitted from a holding circuit to the second node. Semiconductor integrated circuit.

(15) In the semiconductor integrated circuit of claim 14,

A semiconductor integrated circuit, wherein a pair of first and second selection switches corresponding to the respective bit lines among the first and second selection switches are simultaneously turned on. (16) In the semiconductor integrated circuit of claim 14,

The semiconductor integrated circuit according to claim 1, wherein the memory unit includes a sense amplifier arranged between the first node and the write switch.

(17) In the semiconductor integrated circuit of claim 14,

The memory array includes a plurality of word lines connected to the memory cells and selected according to an address.

The semiconductor integrated circuit according to claim 1, wherein the memory cells connected to the respective node lines are simultaneously accessed.

(18) In the semiconductor integrated circuit of Claim 1,

The memory array comprises:

The holding unit includes a plurality of holding circuits for holding the first data read out from the memory cells respectively corresponding to the bit lines and simultaneously accessed to the bit lines,

The memory unit,

A plurality of write switches respectively connecting the bit lines to the holding circuit during reading of the first data; The comparing unit is configured to compare the second data transmitted from the bit line to the first selection switch with the first data output from the holding circuit. A semiconductor integrated circuit comprising a circuit.

(19) In the semiconductor integrated circuit of claim 18,

The write switches and the first selection switches are connected to the bit lines via transmission nodes,

The semiconductor integrated circuit according to claim 1, wherein the memory unit includes a sense amplifier disposed between the bit line and the transmission node.

(20) In the semiconductor integrated circuit of claim 18,

The memory array includes a plurality of read lines connected to the memory cells and selected according to an address... The memory cells connected to each of the read lines are simultaneously accessed. Semiconductor integrated circuit. · (21) In the semiconductor integrated circuit of claim 18,

A semiconductor integrated circuit, wherein outputs of the comparison circuits are wired-OR connected to each other.

(22) The first data read from the memory cell of the memory array in the first access cycle is temporarily held as an expected value data,

Comparing the held first data with a second data read again from the memory cell from which the first data was read in a second access cycle;

A test method for a built-in memory mounted on a semiconductor integrated circuit, wherein a defect of the memory array is determined when the comparison result is different.

(23) The method for testing a built-in memory mounted on a semiconductor integrated circuit according to claim 22, wherein:

A method for testing a built-in memory mounted on a semiconductor integrated circuit, wherein the second access cycle is set longer than the first access cycle.