WO2004077692A1

WO2004077692A1 - Spread spectrum baseband signal processor with decimation filtering

Info

Publication number: WO2004077692A1
Application number: PCT/GB2004/000264
Authority: WO
Inventors: Christopher Nigel Smith; Zoran Dobrosavljevic
Original assignee: Roke Manor Research Limited
Priority date: 2003-02-25
Filing date: 2004-01-27
Publication date: 2004-09-10

Abstract

A baseband signal processor for a spread spectrum receiver comprises an input (20), an output (34), a despreading stage (21, 22), a filtering stage (23) and a frequency translation stage (24, 25, 26); wherein a signal received at the input is multiplied (21) with a despreading code (22) in the despreading stage to produce a narrowband signal; wherein the narrowband despread signal is filtered by a decimating low pass filter (23) in the filtering stage; wherein the filtered signal is multiplied (26) with an oscillator signal (24) to frequency translate the input to zero frequency in the frequency translation stage; and wherein the frequency translated signal is output (33) to a decoder. The decimation (23) allows to reduce the sampling rate, therefore reducing the overall acquisition time.

Description

SPREAD SPECTRUM BASEBAND SIGNAL PROCESSOR WITH DECIMATION FILTERING

This invention relates to a baseband signal processor for a spread spectrum receiver, in particular for satellite navigation. Conventional digital signal processing architecture in a baseband stage of a satellite navigation receiver is arranged to frequency translate a complex spread spectrum signal to zero frequency and then despread to recover a wanted signal. In satellite navigation systems currently being developed, such as Galileo, the input sample rate would need to be around 40MS/s in such an architecture, to support the typical input navigational signal bandwidth, with adequate anti-alias filtering. Existing satellite navigation systems, such as GPS have a sampling rate of 8 to 10 times less than this. Operating at the high rate required by Galileo places stringent demands on the hardware, which have not had to be addressed in past systems. Furthermore, achieving code and carrier synchronisation can take a very long time, so it is necessary to run many operations in parallel to achieve a sensible acquisition time and this adds to both cost and complexity.

In accordance with a first aspect of the present invention, a baseband signal processor for a spread spectrum receiver comprises an input, an output, a despreading stage, a decimating filtering stage and a frequency translation stage; wherein a signal received at the input is multiplied with a despreading code in the despreading stage to produce a narrowband signal; wherein the narrowband despread signal is filtered by a decimating low pass filter in the filtering stage; wherein the filtered signal is multiplied with an oscillator signal to frequency translate the input to zero frequency in the frequency translation stage; and wherein the frequency translated signal is output to a decoder.

The present invention reverses the order of the NCO and despreading stages of a conventional arrangement, and introduces an intermediate lowpass filter and sample rate reduction. The relatively simple despreading process can then be done at a high data rate, whilst the more complex processing required to get a frequency lock can be ' done in much slower time, giving rise to either better resolution and performance, or requiring less hardware to be used. Preferably, the oscillator signal is generated by a numerically controlled oscillator (NCO) and a Costas loop is used to lock the frequency and phase of the NCO to that of the input signal frequency.

The NCO is equivalent to a voltage controlled oscillator (VCO) for analogue signals.

Preferably, the processor further comprises a integrate and dump stage, wherein the frequency translated signal is passed through the integrate and dump stage before being output.

The integrate and dump stage provides an optimum means of accumulating the wanted signal energy and filtering the noise over the integration period.

Preferably, the processor further comprises an FFT based signal acquisition stage after the filtering stage, such that the frequency of the NCO can be set.

The FFT allows the narrowband signal at the output of the filtering stage to be resolved above the noise floor. In accordance with a second aspect of the present invention a direct conversion spread spectrum receiver comprises an antenna, an RF stage, a down-converter, a baseband signal processor according to the first aspect and a decoder.

An example of a baseband signal processor for a spread spectrum receiver will now be described and compared with a conventional system, with reference to the accompanying drawings in which:

Figure 1 is a simplified block diagram of conventional baseband processing architecture;

Figure 2 shows a conventional acquisition architecture; Figure 3 illustrates code and carrier uncertainty area; Figure 4 shows a first example of baseband signal processing architecture according to the present invention;

Figure 5 illustrates a second example of a baseband signal processor according to the present invention, with FFT based fast signal acquisition; and

Figure 6 illustrates the FFT based fast signal acquisition architecture of Fig. 5 in more detail.

Fig. 1 illustrates, in simplified form, a conventional baseband digital signal processing architecture, typically used in satellite navigation receivers. For the purpose of these examples, frequencies are chosen in accordance with Galileo E5a/b signal reception and all signals are processed as complex. For clarity, some of the acquisition and tracking elements have been omitted from these figures. In Fig. 1, an incoming digitised complex spread spectrum signal from a direct conversion receiver front end and analogue to digital converters is input 1 and multiplied 2 by in-phase and quadrature numerically controlled oscillator (NCO) signals 3, to frequency translate the input to zero frequency. In a direct conversion design, the input frequency typically will be offset by a few kHz from zero due to Doppler shift and local oscillator frequency error, hence the need for this NCO multiplier stage. The translated output 4 comprises a slow data sequence , superimposed on a fast random sequence. This output is then multiplied 5 with a despreading code 6 to remove the fast random sequence and integrated 7 over a multiple of the sequence length in order to recover a wanted signal with a positive signal to noise ratio (SNR). Due to frequency error, a Costas loop 8 is used on the despread signal to phase lock the receiver to the incoming signal frequency. In a Galileo application, the input sample rate will need to be around 40MS/s, in order to support the typical Galileo input signal bandwidth, of +/-12MHz for the E5a/b signal, with adequate anti-alias filtering. Consequently, almost all of the processing blocks (NCO, despreading etc.) shown have to operate at this high rate, placing ■ stringent demands on the hardware requirements. A further drawback is that during the initial acquisition phase, both code and carrier synchronisation must be achieved simultaneously, potentially resulting in very long acquisition times from a 'cold' start. There can be about 1000 frequency steps to get to the correct value and the spreading sequence can be up to 100ms long with up to 1,023,000 chips, but the starting point in this sequence is not known. The steps are ^lA a chip at a time, so up to 2 million steps which in combination with the frequency stepping requirement means that finding the signal can take a very long time. In fact it is quite impractical, because at its limits, it could take months to find the signal, so parallel operation is required to get a manageable acquisition time. This is expensive and complex in hardware-terms. In order to estimate the acquisition complexity, a simplified receiver block diagram during acquisition is given in Fig. 2. This diagram shows a sequential acquisition approach. All operations are done with complex baseband signals. During acquisition, a received signal 10 is demodulated 11 with a local carrier from an NCO 12 and despread 13 with a local code 14. If the carrier frequency and code delay are correct, an integrate and dump output 15 will be above 16 an acquisition threshold 17 and a decision circuit 18 will detect synchronism. If the decision sample is below 19 the threshold, the NCO frequency and/or despread code will have to be changed by values Δf and Δτ, respectively, as shown in Fig. 3. The required number of delay and Doppler search steps can be estimated in the following manner. During the acquisition, the total code and carrier uncertainty area that has to be searched is as shown in Figure 3. Rectangle 20 shows the full delay- Doppler area that has to be searched during acquisition. Small square 21 shows a "resolution cell" that is searched in one acquisition dwell. For the purpose of this analysis, the following Galileo E5 signal parameter values will be used:

Sequence period L=l ,023,000 (dataless sub-signal, E5a-Q or E5b-Q); Chip rate = 10.23 MHz, therefore integration time T - 0.1 s; Delay step size Δτ = Tc/2; where Tc is the chip period (= 1/Chip rate) Total number of delay steps Nτ= LTc / (Tc/2) = 2,046,000; Maximal Doppler shift fd = 6 kHz;

Doppler step size Δf = decision rate = 10 Hz; Total number of Doppler steps Nf = 2fd/Δf = 1200. The number of cells that has to be searched: Nτ*Nf Thus, the average acquisition time: T*Nτ*Nf / 2 = 122.8*10⁶ s. The huge time required to acquire a code and carrier synchronisation can be reduced by massive replication of the circuit shown in Figure 2. In order to reduce the acquisition time to acceptable an acceptable amount, e.g. 120 s, the receiver would need to have approximately 10⁶ such circuits in parallel. For carrier demodulation implemented with reasonable bit precision (i.e. more than 1-2 bits), this approach to acquisition would require high-speed digital multipliers in every parallel unit.

Therefore, requirements on the amount of high-speed digital resources in the parallel approach to acquisition are extremely demanding.

The present invention addresses these problems by using a new baseband digital signal processing architecture. The architecture is particularly applicable for satellite navigation direct conversion receivers, but is not limited to satellite applications. The new design enables improved performance, reduced hardware complexity, fast signal acquisition, and lower cost, particularly when used in Galileo applications. A first example of the present invention is shown in Fig. 4, all signal paths being complex. In Fig. 4, a spread spectrum input 20 from a direct conversion receiver front end and ADC's, is first multiplied 21 with a despread code 22 and then passed through a decimating lowpass filter 23, giving an output of limited bandwidth. It can be seen that the output from the despreading process is a single tone offset from zero by an amount equal to the Doppler shift, plus any local frequency error.

By doing the despreading first, the effect of the spreading is undone, but the Doppler error is still present. The signal will be very narrowband, of the order of 100s of Hz, with an unknown frequency error of +/- a few kHz. After the first multiplier step 21, the filter 23 is applied with a bandwidth of e.g. 10kHz. The signal bandwidth, and hence sample rate, can therefore be drastically reduced at this point, using simple decimating lowpass filters. There may also be narrowband data modulation sidebands associated with the tone, but these do not significantly affect the required bandwidth. This means that the subsequent processing can be done in much slower time, so either better resolution and better performance is achieved, or else less hardware can be used. Conventionally, the NCO is very crude, typically less than 3 bits resolution, so the performance is not very good. In this invention, a much higher resolution NCO can be used (eg. 8 bits), so the performance is improved.

For the example of Gallileo, the expected worst case Doppler shift is around 6kHz, so the bandwidth can safely be reduced to 10kHz, and consequently, the sample rate reduced to 20kS/s. This is a 2000 fold decrease in sampling rate over the conventional arrangement of Fig.1.

A stage to translate the final frequency to zero uses an NCO 24 within a Costas loop 25 as before and multiplies 26 the NCO signal with the despread signal, except that now, for the Galileo example, the processing only needs to operate at 20kS/s, rather than 40MS/s. Consequently, a high resolution NCO may be used, giving negligible quantisation noise. Then the signal is passed through an integrate and dump stage 27, using a data symbol rate of 50 sym/s and output 34 to a decoder. It can be seen from Fig. 4 how the wanted signal 28 is spread out over the frequency range and below the white noise level 39 before processing, but that after despread and filter stages, although the band limited white noise 29 remains, the wanted signal 30 is a sharp, narrow peak and easily distinguished. Another benefit of the new architecture is that the multiplication required by the despreading process becomes trivial, since the despreading code is a 1 bit signal. The multipliers thus reduce to simple toggling of the input sign.

A further benefit of the being able to operate at low speed is that a complex fast Fourier transform (FFT) can be used to help with removing the frequency offset. In the arrangement of Fig. 5, it is no longer necessary to step the NCO 24 over the expected frequency error range during acquisition. Instead, the FFT is used to resolve the despread tone with a sufficiently narrow resolution bandwidth to allow it to be discerned above the noise floor. The FFT output can therefore be used to control the initial code phase acquisition, and set the initial centre frequency of the Costas loop NCO. The FFT 31 is applied to the signal output from the low pass filter 23 to give a sharp indicator of where the signal frequency is, then summed 33 with the output of the Costas loop 25, so that the NCO is directed to that frequency to avoid stepping through every possible frequency first. This provides a means of achieving fast signal acquisition with only a small processing overhead.

The FFT-based acquisition scheme is shown in more detail in Fig. 6. During acquisition, a received signal is despread 21, 22 and then decimated 23 to 20 kS/s, in accordance with the highest possible Doppler shift. Downsampled signal blocks of 100 ms duration (2048 samples) are then FFT-transformed 31. At the output of the FFT, a decision circuit 32 detects a frequency bin that is above threshold. This bin corresponds to the Doppler offset of the input signal. In the FFT-based acquisition, despreading is done by a single-bit multiplier, which corresponds to sign change. Immediately after despreading, significant decimation of the signal enables the FFT to be done on a low sample rate signal (20 kS/s), which can be done in high precision even with modest hardware resources.

With the same numbers assumed as in the previous example, required acquisition time now becomes: Average acquisition time: T*Nτ 12 = 102.3*10³ s.

This is three orders of magnitude less than required for a parallel search. With a reasonable amount of parallelism (1000 times), acquisition can be performed in 102 seconds on average. Again, the processing units that have to be replicated in the highspeed (40 MHz) domain are simple sign inverters, while FFTs are running on a low data rate signal, rather than high-speed digital multipliers. The present invention avoids the need to achieve simultaneous carrier phase synchronisation during the code synchronisation process, and thus offers the potential for a large reduction in overall acquisition time. The invention is applicable to any type of receiver, but the input signal needs to be brought to zero frequency first, for the full benefits to apply. Use of direct conversion receivers is uncommon with GPS and the frequency range is such that the benefits would not be so significant, however future systems, such as Galileo have a higher sampling rate, to which the invention is particularly applicable. The data rate of a satellite navigation transmissions will always be low because of the distance it has to travel, so the spreading code rate is likely to increase in the future, rather than reduce.

Although the examples have been given for a satellite navigation receiver, another application for the invention is in communications systems, which use spread spectrum modulation. Such applications could also take advantage of the new architecture in the communication system receiver, and therefore benefit from reduced hardware complexity.

Claims

1. A baseband signal processor for a spread spectrum receiver, the processor comprising an input, an output, a despreading stage, a decimating filtering stage and a frequency translation stage; wherein a signal received at the input is multiplied with a despreading code in the despreading stage to produce a narrowband signal; wherein the narrowband despread signal is filtered by a decimating low pass filter in the filtering stage; wherein the filtered signal is multiplied with an oscillator signal to frequency translate the input to zero frequency in the frequency translation stage; and wherein the frequency translated signal is output to a decoder.

2. A signal processor according to claim 1, wherein the oscillator signal is generated by a numerically controlled oscillator (NCO) and a Costas loop is applied to lock the frequency of the NCO to the input signal frequency.

3. A signal processor according to claim 1 or claim 2, further comprising an integrate and dump stage, wherein the frequency translated signal is passed through the integrate and dump stage before being output.

4. A signal processor according to any preceding claim, further comprising an FFT based signal acquisition stage after the filtering stage, such that the frequency of the NCO can be set.

5. A direct conversion spread spectrum receiver comprising an antenna, an RF stage, a down-converter, a baseband signal processor according to any preceding claim and a decoder.

6. A baseband signal processor for a spread spectrum receiver as hereinbefore described with reference to Figs. 4 to 6.