WO2004077661A1

WO2004077661A1 - Power amplifying device

Info

Publication number: WO2004077661A1
Application number: PCT/CN2003/000143
Authority: WO
Inventors: James Peroulas
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2003-02-25
Filing date: 2003-02-25
Publication date: 2004-09-10
Also published as: CN100452645C; CN1695296A; AU2003210120A1

Abstract

A power-amplifying device is disclosed. The power amplifying device comprises a decomposer (101), a first D/A converter (102), a second D/A converter (103), a f first power amplifier (105), a second power amplifier (106), a signal combiner, (107) and a crossbar switch (108) for switching the decomposed digital signals. With this power-amplifying device, a complex network is not needed to compensate for amplifier imbalance and neither is a complex measurement device required to measure the absolute performance of every component.

Description

POWER AMPLIFYING DEVICE

FIELD OF THE INVENTION

The present invention generally relates to the field of power amplification devices, and more particularly to techniques for improving the linearity and/ or efficiency of power amplifying devices.

BACKGROUND OF THE INVENTION

In cellular base stations, satellite communication systems, as well as other communication and broadcasting systems of today, the final step in a transmitter always involves the amplification of a low power signal to the power level that is required by the transmission medium. As an example, in a radio communications transmitter, the source information signal may have a power level of about 1 milliwatt whereas the radio channel may require a transmit power ten thousand times greater at about 10 watts . The process of amplifying such a low power signal to a high power level is called power amplification and is accomplished through the use of a power amplifier. The power amplifier has some very difficult requirements . It must accurately amplify the source signal, it must not distort the source signal, it must not transmit energy outside the frequency range of the source signal, it must act on the entire bandwidth of the source signal, and it must do all of the above in a very efficient manner. For a fixed architecture and process technology, the classical tradeoffs have been between bandwidth, efficiency, and linearity. Improving one parameter necessarily reduces the performance of the other parameters .

In the past , power amplifier design problems have been avoided (not solved) by modulating the information signal in such a way that the result of the modulation was easy to amplify. As an example, a source signal that has been Frequency Modulation (FM) modulated can be amplified to high power levels using cheap and efficient class C amplifiers. Unfortunately, modulation schemes that are easy to amplify are out of favor nowadays because these modulation schemes are typically either spectrally inefficient (ex. FM) or inefficient in their use of transmitted power (ex. Amplitude Modulation (AM) ) .

Modern modulation schemes such as QAM do not allow any tricks to be used and the power amplification problem can no longer be avoided. Modern transmitters must accept wide bandwidth signals where the information is carried both in the amplitude and the phase of the transmitted signal . Several architectures have been proposed to create an efficient , wide bandwidth, linear amplifier and one such architecture is called LINC, which stands for Linear amplification using Non-linear Components architecture. This type of amplifier also goes by the names of an "Chireix amplifier" or an "Out hasing amplifier" .

Figure 1 is a schematic block diagram of a power amplifying device in a conventional LINC architecture. As seen from figure 1, the power amplifying device 100 comprises a decomposer 101, a pair of D/A converters 102, 103, a modulator 104, a pair of power amplifiers 105, 106 and an combiner 107. The decomposer 101 is used to split a phase and amplitude modulated signal s (n) into two signals si (n) and s2 (n) . The D/A converters 102 and 103 are used to convert the obtained digital signals si (n) , s2 (n) into analog signals sl(t), s2 (t) . The modulator 104 respectively modulates the first analog signal si (t) and the second analog signals s2(t) with a carrier frequency fc. For example, in the case of 3GPP, the information is moved up to a carrier frequency of approximately 2 GHz. The power amplifiers 105, 106 amplify the modulated analog signals to create amplified signals xl(t) and x2 (t) . Then the amplified signals are combined by the combiner 107 and the result x(t) is transmitted through an antenna.

The fundamental principle of such power amplifying device is that the source signal s (n) is decomposed into two component signals si (n) and s2 (n) such that s (n) =sl (n) +s2 (n) . The component signals each have the property that for all values of n, their magnitude is always constant. In other words, the source signal, which contains both amplitude and phase variations, has been decomposed into two signals that have only phase variations .

The following equations (1) and (2) describe the signal decomposition operation and assume that s (n) is constrained so that its magnitude is less than or equal to 1.

Where s (n) is a digital source signal, si (n) is the first decomposed digital signal, s2 (n) is the second decomposed digital signal, n is the time index. The reason why this architecture has received attention is that although it requires two power amplifiers, the power amplifiers in this architecture are much easier to construct than a single power amplifier because the signals going into these power amplifiers have characteristics that are easier to amplify.

This architecture has seen limited real world use because it is very sensitive to gain and phase imbalances between the two amplifiers.

Figure 2a is a graph showing the out of band noise introduced due to a gain imbalance of 0.25 dB between the two power amplifiers in the conventional method. The X-axis represents frequency and ranges from -fs/2 to +fs/2. fs is the sampling rate of the D/A converters 102, 103 and is also equal to the sampling rate of the digital source signal s (n) , and the two component signals si (n) and s2 (n) . The Y-axis represents signal power measured in dB and is useful for relative measurements.

Figure 2b is a graph showing the result of zooming on the passband of figure 2a. The two graphs in figure 2a and figure 2b are the result of plotting the same data, but on different scales.

It can be seen from figure 2a and figure 2b that a 0.25 dB gain imbalance between the two power amplifiers 105, 106 causes out of band noise to begin to appear about 30 dB below the passband.

Furthermore, for a given gain imbalance, the noise introduced does not scale with the input power. For example, in the conventional architecture shown above, with a full power input signal, the out of band emissions are 30 dB below the passband. If the input power is reduced by 12 dB (for example) , the out of band emissions will not go down by 12 dB. They will stay at a fixed absolute power level. The sensitivity to gain imbalance has usually been solved either with a complex network to compensate for the amplifier imbalance. Or with a complex measurement device to measure the performance of every component to make sure that only devices with a similar performance are used.

The high amount of out of band noise introduced by the amplifier causes interference in the adjacent channels . This interference affects performance in several different ways .

First, the interference will introduce errors in the transmission. These errors must be corrected and will require a retransmission or some other form of error correction. This error correction takes time and is seen by the user as a delay or as sluggish response from the system.

Second, in order to overcome the interference, other transmitters must increase their output power which will automatically increase their power consumption. Increased power consumption will be seen by a mobile user as a limit on the amount of time the user can use the mobile before the batteries run out. Increased power consumption will be seen by a fixed operator as requiring heavy cables to power the transmitter and also requiring heavy backup batteries to be used when main power fails.

THE SUMMARY OF THE INVENTION

The object of the invention is to solve the above-mentioned problems that existed in the prior art by providing a power amplifying device in which no complex network is needed to compensate for amplifier imbalance, in which no complex measurement device is required to measure the absolute performance of every component, in which user response time is improved, in which battery life is increased, and in which heavy cables and backup batteries are not needed.

In order to achieve the above object, a power amplifying device is provided. The power amplifying device comprises : a decomposer for decomposing a digital source signal into a first digital component signal and a second digital component signal; a first D/A converter for converting a first switched digital signal into a first analog signal; a second D/A converter for converting a second switched digital signal into a second analog signal; a first power amplifier for amplifying the first analog signal to obtain a first amplified signal; a second power amplifier for amplifying the second analog signal to obtain a second amplified signal; a signal combiner for combining the first amplified signal and the second amplified signal to obtain an output signal; wherein said power amplifying device further comprises a crossbar switch for switching the decomposed digital signals and outputting the first switched digital signal to the first D/A converter, and the second switched digital signal to the second D/A converter.

In accordance with the present invention, a complex network is not needed to compensate for amplifier imbalance. Neither is a complex measurement device required to measure the absolute performance of every power amplifier. The battery life of mobile units is improved. Also, heavy cables and backup batteries are not needed.

BRIEF DESCRIPTION ON THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

Figure 1 is a schematic block diagram of a power amplifying device in a conventional LINC architecture;

Figure 2a is a graph showing the out of band noise introduced due to gain imbalance of two power amplifiers in a conventional method;

Figure 2b is a graph showing the result of zooming on the passband of figure 2a;

Figure 3 is a schematic block diagram of a power amplifying device of the embodiment according to the invention;

Figure 4a is a graph showing the out of band noise introduced due to gain imbalance of two power amplifiers according to the present invention;

Figure 4b is a graph showing the result of zooming on the passband of figure 4a;

Figure 5a is a graph showing the out of band noise introduced due to gain imbalance of two power amplifiers according to the present invention; and

Figure 5b is a graph showing the result of zooming on the passband of figure 5a.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be described in detail in accordance with the accompanying drawings. A schematic configuration of a power amplifying device 300 in the present embodiment of the invention will be described with reference to figure 3 , which is a schematic block diagram of a power amplifying device of the embodiment according to the invention. It is preferred that the digital source signal of the power amplifying device is a full power input signal. For instance, if the peak power of the digital source signal is assumed to be 0 dB, and the peak to average ratio is assumed to be 10 dB, the largest value of the average input power will be -10 dB. With such an average input power, the gain of the amplifiers is chosen so that the output power in watts is equal to the desired level of output power. For instance, if the desired output power is 10 watts or 40 dBm, this amount of power will be produced when the input signal power is at -10 dB .

As shown in figure 3, the power amplifying device 300 according to the invention comprises a decomposer 101, a first D/A converter 102, a second D/A converter 103, a modulator 104, a first power amplifier 105, a second power amplifier 106, and a combiner 107. The power amplifying device 300 further comprises a crossbar switch 108. In this particular embodiment, the decomposer 101 is a digital device for splitting a digital source signal s (n) into to two component signals, i.e., a first digital component signal kl (n) and a second digital component signal k2 (n) . The decomposer 101 is connected to the crossbar switch 108. The crossbar switch 108 will, on a sample by sample basis, decide whether to swap the values of the decomposed digital component signals kl (n) , k2 (n) .

The decomposed digital component signals kl (n) , k2 (n) outputted from the decomposer 101 are sent to the first D/A converter 102 and the second converter 103 via the crossbar switch 108. For any time index n, the crossbar switch 108 will either assign si (n) to be equal to kl (n) and s2 (n) to be equal to k2 (n) . OR, it will assign si (n) to be equal to k2 (n) and s2 (n) to be equal to kl (n) . ie, on a sample by sample basis, the crossbar switch 108 may exchange the values of kl (n) and k2 (n) before creating si (n) and s2 (n) . As seen from figure 3, the first D/A converter 102 converts a first switched digital signal si (n) into a first analog signal sl(t) . Similarly, the second D/A converter

103 converts a second switched digital signal s2 (n) into a second analog signal s2 (t) .

The first D/A converter 102 and the second converter 103 are connected to the modulator 104. The modulator 104 respectively modulates the first analog signals si (t) and the second analog signals s2(t) with a carrier frequency fc. Thus, a first modulated signal ml(t) and a second modulated signal m2 (t) can be obtained and input respectively to the first power amplifier 105 and the second power amplifier 106. The outputs of the power amplifiers are xl(t) and x2(t) respectively. It should be noted that the modulator 104 is optional . Even if the desired carrier frequency fc is zero, the power amplifying device will work. In other words , the modulation operation does not affect any of the properties of the power amplifying device, which are equally valid for a carrier frequency of OHz as they are valid for a carrier frequency of, for example, 2 GHz.

Referring to figure 3, the first power amplifier 105 amplifies the first modulated signal ml(t) to obtain a first amplified signal xl(t) . According to the present invention, the crossbar switch 108 can be used to shape the noise introduced by power amplifier imbalances. The noise shaping procedure will cause the adjacent channel noise power to go down and will thus relax the requirements on the gain imbalance between the power amplifiers 105, 106. For instance, whereas the original architecture required a 0.25 dB gain balance between the power amplifier 105, 106 to reduce the out of band noise to -30 dBc, the power amplifying device 300 according to the present invention can reduce the out of band noise to -30 dBc with only a 1 dB gain balance. As seen from figure 3, after the crossbar switch 108, the decomposed digital component signals kl (n) , k2 (n) are converted to digital signals si (n) , s2 (n) , which are respectively input to the first D/A converter 102 and the second D/A converter 103. From the above-mentioned equations (1) and (2) , the digital signals input into the first and the second D/A converters 102 and 103 can be determined by:

Where s (n) is a digital source signal, si (n) is the first switched digital signal inputted into the first D/A converter 102, s2 (n) is the second switched digital signal inputted into the second D/A converter 103; p (n) either takes on the value +1 or -1, n is the time index..

As seen from equations (3) and (4) , if p (n) is 1, no switch takes place. If p (n) is -1, then the digital components are swapped, in that the first digital component signal kl (n) is sent to the second D/A converter 103, and the second digital component signal k2 (n) is sent to the first D/A converter 102. Depending on how p(n) is chosen, one can shape the adjacent channel noise that is produced. Figure 4a, figure 4b is an example of the output of the present invention for a p (n) function where the value of the function is randomly determined and has an equal probability of being +1 or -1. figure 4b is a graph showing the result of zooming on the passband of figure 4a. The two graphs in figure 4a and figure 4b are the result of plotting the same data, but on different scales.

In figure 4a and figure 4b, with a gain imbalance of 0.25 dB, one sees that the noise introduced is flatter than it was in the prior art. This flattened noise has a better adjacent channel performance of about 31 dBc as compared with 30 dBc with the original architecture shown in figure 1.

Figure 5a, figure 5b is another example of the output of the present invention for a p (n) function where in this case, the p (n) function alternates between +1 and -1 for every value of n, i.e. p(n)=-ln. figure 5b is a graph showing the result of zooming on the passband of figure 5a. The two graphs in figure 5a and figure 5b are the result of plotting the same data, but on different scales.

In Figure 5a, one can see that most of the noise energy has been moved far away from the passband and a great decrease in adjacent channel noise can be observed. With this p (n) function, the adjacent channel noise is down to 55 dBc.

Although this invention has given several examples of p (n) functions, more functions can be created to shape the noise produced to make it follow some design criteria. For instance, one may wish to to create a certain stair-wise noise pattern and a p (n) function could be made to create noise with that particular noise pattern.

Furthermore, a p (n) function can be created that analyzes the signals s (n) , si (n) , and s2 (n) directly to determine whether a swap should be performed. That is, this function would take into account the current time index n, the values of s before, during, and after the current time index, and the values of si and s2 before, during, and after the current time index.

Furthermore, the primary use of the invention is in the RF field. It is not limited, however, to only amplify radio signals. One could also use this technique to amplify light signals or another energy carrying signal. Although most of the benefits of the architecture are realized when the source signal is an amplitude and phase modulated signal, the present invention still has benefits when the source signal is only amplitude modulated or only phase modulated.

As many apparently widely different embodiments of the present invention can be made without departing from the spirit and scope thereof, it is to be understood that the invention is not limited to the specific embodiments thereof except as defined in the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A power amplifying device comprising: a decomposer (101) for decomposing a digital source signal (s (n) ) into a first digital component signal (kl (n) ) and a second digital component signal (k2 (n) ) ; a first D/A converter (102) for converting a first switched digital signal (si (n) ) into a first analog signal (sl(t)); a second D/A converter (103) for converting a second switched digital signal (s2 (n) ) into a second analog signal (s2(t)) ; a first power amplifier (105) for amplifying the first analog signal (sl(t)) to obtain a first amplified signal (xl(t)) ; a second power amplifier (106) for amplifying the second analog signal (s2 (t) ) to obtain a second amplified signal (x2 (t) ) ; a signal combiner (107) for combining the first amplified signal (xl(t)) and the second amplified signal (x2 (t) ) to obtain an output signal x(t); wherein said power amplifying device further comprises a crossbar switch (108) for switching the decomposed digital component signals (kl (n) , k2 (n) ) and outputting the first switched digital signal (si (n) ) to the first D/A converter (102) , the second switched digital signal (s2 (n) ) to the second D/A converter (103) .

2. The power amplifying device according to claim 1, wherein said power amplifying device further comprises a modulator (104) for modulating respectively the first analog signal (sl(t)) and the second analog signal (s2(t)), to be sent respectively to the first power amplifier (105) and the second power amplifier (106) , to a desired carrier frequency (fc) .

3. The power amplifying device according to claim 1 or 2, wherein the digital signals inputted into the first and the second D/A converters 102 and 103 can be determined by:

Where s (n) is a digital source signal, si (n) is the first switched digital signal inputted into the first D/A converter (102), s2 (n) is the second switched digital signal inputted into the second D/A converter (103) , p (n) either takes on the value +1 or -1, n is the time index.

4. The power amplifying device according to claim 3, wherein the value of p (n) is randomly determined and has an equal probability of being +1 or -1.

5. The power amplifying device according to claim 3, wherein p(n) = (-l) , where n is the time index.

6. The power amplifying device according to claim 3, wherein the value of p (n) depends only on the value n, other than p(n)=l, where n is the time index.

7. The power amplifying device according to claim 3, wherein the value of p (n) depends both on the time index n, and on the past, current, and future values of s (n) , si (n) , and s2 (n) .