WO2004070729A1

WO2004070729A1 - Semiconductor memory

Info

Publication number: WO2004070729A1
Application number: PCT/JP2003/001167
Authority: WO
Inventors: Kazufumi Komura
Original assignee: Fujitsu Limited
Priority date: 2003-02-05
Filing date: 2003-02-05
Publication date: 2004-08-19

Abstract

During a partial refresh mode when only the memory cells in a partial area are refreshed, the least significant bit of a refresh address counter is converted into the most significant bit. The most significant bit of the refresh address is reversed upon each refresh request, and the memory area selected is successively switched each time the refresh address is updated. Accordingly, it is possible to obtain an identical interval of refresh operation without using a special divider. As a result, it is possible to reduce the semiconductor memory chip size. Since the refresh operation can be distributed, the current consumption during the partial refresh mode can be measured in a short time, thereby reducing the manufacturing cost. It is possible to minimize the frequency of the refresh operations, which in turn reduces the power consumption during the partial refresh mode.

Description

Description '' Semiconductor memory ^ ^

The present invention relates to a semiconductor memory having DRAM memory cells, and more particularly to a semiconductor memory having a partial refresh mode for inhibiting a refresh operation of some memory cells. Background art

In recent years, mobile devices such as mobile phones that operate on batteries have become widespread. The semiconductor memory mounted on these mobile devices is required to have low power consumption in order to make the battery usable for a long time. In particular, low power consumption during standby is desirable for semiconductor memories used in mobile phones. In addition, mopile devices that handle large amounts of data, such as images, are increasing. Work memories of these mobile devices are increasingly being replaced by SRAMs with small storage capacity and high bit unit cost, and DMMs with large storage capacity and low bit unit cost. As a result, DRAMs with low power consumption are demanded for these mopile devices.

DRAMs with partial refresh mode have been developed to reduce standby power consumption. This type of DRAM reduces power consumption by prohibiting the refresh operation of some memory cells during standby (during partial refresh mode).

Further, a technique for further reducing the power consumption during the partial refresh mode is disclosed in Japanese Patent Application Laid-Open No. 2000-150780. In this publication, during the partial refresh mode, the number of bits of the refresh address counter for generating the refresh address is reduced, and the period of the timer for generating the refresh request is lengthened by using the frequency divider. The power consumption during the partial refresh mode is reduced by lengthening the generation interval of the refresh request. Hereinafter, prior art documents related to the present invention are listed.

(Patent Document)

(1) Japanese Patent Publication No. 200 00—15 7880 (P.7, Fig. 8 ~: 13)

An object of the present invention is to reduce power consumption during a partial refresh mode in which a refresh operation of some memory cells is prohibited.

Another object of the present invention is to reduce the power consumption during the partial refresh mode while minimizing the increase in the circuit size.

Another object of the present invention is to provide a semiconductor memory that can operate stably while reducing power consumption during the partial refresh mode.

In one embodiment of the present invention, the memory array has dynamic memory cells and has a plurality of memory areas partitioned by upper bits of an address. At least one of the memory areas operates as a partial area, and the remaining memory areas operate as non-partial areas. During the partial refresh mode, which is one of the low-power modes, and the partial refresh mode, a refresh operation is performed to hold the data held in the memory cells in the partial area. Is done. In the non-partial area, the refresh operation is performed during the non-partial refresh mode, and the refresh operation is prohibited during the partial refresh mode. In the refresh period, a refresh request for refreshing a memory cell is generated at a predetermined cycle. The refresh address counter sequentially generates a refresh address consisting of a plurality of bits indicating a memory cell to be refreshed in response to a refresh request.

The refresh address change circuit outputs the lower bit of the output of the refresh address counter as an upper bit to the memory array during the partial refresh mode, and sequentially shifts the remaining bits to the lower bit side. And outputs it to the memory array. Therefore, during the partial refresh mode, the upper bits of the refresh address are inverted each time. The selected memory area is sequentially switched every time the refresh address is updated. On the other hand, during non-partial refresh mode, The cache address changes sequentially from the lower bit. The selected memory area is sequentially switched each time the refresh address is updated a plurality of times.

The refresh control circuit generates a refresh start signal in response to the refresh request only when the refresh address indicates the partial area in the partial refresh mode, and starts the refresh in response to the refresh request in the non-partial refresh mode. Generate a signal. Therefore, when the refresh address indicates a non-partial area during the partial refresh mode, the refresh request is masked. Therefore, a frequency divider for dividing a refresh request (pulse) operating during the partial refresh mode is not required. As a result, the chip size of the semiconductor memory can be reduced. Also, the frequency of refresh operations can be minimized by masking the refresh requests corresponding to the non-partial areas. As a result, power consumption during the partial refresh mode can be reduced with a simple circuit.

During the partial refresh mode, the refresh operation is not executed in the refresh address that does not indicate the partial area. For this reason, the interval of the refresh operation can be made uniform during the partial refresh mode. Since the refresh operation can be dispersed, the current consumption in the partial refresh mode can be measured in a short time. Specifically, current consumption can be accurately measured in a period in which refresh requests are generated several times. As a result, the test time can be reduced, and the manufacturing cost can be reduced. In another aspect of the invention, a refresh address change circuit has a plurality of multiplexers for selecting a first input during a non-partial refresh mode and selecting a second input during a partial refresh mode. are doing. The first input of the multiplexer is connected to the output bit of the refresh address counter. The second input of the multiplexer corresponding to the most significant bit of the refresh address count is connected to the least significant bit of the output bit of the refresh address count. The second input of the remaining multiplexer is connected to the next higher bit of the corresponding output bit in the refresh address count. In this way, by shifting one bit of the output bit of the refresh address counter during the partial refresh mode by the simple multiplexer, the refresh of the partial area is performed. Operation can be distributed.

In another aspect of the present invention, a refresh address change circuit has a plurality of multiplexers for selecting a first input during a non-partial refresh mode and selecting a second input during a partial refresh mode. The first input of the multiplexer is connected to the output bit of the refresh address counter. The second input of the multiplexer corresponding to the second highest bit of the refresh address count is connected to the least significant bit of the output bit of the refresh address count. The second input of the multiplexer corresponding to the most significant bit of the refresh address count is connected to the second lowest bit of the output bits of the refresh address count. The second input of the remaining multiplexer is connected to the next higher bit of the corresponding output bit in the refresh address count. As described above, by shifting the two bits of the output bit of the refresh address counter during the partial refresh mode by the simple multiplexer, the refresh operation of the partial area can be dispersed.

In another embodiment of the present invention, the refresh frequency in the partial refresh mode is n / m of the refresh frequency in the non-partial refresh mode, where m is the number of memory areas and n is the number of partial areas. Is set. Since the frequency of the refresh operation is reduced, the current consumption during the partial refresh mode can be reduced.

In another embodiment of the present invention, each memory region has a plurality of word lines connected to the memory cells, respectively. One of the memory areas is selected by the upper bits of the refresh address. One of the lead lines in the selected memory area is selected by the remaining refresh address bits. During partial refresh, refresh operations can be distributed by sequentially selecting word lines in different memory areas instead of sequentially selecting adjacent code lines in the same memory area and performing the refresh operation. .

In another form of the semiconductor memory of the present invention, the memory array has a dynamic memory cell and is constituted by a plurality of memory areas partitioned by upper bits of an address. At least one of the memory areas operates as a partial area and the remaining The memory area operates as a non-partial area. During the partial refresh mode, which is one of the low-power modes, and during the non-partial refresh mode, the partial area has a refresh operation for holding the data held in the memory cells. Be executed. In the non-partial area, the refresh operation is performed during the non-partial refresh mode, and the refresh operation is prohibited during the partial refresh mode.

The refresh timer generates a refresh request of a memory cell at a predetermined cycle. The refresh address counter has a plurality of flip-flops connected in series to output a refresh address composed of a plurality of bits indicating a memory cell to be refreshed, and sequentially generates a refresh address in response to a refresh request. .

The refresh address change circuit connects the output of the highest flip-flop to one of the inputs of the lowest flip-flop during the partial refresh mode, and supplies the refresh request to the input of the high-order flip-flop. Therefore, during partial refresh mode, the upper bits of the refresh address are inverted each time. The selected memory area is sequentially switched every time the refresh address is updated. On the other hand, during the non-partial refresh mode, the refresh address changes sequentially from the lower bit. The selected memory area is sequentially switched every time the refresh address is updated a plurality of times.

The refresh control circuit generates a refresh start signal in response to the refresh request only when the refresh address indicates the partial area during the partial refresh mode, and responds to the refresh request during the non-partial refresh mode. Generate a refresh start signal. Therefore, when the refresh address indicates a non-partial area during the partial refresh mode, the refresh request is masked. Therefore, a frequency divider for dividing a refresh request (pulse) that operates during the partial refresh mode is not required. As a result, the chip size of the semiconductor memory can be reduced. Also, the frequency of refresh operations can be minimized by masking the refresh requests corresponding to the non-partial areas. As a result, the power consumption during partial refresh mode can be reduced with a simple circuit. Can be reduced.

During the partial refresh mode, the refresh operation is not executed in the refresh address that does not indicate the partial area. Therefore, the intervals of the refresh operation can be made uniform during the partial refresh. Since the refresh operation can be distributed, the current consumption in the partial refresh mode can be measured in a short time. Specifically, current consumption can be accurately measured in a period in which refresh requests are generated several times. As a result, the test time can be reduced, and the manufacturing cost can be reduced. In another aspect of the present invention, a refresh address change circuit has a first multiplexer and a second multiplexer. The first multiplexer selects the most significant bit flip-flop during the partial refresh mode, selects the refresh request during the non-partial refresh mode, and outputs the selected bit to the least significant flip-flop. The second multiplexer selects a refresh request during the partial refresh mode, selects a flip-flop of the second most significant bit during the non-partial refresh mode, and recalls the selected bit. Output to the input of the upper flip-flop. As described above, the refresh operation of the partial area can be distributed by shifting one bit of the output bit of the refresh address count during the partial refresh mode by the simple multiplexer.

In another aspect of the present invention, a refresh address change circuit has a first multiplexer and a second multiplexer. The first multiplexer selects the flip-flop group of the most significant bit during the partial refresh mode, selects the refresh request during the non-partial refresh mode, and outputs the selected bit to the least significant flip-flop. I do. The second multiplexer selects the refresh request during the partial refresh mode, selects the output of the flip-flop of the third most significant bit during the non-partial refresh mode, and places the selected bit in the second most significant bit. Output to the input of the flip-flop. As described above, the refresh operation in the partial area is distributed by shifting the two bits of the output bit of the refresh address power during the partial refresh mode by the simple multiplexer. it can. A day

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing details of the refresh address counter, refresh address change circuit, and refresh control circuit shown in FIG.

FIG. 3 is a circuit diagram showing details of the multiplexer shown in FIG.

FIG. 4 is a block diagram showing details of the memory core shown in FIG.

FIG. 5 is a timing chart showing the operation in the self-refresh mode in the first embodiment.

FIG. 6 is a timing chart showing an operation during the partial refresh mode in the first embodiment.

FIG. 7 is a block diagram showing a second embodiment of the present invention.

FIG. 8 is a circuit diagram showing details of the refresh address counter, refresh address change circuit, and refresh control circuit shown in FIG.

FIG. 9 is a block diagram showing details of the memory core shown in FIG.

FIG. 10 is a timing chart showing an operation during the partial refresh mode in the second embodiment.

FIG. 11 is a block diagram showing a third embodiment of the present invention.

FIG. 12 is a circuit diagram showing details of the refresh address counter, the refresh address change circuit, and the refresh control circuit shown in FIG.

FIG. 13 is a block diagram showing a fourth embodiment of the present invention.

FIG. 14 is a circuit diagram showing details of the refresh address counter, the refresh address change circuit, and the refresh control circuit shown in FIG. The best shape bear to put together

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the figure, the signal lines indicated by bold lines are composed of a plurality of bits. Double circles on the left side of the figure indicate external terminals. Signals with "Z" at the end indicate positive logic. Signals ending with "X" indicate negative logic. FIG. 1 shows a first embodiment of a semiconductor memory and a refresh control method of the semiconductor memory according to the present invention.

This semiconductor memory is formed on a silicon substrate as a clock asynchronous FCRAM (Fast Cycle RAM) using a CMOS process. FCRAM is a pseudo SRAM having a DRAM memory and an SRAM interface. The FCRAM periodically performs a refresh operation inside the chip without receiving a refresh command from the outside, and retains the data written in the memory cells. This FCRAM is used, for example, as a work memory mounted on a mobile phone.

The FGRAM has, as operation modes, a normal operation mode for executing a read operation, a write operation, and a refresh operation, and a low power mode for executing only a refresh operation. The low power mode includes a self refresh mode and a partial refresh mode. Hereinafter, the normal operation mode and the self-refresh mode are also referred to as a non-partial refresh mode. Details of the self-refresh mode and the partial refresh mode will be described later.

The read operation and the write operation are performed in response to a read command and a write command supplied via external terminals. The refresh operation is performed in response to a refresh request generated inside the FCRAM without being recognized by an external system.

FCRAM consists of a command control circuit 10, a mode register 12, a refresh timer 14, a refresh address counter 16, a refresh address change circuit 18, an address input circuit 20, a data input / output circuit 22, It has a core control circuit 24, a refresh control circuit 26, an address switching circuit 28, and a memory core 30. FIG. 1 shows only the main signals necessary for explaining the present invention.

The command control circuit 10 receives a command signal CMD (for example, a chip enable signal / CE, a write enable signal / WE, an output enable signal / 0E) supplied from an external terminal. The command control circuit 10 outputs a read control signal RDZ for performing a read operation, a write control signal WRZ for performing a write operation, and the like in response to the received command signal CMD. The command control circuit 10 sets the mode register 12 when the command signal CMD indicates the low power mode. Activates (high level) the partial refresh mode signal PMDZ according to the specified contents.

The mode register 12 is a register for setting the operation mode of the FCRAM. The mode register 12 is set according to the logic level of the decoder signal supplied to the data terminal DQ when the mode register setting command is supplied via the command terminal CMD. Depending on a predetermined bit in the mode register 12, a normal self-refresh is executed during the low power mode (self-refresh mode) or a partial refresh is executed (partial refresh). Mode) is set.

The refresh timer 14 outputs a refresh request signal RQ at a predetermined cycle. The refresh address counter 16 counts in response to the refresh request signal RQ, and outputs a 5-bit refresh address signal RFA0-4. The refresh address signals RFA0-4 are low address signals for selecting a word line WL described later. The actual number of bits of the refresh address signal RFA output by the refresh address counter 16 is larger than 5 bits. However, here, it is 5 bits to make the explanation easy to understand.

When receiving the low-level partial mode signal PMDZ (normal operation mode or self-refresh mode), the refresh address change circuit 18 outputs the refresh address signal RFA0-4 as the refresh address signal RRA0-4. When receiving the high-level partial mode signal PMDZ (partial refresh mode), the refresh address change circuit 18 outputs the refresh address signal RFA0 as the refresh address signal RRA4 and refreshes the refresh address signals RFA1-4. Output as address signals RRA0-3. That is, during the partial refresh mode, the least significant bit of the refresh address signal is output as the most significant bit of the refresh address signal RRA, and the other output bits of the refresh address signal RFA are shifted one bit lower. It is output as the refresh address signal RRA.

The address input circuit 20 receives the address signal ADD supplied from the address terminal, and uses the received signal as a row address signal RA and a column address signal CA. Output. The row address signal RA is supplied to select a word line WL described later. The column address signal CA is supplied to select a bit line BL (or / BI) described later.

The data input / output circuit 22 outputs read data transferred from the memory core 30 via the common data bus CDB to the external terminal DQ during a read operation. During a write operation, the data input / output circuit 22 receives write data via the external terminal DQ and transfers the received data to the memory core 30 via the common data bus CDB.

The core control circuit 24 outputs a plurality of control signals for controlling the operation of the memory core 30 when receiving any of the read control signal RDZ, the write control signal WRZ, and the refresh start signal RSZ '. The control signal is a signal that determines the activation timing of the gate line WL, a signal that determines the activation timing of the sense amplifier, and a signal that determines the precharge timing (equalize timing) of the complementary bit lines BL and / BL. Etc. The core control circuit 24 has an arbitration circuit that determines which of a read command and a write command (command signal CMD) supplied from the outside and a refresh command (refresh request signal RQ) generated internally has priority. It also has functions. The core control circuit 24 activates (high level) the refresh signal REFZ when executing the refresh operation in response to the refresh command. The refresh control circuit 26 outputs a refresh start signal RSZ in response to the refresh request signal RQ during the normal operation mode or the self-refresh mode. The refresh control circuit 26 outputs the refresh start signal RSZ in response to the refresh request signal only when the refresh address signal RRA4 is at the low level during the partial refresh mode.

When receiving the low-level refresh signal REFZ (normal operation mode), the address switching circuit 28 outputs the row address signal RA as the internal row address signal IRA. When receiving the high-level refresh signal REFZ (partial refresh mode or self-refresh mode), the address switching circuit 28 outputs the refresh address signals RRA0-4 as internal row address signals IRA. That is, in the read operation and the write operation, a row address supplied from the outside is used. The signal RA is selected, and in the refresh operation, the internally generated refresh address signal MA (FRA) is selected.

The memory core 30 has a memory array ARY, a word decoder WDEC, a column decoder CDEC, a sense buffer SB, and a write amplifier WA.

The memory array ARY includes a plurality of volatile memory cells MC (dynamic memory cells) arranged in a matrix, and a plurality of word lines WL and a plurality of bit line pairs BL and / BL connected to the memory cells MC. , And a plurality of sense amplifiers SA connected to the bit line pair BL, / BL.

The memory cell MC is the same as a general DRAM memory cell, and has a capacity for holding data as a charge and a transfer transistor disposed between the capacity and the bit line BL. have. The gate of the transfer transistor is connected to the lead WL.

The sense amplifier SA operates in synchronization with the control signal from the core control circuit 24, and amplifies the amount of data on the bit lines BL and / BL. The data amplified by the sense amplifier SA is transmitted to the data bus DB via a column switch during a read operation, and is written to the memory cell MC via a bit line during a write operation.

The word decoder WDEC selects one of the word lines WL according to the internal row address signal IRA, and changes the selected word line WL to a high level in synchronization with a control signal from the core control circuit 24.

The column decoder CDEC outputs a column line signal for turning on a column switch connecting each of the bit lines BL, / BL and the data bus DB according to the column address signal CAD.

The sense buffer section SB amplifies the signal amount of the read data on the data bus DB during the read operation and outputs the amplified signal to the common data bus CDB. The write amplifier WA amplifies the signal amount of the write data on the common data bus CDB during a write operation and outputs the amplified data to the data bus DB.

FIG. 2 shows details of the refresh address counter 16, the refresh address changing circuit 18 and the refresh control circuit 26 shown in FIG.

The refresh address counter 16 has five flip-flop ports connected in series. It has a FFO-4 (latch circuit). Each flip-flop FF0-4 inverts the logic level of the data held in synchronization with the rising edge of the signal received at the input terminal, and outputs the inverted signal from the output terminal. The first-stage flip-flop FF0 receives a refresh request signal RQ at an input terminal and outputs a refresh address signal RFA0 from an output terminal. The flip-flops FF4 and FF4 receive the outputs of the preceding flip-flops FF0-3 at their input terminals and output the refresh address signals RFA1-4 from their output terminals.

The refresh address change circuit 18 has multiplexers MUX1 corresponding to the refresh address signals RFA0-4, respectively. Each multiplexer MUX1 outputs the signal supplied to the first input terminal A to the output terminal C when receiving the low-level partial mode signal PMDZ at the control terminal ø (normal operation mode or self-refresh mode). I do. Each multiplexer MUX1 outputs the signal supplied to the second input terminal B to the output terminal C when receiving the high-level partial mode signal PMDZ (partial refresh mode).

The multiplexer MUX1 receives the refresh address signals RFA0-4 at the first input terminal A, and outputs the refresh address signals RRA0-4 from the output terminal C, respectively. The multiplexer MUX1, which receives the refresh address signal RFA0-3 at the first input terminal A, receives the refresh address signal RFA1-4 at the second input terminal B. The multiplexer MUX1 receiving the refresh address signal RFA4 at the first input terminal A receives the refresh address signal RFA0 at the second input terminal B.

The refresh control circuit 26 includes a three-input NAND gate that is activated in response to the high-level partial mode signal PMDZ, a two-input NAND gate that is activated in response to the low-level partial mode signal PMDZ, and It has a 2-input NAND gate (negative logic OR gate) that receives the output of the NAND gate and outputs the refresh start signal RSZ.

As described above, when the partial mode signal PMDZ is low (normal operation mode or self-refresh mode), the refresh control circuit 26 outputs the refresh start signal RSZ in response to the refresh request signal RQ, and outputs the partial start signal RSZ. When the mode signal PMDZ is high (partial refresh mode), the refresh のみ Only when the cache address signal RRA4 is low, the refresh start signal RSZ is output in response to the refresh request signal.

FIG. 3 shows details of the multiplexer MUX1 shown in FIG.

The multiplexer MUX1 includes a two-input NAND gate connected to the control terminal ø via the first input terminal A and the input terminal, a two-input NAND gate connected to the second input terminal B and the control terminal ø, and a two-input NAND gate. It has a two-input NAND gate (negative logic OR gate) connected to the output of the NAND gate and the output connected to output terminal C. FIG. 4 shows details of the memory core 30 shown in FIG.

The memory array ARY is divided into four row blocks (memory areas) RBLK0-3. A sense amplifier array SA is arranged between the row blocks RBLK0-3. The sense amplifier array SA is shared by the row blocks RBLK on both sides. That is, this

FCRAM employs a shared sense amplifier system.

The side decoder WDEC has four side decoder rows WD0-3 corresponding to the row blocks RBLK0-3, respectively. In this embodiment, the row block RBLK0-1 selected when the highest internal row address signal IRA4 is logic "0" is allocated as one partial area, and the other row blocks RBLK2-3 are assigned to non-partial areas. Is assigned as an area.

The refresh operation is executed for all row locks RBLK0-3 during the normal operation mode and the self-refresh mode, and is executed only for the partial area during the partial refresh mode. In other words, the refresh operation in the non-partial area is prohibited during the single refresh mode. For this reason, the data held in the memory cells MC of the row blocks RBLK2-3 are lost during the single refresh mode. The data held in the memory cells MC of the row block RBLK0-2 is held without being lost during the partial refresh mode.

FIG. 5 shows the operation during the self-refresh mode in the first embodiment.

The command control circuit 10 shown in FIG. 1 holds the partial mode signal PMDZ at a low level “L” during the self-refresh mode. Refresh evening Ima 1 4 A refresh request signal is output at a fixed cycle. The refresh address changing circuit 18 shown in FIG. 2 outputs the refresh address signals RRA0-4 without replacing the bits of the refresh address signals RFA0-4 while the partial mode signal PMDZ is at a low level. For this reason, the refresh address signal A0-4 sequentially decreases every time the refresh request signal RQ is output.

The block selection signals RBLK0X-RBLK3X are generated by the word decoder WDEC according to the internal row address signals IRA3-4. The block selection signals RBLK0X-RBL X change to low level when the input blocks RBLK0-3 are selected. During the self refresh mode, the refresh address signal RRA3-4 is output as the internal row address signal IRA3-4. One of the row blocks RBLK0-3 selected by the block selection signal HBLK sequentially selects the connection lines WL in accordance with an internal row address signal IRA0-2 not shown. During self-refresh mode, the refresh address signal is output as internal load signal IRA0-2.

As a result, the refresh operation in the self-refresh mode is executed at equal intervals in the order of the row blocks RBLK3-0. The interval of the refresh operation is equal to the interval of generation of the refresh request signal RQ. For this reason, the current consumption regularly increases every time the refresh operation is executed. Note that, in the normal operation mode, the timing is almost the same as that shown in FIG. 5 except that the read operation or the write operation is performed between the refresh operations. When a read operation or a write operation and a refresh operation conflict with each other, the priority is determined by the core control circuit 24 shown in FIG.

FIG. 6 shows an operation during the partial refresh mode in the first embodiment. The description of the same operation as in FIG. 5 is omitted.

The partial mode signal PMDZ is held at a high level "H" during the partial refresh mode. The refresh timer 14 shown in FIG. 1 outputs the refresh request signal RQ at a predetermined cycle, as in FIG. 5 described above.

The refresh address change circuit 18 shown in FIG. 2 outputs the refresh address signal RFA0 as the refresh address signal RRA4 while the partial mode signal PMDZ is at the high level, and refreshes the refresh address signals RFA1-4. Output as dress signal RRAO-3. That is, during one refresh mode, the bit of the refresh address signal RFA0-4 output from the refresh address counter 16 is replaced by the refresh address change circuit 18. Therefore, the logic level of the highest-order refresh address signal RRA4 is inverted every time the refresh request signal RQ is output. The address value indicated by the remaining refresh address RRA0-3 sequentially decreases each time the refresh address signal RRA4 changes from a low level (logic "0") to a high level (logic "1").

The refresh control circuit 24 shown in FIG. 2 outputs the refresh start signal RSZ in response to the refresh request signal RQ only when the refresh address signal RRA4 is at a low level during the partial refresh mode. . Therefore, the refresh operation in the partial refresh mode is executed only in the row lock RBLK0-1 (partial area). The refresh operation of row program RBLK2-3 is not executed during the partial refresh mode.

Also, since the lowest refresh address signal RRA0 is output as the refresh address signal RRA, the refresh start signal RSZ is output once every time the refresh request signal RQ is output twice. That is, the refresh operation in the partial refresh mode is executed at equal intervals at twice the period of the non-partial refresh mode. In other words, the refresh frequency in the partial refresh mode is set to (number of partial areas "2") / (number of memory areas "4"). Since the frequency of the refresh operation is reduced, the power consumption in the partial refresh mode is reduced as compared with that in the self refresh mode.

The current consumption during the partial refresh mode increases regularly every time a refresh operation is performed. Therefore, the current consumption in the partial refresh mode can be measured in a period in which the refresh request signal RQ occurs several times.

As described above, in the first embodiment, the refresh request signal is masked when the refresh address signal RRA0-4 indicates the non-partial area during the partial refresh mode. Therefore, a frequency divider for dividing the frequency of the refresh request signal RQ during the partial refresh mode is not required. As a result, the chip size of the FCRAM can be reduced. Also masks the refresh request signal RQ corresponding to the non-partial area By doing so, the frequency of the refresh operation can be minimized. That is, power consumption during the partial refresh mode can be reduced with a simple circuit.

During the partial refresh mode, the refresh operation is not performed by the refresh address signals RRA0-4 that do not indicate the partial area. Therefore, the intervals between refresh operations can be equalized during the partial refresh mode. Since the refresh operation can be dispersed, the current consumption in the partial refresh mode can be measured in a short time. Specifically, current consumption can be accurately measured during the period in which refresh requests occur several times. As a result, test time can be shortened, and manufacturing costs can be reduced.

By converting the lower 1 bit of the output of the refresh address counter 16 into the most significant bit during the partial refresh mode, the selected memory area can be sequentially switched every time the refresh address RRA is updated . Therefore, in the memory array ARY in which half of the entire memory area RBLK is a partial area, the refresh operation can be dispersed during the partial refresh mode. The refresh operation of the partial area can be dispersed by converting the output of the refresh address counter 16 during the partial refresh mode by the refresh address changing circuit 18 having the simple multiplexer MUX1. · By selecting the memory area by the upper bit of the refresh address A and selecting the lead line WL in the selected memory area by the lower bit of the refresh address RRA, a different memory area can be selected during the partial refresh mode. Word lines WL can be selected sequentially, and refresh operations can be distributed.

FIG. 7 shows a second embodiment of the semiconductor memory and the refresh control method of the semiconductor memory according to the present invention. Circuits and signals that are the same as the circuits and signals described in the first embodiment are given the same reference numerals, and detailed descriptions thereof are omitted.

In this embodiment, a refresh address change circuit 32 and a refresh control circuit 34 are formed instead of the refresh address change circuit 18 and the refresh control circuit 26 of the first embodiment. Other configurations are the same as those of the first embodiment. FIG. 8 shows details of the refresh address counter 16, the refresh address change circuit 32, and the refresh control circuit 34 shown in FIG.

The refresh address change circuit 32 has multiplexers MUX1 respectively corresponding to the refresh address signal RF AO-4.

The multiplexer MUX1 receives the refresh address signals RFA0-4 at the first input terminal A, and outputs the refresh address signals RRA0-4 from the output terminal C, respectively. The multiplexer MUX1 which receives the refresh address signal RFA0-2 at the first input terminal A receives the refresh address signal RFA1-3 at the second input terminal B, respectively. The multiplexer MUX1 receiving the refresh address signal RFA3-4 at the first input terminal A receives the refresh address signal RFA0-1 at the second input terminal B, respectively. -..

The refresh control circuit 34 is a 4-input NAND gate that is activated by receiving a high-level partial mode signal PMDZ, and a 2-input NAND gate that is activated by receiving a low-level partial mode signal PMDZ. It has a gate and a two-input NAND gate (negative logic OR gate) that receives the output of both NAND gates and outputs a refresh start signal RSZ. The four-input NAND gate receives the inversion signal of the refresh address signal RRA3-4, the refresh request signal RQ, and the partial mode signal PMDZ. The two-input NAND gate receives a refresh request signal RQ and an inverted signal of the partial mode signal PMDZ.

The refresh control circuit 34 outputs the refresh start signal RSZ in response to the refresh request signal when the single mode signal PMDZ is low (normal operation mode or self-refresh mode), and the partial mode signal PMDZ is high. In some cases (partial refresh mode), the refresh start signal RSZ is output in response to the refresh request signal RQ only when the refresh address signal RRA3-4 is low.

FIG. 9 shows details of the memory core 30 shown in FIG.

The memory core 30 is the same as the first embodiment, but differs in the allocation of the partial area. In this embodiment, the row block RBLK0 selected when the upper two-bit internal row address signal IRA3-4 is logic "0" is The other row blocks RBLK1-3 are allocated as non-partial areas.

FIG. 10 shows the operation during the partial refresh mode in the second embodiment. The description of the same operation as in FIGS. 5 and 6 is omitted.

The refresh address change circuit 32 shown in FIG. 8 outputs the refresh address signal RFA0-1 as the refresh address signal RRA3-4 while the partial mode signal PMDZ is at the high level, and resets the refresh address signal RFA2-4. Output as fresh address signal RRA0-2. For this reason, the address value indicated by the upper two bits of the refresh address signal RRA3-4 sequentially decreases every time the refresh request signal RQ is output. The address value indicated by the remaining refresh address RRA0-2 sequentially decreases each time the refresh address signal RRA4 changes from low and level (logic "0") to high (logic "1").

During the partial refresh mode, the refresh control circuit 34 shown in FIG. 8 generates the refresh start signal RSZ in response to the refresh request signal RQ only when the refresh address signals MA3-4 are both low. Output. Therefore, the refresh operation in the partial refresh mode is executed only in the row lock RBLK0 (partial area). The refresh operation of row blocks RBLK1-3 is not executed during the partial refresh mode.

Also, since the lower two bits of the refresh address signal RFA0-1 are output as the refresh address signal MA3-4, the refresh start signal RSZ is output once every four times the refresh request signal RQ is output. Is done. That is, the refresh operation in the partial refresh mode is executed at regular intervals with a cycle four times as long as that of the non-partial refresh mode shown in FIG. In other words, the refresh frequency during the partial refresh mode is set to (number of partial areas "1") (no number of memory areas "4"). Because the frequency of the refresh operation is reduced, the power consumption during the partial refresh mode is significantly reduced as compared with the self refresh mode.

The current consumption during the partial refresh mode regularly increases every time the refresh operation is performed. Therefore, as in the first embodiment, the The current consumption during the refresh mode can be measured during the period in which the refresh request signal is generated several times.

In this embodiment, the same effects as in the first embodiment can be obtained. By the way, in this embodiment, the lower two bits of the refresh address signal are converted into the upper two bits during the partial refresh mode, so that a quarter of the entire memory area RBLK is a partial area in the memory array ARY. The refresh operation can be dispersed in the partial refresh mode.

FIG. 11 shows a third embodiment of the semiconductor memory and the semiconductor memory refresh control method according to the present invention. Circuits that are the same as the circuits and signals described in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

In this embodiment, a refresh address counter 36 and a refresh address change circuit 38 are formed in place of the refresh address counter 16 and the refresh address change circuit 18 of the first embodiment. . Other configurations are the same as those of the first embodiment.

FIG. 12 shows details of the refresh address counter 36, the refresh address change circuit 38, and the refresh control circuit 26 shown in FIG. The refresh address change circuit 38 has a first multiplexer MUX21 and a second multiplexer MUX22. The multiplexer MUX222 has one end and the other end connected to the second input terminal B and the output terminal C, respectively, and a CMOS switch that is turned on when the partial mode signal PMDZ received at the control terminal ø is at a high level, and one end and the other end. And a CMOS switch that is connected to the first input terminal A and the output terminal C, respectively, and that is turned on when the partial mode signal PMDZ received at the control terminal is at a low level.

The multiplexer MUX21 receives the refresh address signal RRA4 at the input terminal B, receives the refresh request signal RQ at the first input terminal A, and connects the output terminal C to the input of the flip-flop FF0 of the refresh address counter 36. The multiplexer MUX22 receives the refresh request signal RQ at the second input terminal B, receives the refresh address signal RRA3 at the first input terminal A, and outputs the refresh terminal C to the refresh address. It is connected to the input of flip-flop FF4 of counter 36.

The refresh address counter 36 has five flip-flops 0-4 (latch circuits) connected in series similarly to the first embodiment. The difference from the refresh address counter 16 of the first embodiment is that the input of the flip-flop FF0, the output of the flip-flop FF3, and the input of the flip-flop FF4 are different from the refresh address change circuit 3. 8 is connected.

The refresh address changing circuit 18 has multiplexers MUX1 corresponding to the refresh address signals RFA0-4, respectively. When the multiplexer MUX1 receives the low-level partial mode signal PMDZ at the control terminal ø (normal operation mode or self-refresh mode), it outputs the signal supplied to the first input terminal A to the output terminal C. Each multiplexer MUX1 outputs a signal to be supplied to the second input terminal B to the output terminal C when receiving the 髙 level partial mode signal PMDZ (partial refresh mode).

In this embodiment, when the partial mode signal PMDZ is at a low level (non-partial refresh mode), the refresh request signal is supplied to the input of the flip-flop FF0, and the refresh address signal RRA3 is supplied to the input of the flip-flop FF4. You. Therefore, the connection order of the flip-flops is FF0-01-ΪΤ2-FF3-FF4. When the partial mode signal PMDZ is at a high level (partial refresh mode), the refresh address signal RRA4 is supplied to the input of the flip-flop FF0, and the refresh request signal RQ is supplied to the input of the flip-flop FF4. You. Therefore, the connection order of flip-flops is FF4-FF0-FF to FF2-FF3. Therefore, the refresh address signals RRA0-4 generated in the non-partial refresh mode and the partial refresh mode are the same as those in the first embodiment.

In this embodiment, the same effects as in the first embodiment can be obtained.

FIG. 13 shows a fourth embodiment of the semiconductor memory and the refresh control method of the semiconductor memory according to the present invention. Circuits Same as Circuits and Signals described in First to Third Embodiments Signals are given the same reference numerals, and these are described in detail. The description is omitted.

In this embodiment, a refresh address counter 40 and a refresh control circuit 34 are formed instead of the refresh address counter 36 and the refresh control circuit 26 of the third embodiment. The refresh control circuit 34 is the same circuit as in the second embodiment. Other configurations are the same as those of the first embodiment.o

FIG. 14 shows details of the refresh address counter 40, the refresh address change circuit 38, and the refresh control circuit 34 shown in FIG. In this embodiment, the output (refresh address signal RRA2) of the flip-flop FF2 of the refresh address counter 40 is connected to the first input terminal A of the multiplexer MUX22, and the input of the flip-flop FF3 is connected to the output terminal of the multiplexer MUX22. Connected to C.

When the partial mode signal PMDZ is low (non-partial refresh mode), the refresh request signal RQ is supplied to the input of the flip-flop FF0, and the refresh address signal RRA2 is supplied to the input of the flip-flop FF3. You. Therefore, the connection order of the flip-flops is FF0-FF FF2-FF3-FF4. When the partial mode signal PMDZ is at a high level (partial refresh mode), the refresh address signal RRA4 is supplied to the input of the flip-flop FF0, and the refresh request signal RQ is supplied to the input of the flip-flop FF3. Supplied. Therefore, the connection order of the flip-flops is FF3-FF4-FF0-FF1-FF2. Therefore, the refresh address signals A0-4 generated in the non-partial refresh mode and the partial refresh mode are the same as those in the second embodiment.

In this embodiment, the same effects as those of the first and second embodiments can be obtained.

In the above-described embodiment, the example in which the present invention is applied to the FCRAM has been described. The present invention is not limited to such an embodiment. For example, the present invention may be applied to a DRAM or a pseudo SRAM having a partial refresh mode.

In the first embodiment described above, half of the four memory areas are set as partial areas. In the described FCRAM, an example was described in which the lower one bit of the refresh address was converted to the most significant bit during the partial refresh mode. In the above-described second embodiment, in the FCRAM in which one quarter of the four memory areas are set to the partial area, the lower two bits of the refresh address are assigned to the upper two bits during the partial refresh mode. An example of conversion to bits has been described. The present invention is not limited to such an embodiment. In general, when 1 / a of the entire memory area is set in the partial area, the number of lower bits to be converted into upper bits is set to "b" that satisfies "a = 2 to the power of b". Good. In this case, the refresh operation can be distributed during the partial refresh mode.

As described above, the present invention has been described in detail. However, the above-described embodiment and its modifications are merely examples of the present invention, and the present invention is not limited thereto. Obviously, the present invention can be modified without departing from the scope of the present invention. Πτ ability 'I' cow of the use of 麵

In the semiconductor memory of the present invention, a frequency divider that operates during the partial refresh mode to divide the refresh request (pulse) can be dispensed with. As a result, the chip size of the semiconductor memory can be reduced. Also, by masking the refresh request corresponding to the non-partial area, the frequency of the refresh operation can be minimized. That is, the power consumption during the partial refresh mode can be reduced with a simple circuit.

During the partial refresh mode, the intervals between refresh operations can be equalized. Since the refresh operation can be dispersed, the current consumption during the partial refresh mode can be measured in a short time. Specifically, current consumption can be accurately measured in a period in which refresh requests occur several times. As a result, the test time can be reduced, and the manufacturing cost can be reduced.

In the semiconductor memory of the present invention, the refresh operation of the partial area can be distributed by shifting one bit of the output bit of the refresh address count during the partial refresh mode by the simple multiplexer.

In the semiconductor memory of the present invention, partial refresh is performed by a simple multiplexer. By shifting the two bits of the output bit of the refresh address counter during the hash mode, the refresh operation in the partial area can be dispersed.

In the semiconductor memory of the present invention, during the partial refresh mode, the refresh operation is not performed by sequentially selecting the adjacent memory cells in the same memory area, but the memory cells in different memory areas are sequentially selected. By doing so, the refresh operation can be distributed.

Claims

The scope of the claims

(1) a memory array having dynamic memory cells and having a plurality of memory areas partitioned by upper bits of an address;

The memory device includes at least one of the memory areas, and is used for holding data held in the memory cells during a partial refresh mode and a non-partial refresh mode, which are one of the low power modes. A partial area where the refresh operation is performed, and

A non-partial area configured by the remaining memory area, wherein a refresh operation is performed during the non-partial refresh mode, and a refresh operation is prohibited during the partial refresh mode;

A refresh timer for generating a refresh request for refreshing a memory cell at a predetermined cycle;

A refresh address counter for sequentially generating a refresh address consisting of a plurality of bits indicating a memory cell to be refreshed in response to the refresh request;

During the partial refresh mode, the lower bit of the output of the refresh address count is output to the memory array as an upper bit, and the remaining bits are sequentially shifted to the lower bit side. A refresh address change circuit that outputs the refresh address to the memory array;

During the partial refresh mode, a refresh start signal is generated in response to the refresh request only when the refresh address indicates the non-active area, and during the non-partial refresh mode, the refresh request signal is generated. A refresh control circuit for generating the refresh start signal in response to the refresh signal.

(2) In the semiconductor memory of Claim 1,

The refresh address changing circuit includes a plurality of multiplexers for selecting a first input during the non-partial refresh mode and selecting a second input during the partial refresh mode, The first input is connected to an output bit of the refresh address counter,

The second input of the multiplexer corresponding to the most significant bit of the refresh address count is connected to the least significant bit of the output bit of the refresh address count,

The semiconductor memory according to claim 1, wherein a second input of the remaining multiplexer is connected to a bit one level higher than a corresponding output bit in the refresh address counter.

(3) In the semiconductor memory of Claim 1,

The refresh address changing circuit includes a plurality of multiplexers for selecting a first input during the non-partial refresh mode and selecting a second input during the partial refresh mode,

The first input is connected to an output bit of the refresh address counter, respectively.

The second input of the multiplexer corresponding to the second highest bit of the refresh address count is connected to the least significant bit of the output bit of the refresh address count,

The second input of the multiplexer corresponding to the most significant bit of the refresh address count is connected to the second least significant bit of the output bit of the refresh address count,

(4) In the semiconductor memory of Claim 1,

The refresh frequency during the partial refresh mode is set to nZm, the refresh frequency during the non-partial refresh mode, where m is the number of memory areas and n is the number of partial areas. Semiconductor memory characterized by the above-mentioned.

(5) In the semiconductor memory of claim 1, Each of the memory regions includes a plurality of lead lines connected to the memory cells, respectively.

One of the memory areas is selected by an upper bit of the refresh address.

A semiconductor memory, wherein one of the word lines in a selected memory area is selected by the remaining bits of the refresh address. .

(6) A memory array having a plurality of memory areas each having a dynamic memory cell and partitioned by upper bits of an address;

Holds data held in the memory cell during partial refresh mode and non-partial refresh mode, which are configured by at least one of the memory areas and are one of low power modes. A partial area where a refresh operation is performed to perform

A non-partial area composed of the remaining memory areas, wherein a refresh operation is performed during the non-partial refresh mode, and a refresh operation is prohibited during the partial refresh mode;

A refresh timer for generating a refresh request of a memory cell at a predetermined cycle; and a plurality of flip-flops connected in series to output a refresh address composed of a plurality of bits indicating the memory cell to be refreshed. A refresh address counter for sequentially generating the refresh address in response to a request;

A refresh address changing circuit for connecting an output of a highest-order flip-flop to one of inputs of a lowest-order flip-flop during the partial refresh mode, and supplying the refresh request to an input of a higher-order flip-flop; And generating a refresh start signal in response to the refresh request only when the refresh address indicates the partial area during the partial refresh mode, and during the non-partial refresh mode, And a refresh control circuit for generating a refresh start signal in response.

(7) In the semiconductor memory according to claim 6, The refresh address change circuit,

A first flip-flop for selecting the most significant bit flip-flop during the partial refresh mode, selecting the refresh request during the non-partial refresh mode, and outputting the selected bit to the least significant flip-flop; A multiplexer for selecting the refresh request during the partial refresh mode, selecting a flip-flop of the second highest bit during the non-partial refresh mode, and selecting the selected bit as a most significant flip-flop. A semiconductor memory, comprising: a second multiplexer that outputs a signal to an input of a memory card.

(8) In the semiconductor memory of claim 6,

The refresh address change circuit,

Selecting the flip-flop of the most significant bit during the partial refresh mode, selecting the refresh request during the non-partial refresh mode, and outputting the selected bit to the least significant flip-flop A first multiplexer, selecting the refresh request during the partial refresh mode, selecting the flip-flop output of the third most significant bit during the non-partial refresh mode, and selecting the selected bit from the second most significant bit; And a second multiplexer for outputting an input to an input of the flip-flop.

(9) In the semiconductor memory according to claim 6,

The refresh frequency during the partial refresh mode is set to nZm, the refresh frequency during the non-partial refresh mode, where m is the number of memory areas and n is the number of partial areas. Semiconductor memory characterized in that:

(10) In the semiconductor memory according to claim 6,

Each of the memory areas includes a plurality of read lines connected to the memory cells, and one of the memory areas is selected by an upper bit of the refresh address,

The semiconductor memory according to claim 1, wherein any one of the pad lines in the selected memory area is selected by the remaining bits of the refresh address.

(11) It has dynamic memory cells and is partitioned by the upper bits of the address. A memory array having a plurality of memory areas, wherein the memory array is configured by at least one of the memory areas, and the memory array is provided during a partial refresh mode and a non-partial refresh mode which are one of low power modes. A partial area in which a refresh operation for holding data held in a cell is executed, and a remaining memory area, wherein a refresh operation is executed during the non-partial refresh mode, and the partial refresh mode is executed. A refresh control method for a semiconductor memory including a non-partial area in which a refresh operation is prohibited during a read operation.

A refresh request for refreshing a memory cell is generated at a predetermined cycle, and a refresh address consisting of a plurality of bits indicating a memory cell to be refreshed in response to the refresh request is sequentially generated.

During the partial refresh mode, a lower bit of the refresh address is output to the memory array as an upper bit, and the remaining bits of the refresh address are sequentially shifted to lower bits and output to the memory array. Performing a refresh operation of the partial area only when a refresh address output to the memory array indicates the partial area during the partial refresh mode;

A refresh control method for a semiconductor memory, wherein the refresh operation of the partial area and the non-partial area is sequentially performed in response to the refresh request during the non-partial refresh mode. ·

(12) The refresh control method for a semiconductor memory according to claim 11, wherein the refresh frequency in the partial refresh mode is such that the number of the memory areas is m, the number of the partial areas is n, and the non-partial A refresh control method for a semiconductor memory, wherein the refresh frequency is set to n / m of a refresh frequency in a refresh mode.

(13) A memory array having dynamic memory cells and having a plurality of memory areas partitioned by upper bits of an address, and a refresh address counter having a plurality of flip-flop openings connected in series. Wherein the memory array comprises at least one of the memory areas and is in one of low-power modes. The memory device includes a partial area in which a refresh operation for holding data held in the memory cell is performed during the partial refresh mode and the non-partial refresh mode, and the remaining memory area. A refresh operation of the semiconductor memory, wherein the refresh operation is performed during the non-partial refresh mode, and a non-partial region in which the refresh operation is prohibited during the partial refresh mode;

A refresh request for refreshing a memory cell is generated at a predetermined cycle, and a refresh address including a plurality of bits indicating a memory cell to be refreshed in response to the refresh request is sequentially generated during the non-partial refresh mode;

During the partial refresh mode, the output of the highest flip-flop of the refresh address counter is connected to the input of the lowest flip-flop, and the refresh request is transmitted to the upper flip-flop. To generate the refresh address by feeding it to one of the inputs of the

During the partial refresh mode, a refresh operation of the partial area is performed only when a refresh address output to the memory array indicates the partial area;

A refresh control method for a semiconductor memory, characterized in that during the non-partial refresh mode, the refresh operation of the partial area and the non-partial area is sequentially performed in response to the refresh request.

(14) In the refresh control method for a semiconductor memory according to claim 13, the refresh frequency in the partial refresh mode is such that the number of the memory areas is m and the number of the partial areas is n. A refresh control method for a semiconductor memory, wherein the refresh frequency is set to n / m of a refresh frequency during the non-partial refresh mode.