WO2004066167A3 - Verfahren zum bereitstellen und optimieren eines virtuellen prototypen und anordnung - Google Patents

Verfahren zum bereitstellen und optimieren eines virtuellen prototypen und anordnung Download PDF

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Publication number
WO2004066167A3
WO2004066167A3 PCT/EP2004/000582 EP2004000582W WO2004066167A3 WO 2004066167 A3 WO2004066167 A3 WO 2004066167A3 EP 2004000582 W EP2004000582 W EP 2004000582W WO 2004066167 A3 WO2004066167 A3 WO 2004066167A3
Authority
WO
WIPO (PCT)
Prior art keywords
optimizing
supplying
arrangement
virtual prototype
integrated circuit
Prior art date
Application number
PCT/EP2004/000582
Other languages
English (en)
French (fr)
Other versions
WO2004066167A2 (de
WO2004066167B1 (de
Inventor
Carsten Mielenz
Thomas Zettler
Original Assignee
Infineon Technologies Ag
Carsten Mielenz
Thomas Zettler
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Carsten Mielenz, Thomas Zettler filed Critical Infineon Technologies Ag
Publication of WO2004066167A2 publication Critical patent/WO2004066167A2/de
Publication of WO2004066167A3 publication Critical patent/WO2004066167A3/de
Publication of WO2004066167B1 publication Critical patent/WO2004066167B1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/333—Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2117/00—Details relating to the type or aim of the circuit design
    • G06F2117/08—HW-SW co-design, e.g. HW-SW partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation

Abstract

Die Erfindung betrifft ein Verfahren zum Bereitstellen und Optimieren eines virtuellen Prototyps, insbesondere für eine integrierte Schaltung oder ein System, wobei die integrierte Schaltung bzw. das System und/oder eine dafür vorgesehene Applikations-Software in eine Vielzahl von Transaktionen unterteilt ist und eine Transaktion jeweils einen ihr zugeordnenten Teil der integrierten Schaltung bzw. des Systems oder ein Software-Element charakterisiert, bei dem einer Transaktion jeweils ein Wichtungselement zugeordnet wird, welches die Leistungsaufnahme des entsprechenden Teils bzw. des Software-Elements darstellt, und dass eine Leistungsberechnung vorgenommen wird.
PCT/EP2004/000582 2003-01-24 2004-01-23 Verfahren zum bereitstellen und optimieren eines virtuellen prototypen und anordnung WO2004066167A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10302795.5 2003-01-24
DE10302795A DE10302795B4 (de) 2003-01-24 2003-01-24 Verfahren zum Bereitstellen und Optimieren eines virtuellen Prototypen und Anordnung

Publications (3)

Publication Number Publication Date
WO2004066167A2 WO2004066167A2 (de) 2004-08-05
WO2004066167A3 true WO2004066167A3 (de) 2005-01-06
WO2004066167B1 WO2004066167B1 (de) 2005-03-10

Family

ID=32694953

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2004/000582 WO2004066167A2 (de) 2003-01-24 2004-01-23 Verfahren zum bereitstellen und optimieren eines virtuellen prototypen und anordnung

Country Status (2)

Country Link
DE (1) DE10302795B4 (de)
WO (1) WO2004066167A2 (de)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0875833A1 (de) * 1997-05-02 1998-11-04 Texas Instruments Incorporated Modular configurierbarer, auf einen ganzen Chip anwendbarer Leistungsprofilgenerator
US6205555B1 (en) * 1998-02-16 2001-03-20 Kabushiki Kaisha Toshiba Processor power consumption estimating system, processor power consumption estimating method, and storage medium storing program for executing the processor power consumption estimating method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0875833A1 (de) * 1997-05-02 1998-11-04 Texas Instruments Incorporated Modular configurierbarer, auf einen ganzen Chip anwendbarer Leistungsprofilgenerator
US6205555B1 (en) * 1998-02-16 2001-03-20 Kabushiki Kaisha Toshiba Processor power consumption estimating system, processor power consumption estimating method, and storage medium storing program for executing the processor power consumption estimating method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
TIEN-CHIEN LEE M ET AL: "POWER ANALYSIS AND MINIMIZATION TECHNIQUES FOR EMBEDDED DSP SOFTWARE", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE INC. NEW YORK, US, vol. 5, no. 1, 1 March 1997 (1997-03-01), pages 123 - 135, XP000679029, ISSN: 1063-8210 *

Also Published As

Publication number Publication date
WO2004066167A2 (de) 2004-08-05
WO2004066167B1 (de) 2005-03-10
DE10302795B4 (de) 2006-03-09
DE10302795A1 (de) 2004-08-12

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