WO2004064464A3 - System and method for packaging electronic components - Google Patents

System and method for packaging electronic components Download PDF

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Publication number
WO2004064464A3
WO2004064464A3 PCT/US2004/000181 US2004000181W WO2004064464A3 WO 2004064464 A3 WO2004064464 A3 WO 2004064464A3 US 2004000181 W US2004000181 W US 2004000181W WO 2004064464 A3 WO2004064464 A3 WO 2004064464A3
Authority
WO
WIPO (PCT)
Prior art keywords
capacitor
electronic components
packaging electronic
substrate
package
Prior art date
Application number
PCT/US2004/000181
Other languages
French (fr)
Other versions
WO2004064464A2 (en
Inventor
Joan K Vrtis
Original Assignee
Joan K Vrtis
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/752,045 external-priority patent/US20040160753A1/en
Application filed by Joan K Vrtis filed Critical Joan K Vrtis
Publication of WO2004064464A2 publication Critical patent/WO2004064464A2/en
Publication of WO2004064464A3 publication Critical patent/WO2004064464A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/01039—Yttrium [Y]
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    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
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    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
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    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
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    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
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    • H01L2924/30107—Inductance

Abstract

A capacitor design, which incorporates a material set that is adaptable to standard substrate or electronic packaging fabrication methods, uses copper as a base and electrode, mesoporous nanocomposite materials or other adhesion promoting materials combined with a high dielectric material specific to the application's capacitance requirements. This capacitor is then used as a basis for forming a capacitor in substrate or package or wafer level package or die or wafer.
PCT/US2004/000181 2003-01-10 2004-01-06 System and method for packaging electronic components WO2004064464A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US43917503P 2003-01-10 2003-01-10
US60/439,175 2003-01-10
US10/752,045 US20040160753A1 (en) 2003-01-10 2004-01-05 System and method for packaging electronic components
US10/752,045 2004-01-05

Publications (2)

Publication Number Publication Date
WO2004064464A2 WO2004064464A2 (en) 2004-07-29
WO2004064464A3 true WO2004064464A3 (en) 2004-12-02

Family

ID=32718056

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/000181 WO2004064464A2 (en) 2003-01-10 2004-01-06 System and method for packaging electronic components

Country Status (1)

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WO (1) WO2004064464A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7727808B2 (en) 2008-06-13 2010-06-01 General Electric Company Ultra thin die electronic package

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6703697B2 (en) * 2001-12-07 2004-03-09 Intel Corporation Electronic package design with improved power delivery performance
US6710444B2 (en) * 2002-03-21 2004-03-23 Intel Corporation Molded substrate stiffener with embedded capacitors
US6713860B2 (en) * 2002-02-01 2004-03-30 Intel Corporation Electronic assembly and system with vertically connected capacitors

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6703697B2 (en) * 2001-12-07 2004-03-09 Intel Corporation Electronic package design with improved power delivery performance
US6713860B2 (en) * 2002-02-01 2004-03-30 Intel Corporation Electronic assembly and system with vertically connected capacitors
US6710444B2 (en) * 2002-03-21 2004-03-23 Intel Corporation Molded substrate stiffener with embedded capacitors

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Publication number Publication date
WO2004064464A2 (en) 2004-07-29

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