WO2004059487A1 - Dispositif et procede de calcul en parallele d'un syndrome de code d'erreur - Google Patents

Dispositif et procede de calcul en parallele d'un syndrome de code d'erreur Download PDF

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Publication number
WO2004059487A1
WO2004059487A1 PCT/IL2002/001054 IL0201054W WO2004059487A1 WO 2004059487 A1 WO2004059487 A1 WO 2004059487A1 IL 0201054 W IL0201054 W IL 0201054W WO 2004059487 A1 WO2004059487 A1 WO 2004059487A1
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WIPO (PCT)
Prior art keywords
reminder
syndrome
calculator
register
input
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PCT/IL2002/001054
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English (en)
Inventor
Idan Alrod
Danny Lahav
Aryeh Lezerovitz
Simon Litsyn
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Optix Networks, Ltd.
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Publication date
Application filed by Optix Networks, Ltd. filed Critical Optix Networks, Ltd.
Priority to PCT/IL2002/001054 priority Critical patent/WO2004059487A1/fr
Priority to AU2002360207A priority patent/AU2002360207A1/en
Publication of WO2004059487A1 publication Critical patent/WO2004059487A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1575—Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/159—Remainder calculation, e.g. for encoding and syndrome calculation
    • H03M13/1595—Parallel or block-wise remainder calculation

Definitions

  • the present invention relates generally to a syndrome computing apparatus used for the purpose of error detection and correction, and more particularly for the purpose of error detection and correction of data coded in accordance with a Bose-Chaudhuri- Hocquenghem (BCH) code.
  • BCH Bose-Chaudhuri- Hocquenghem
  • a well-known member of the large family of such codes is the BCH encoding and decoding technique.
  • a BCH code can be used for correction of scattering of single error bits within an input data word.
  • the BCH code is used in satellite communication links, optical networks, etc., where error correction codes are often employed to mitigate the effects of noise interference.
  • An error correction procedure is described herein for a BCH code that corrects up to 't' bit errors, where 't' is a predetermined number.
  • a selection of a large 't' leads to increased length of the redundancy bits in a codeword and therefore to a more complex decoding process.
  • a typical BCH decoder accomplishes the following steps:
  • step (b) a Berlekamp algorithm (US Patent Nos. 4,162,480 and 4,410,989) is well known in the art.
  • step (c) a search algorithm proposed by Chien, as disclosed in
  • c(x) is a codeword if and only if a Jo+] , ⁇ ⁇ +i , a +s , ..., a h * 2 ' ⁇ are roots of c(x).
  • ⁇ is a primitive element of a Galois field of power 2 m (GF(2 m )), and where 'm' is the length of the syndrome coefficient (S j ).
  • the maximal length of c(x), including the redundancy bits, is (2 m -l) bits.
  • the value jo is a positive integer between 0 and 2 m -2.
  • a Galois field is an algebraic field having a finite number of elements. The number of elements is always of the form p m , where p' is a prime number and 'm' is a positive integer. A detailed description of the Galois field may be found in "Error Correcting Codes" by W. Wesley Peterson and E. J. Weldon, Jr., MIT 1972, pages 155-160.
  • Sy is an element in GF(2 ) and includes 'm' bits.
  • S j th syndrome coefficient
  • b is the received bit
  • a"' is also an element in GF(2 m ).
  • the number N is equal to the number of received bits, i.e., the length of an input word b(x).
  • jo is chosen to have the zero. Such selection ensures that only 't' syndrome coefficients are required to be calculated.
  • the received word is described as a polynomial b(x) such that its binary coefficients are the bits in the received word, and the power of 'x' represents the location of the coefficient in the received word.
  • Circuit 100 includes ' elements 110-0 through 110-t-l, where element 110-j calculates S j , for j starting at zero and ending at t-1.
  • Element 110 is a serial implementation of equation (2).
  • Element 110-j includes a single XOR gate 112-j, a register 114-j, and a multiplier 116-j.
  • element 110 The functionality of element 110 is accomplished through the following steps: a) receiving the current input bit bj of an input word in an XOR gate 112, the first received bit being b -i ; b) obtaining the data stored in registers 114 and multiplying it by the constant a"' using multipliers 116; c) adding the multiplication results to the current received bit using XOR gate 112; d) saving the results in registers 114; and, e) repeating steps a) through d) until the entire word is received (i.e., N times).
  • Each syndrome is computed using a different power of " ⁇ ", namely element 110-j includes the value a ' .
  • circuit 100 Although the implementation of circuit 100 is simple, it is not suitable for parallel data input, and especially not suitable for long input codewords that need to be processed at a high rate. Furthermore, the use of a serial circuit is not suitable for optical networks where data is transmitted and received at a high rate. Therefore, parallel processing is required. In view of the fact that prior art syndrome calculators are not compliant with processing parallel data, it would be advantageous to provide a high rate syndrome calculator that overcomes these limitations.
  • the present invention is of an apparatus and method for parallel calculation of the syndrome of an error correcting code, in particular a Bose-Chaudhuri-Hocquenghem code.
  • the apparatus includes a plurality of syndrome calculators capable of calculating concurrently a plurality of syndrome coefficients.
  • the essence of the method lies in replacing the prior art solution for the syndrome exemplified in equation (1) with a polynomial division.
  • a syndrome circuit comprising a plurality of calculators operative to calculate concurrently a plurality of different syndrome coefficients (Sj), each coefficient having a coefficient length 'm' bits, each calculator including: a reminder computation logic (RCL) coupled to an input channel and operative to receive, per cycle, an input block of 'p' bits belonging to an input word polynomial b(x) and operative to compute a remainder; a register coupled to the RCL and operative to store the computed reminder; and an evaluator coupled to the RCL and to an output channel, the evaluator operative to evaluate contents of the reminder, whereby the syndrome circuit is capable of parallel calculation of the syndrome of an error correction code.
  • RCL reminder computation logic
  • a calculator capable of calculation of the syndrome coefficient of error correction codes, comprising: a reminder computation logic (RCL) coupled to an input channel and operative to receive, per cycle, an input block of 'p' bits belonging to an input word polynomial b(x), and operative to compute a remainder; a register coupled to the RCL and operative to store the computed reminder; and an evaluator coupled to the RCL and to an output channel, the evaluator operative to evaluate contents of the reminder, whereby the calculator is capable of parallel calculation of the syndrome of an error correction code.
  • RCL reminder computation logic
  • a method for parallel calculation of syndrome coefficients S j comprising the steps of: receiving an input word polynomial b(x) comprising a plurality of data blocks of 'p' bits, each data block fed into a plurality of calculators; for each data block iteratively computing a temporary reminder; upon reception of the complete input word, substituting the value of an elementa l of a Galois field "GF(2 m )" in the temporary reminder; and outputting the syndrome coefficient S j .
  • Figure 1 - is a schematic diagram of a prior art circuit uses for calculating the syndrome
  • Figure 2 - a schematic block diagram of a syndrome circuit in accordance with one embodiment of this invention
  • Figure 3 - is a schematic block diagram of a calculator used for the calculation of Sj in accordance with one embodiment of this invention.
  • Figure 4 - is an exemplary flowchait describing the method for calculating the syndrome in accordance with one embodiment of this invention
  • FIG. 5 - a non-limiting example of RCL circuit used in this invention
  • Figure 6 an exemplary block diagram of a syndrome circuit and RCL used in this invention:
  • the present invention discloses an apparatus and method enabling fast parallel processing of syndrome coefficients, specifically of a BCH code, which is superior to syndrome calculation solutions described in prior art.
  • the essence of the method lies in replacing the prior art solution for the syndrome exemplified in equation (1) with a polynomial division.
  • Circuit 200 is a high-speed integrated circuit (IC), which is capable of operating at speeds of 10 Gigabits per second (GBPS) and beyond. Specifically circuit 200 is designed to operate at a speed of 40GBPS. Circuit 200 is designed to perform parallel calculation of the syndrome as derived from the received input word. Circuit 200 produces ' syndrome coefficients after receiving the entire input word.
  • IC integrated circuit
  • GBPS Gigabits per second
  • circuit 200 In order to understand the operation of circuit 200, a brief explanation of the underlying mathematics of circuit 200 is helpful.
  • a syndrome coefficient S j in a BCH code is calculated using equations (2) and (3).
  • the input polynomial b(x) is divided by the minimal polynomial of a"' (hereinafter "M j (x)").
  • M j (x) is now represented as follows:
  • b(x) M j (x)*q(x) + r(x) (4)
  • the polynomial q(x) is the resultant quotient
  • the polynomial r(x) is the reminder of the division of b(x) by M j (x).
  • circuit 200 processes 'p' bits in parallel in each cycle.
  • Circuit 200 is comprised of 't' syndrome calculators marked 210-0 through 210-t-l, each having the same functionally.
  • the number of syndrome coefficient calculators 210 is equal to the number of correctable bit errors by a BCH decoder within a word of 'N' bits. A detailed description of a calculator 210 is provided in Fig. 3 below.
  • Circuit 200 receives in each cycle an input block of 'p' bits, which are fed into calculators 210-0 through 210-t-l. After reception of the entire word (i.e., 'N' bits) by circuit 200, each calculator 210 outputs its corresponding syndrome coefficient.
  • FIG. 3 shows an exemplary block diagram of a calculator 210 used for the calculation of S j , in accordance with one embodiment of this invention.
  • Calculator 210 includes a reminder computation logic (RCL) 320, a register 330, and an evaluator 340.
  • RCL 320 computes the remainder r ⁇ (x) that results from dividing the input polynomial b(x) by the polynomial M j (x).
  • the polynomial M j (x) is correlated to the term a ' used to calculate S j .
  • RCL 320 performs the polynomial division using a quotient prediction mechanism.
  • Evaluator 340 includes a combinational logic of AND gates and
  • Fig. 4 shows an exemplary flowchart 400 describing the method for calculating a syndrome coefficient S j , in accordance with one embodiment of this invention. This method shows the steps of the syndrome calculation performed by a single calculator 210. At step 410, an index "i" and the content of the register 330 are both set to zero.
  • the index "i” counts the number of received bits, and since 'p' bits are received in each cycle, each cycle index "i " is increased by 'p'. Obviously, 'p' is a positive integer.
  • syndrome calculator 210 receives the current input block, i.e., 'p' input bits to process.
  • the temporary reminder r ⁇ (x) is calculated by means of RCL 320. The result of step 430 is saved in register 330.
  • the index "i" is increased by 'p'.
  • a check is performed to determine whether the index "i" is above or equal to 'N', where 'N' is the length of the received input word.
  • step 460 after the entire input word is received and register 330 together with RCL 320 include the resultant reminder r(x), evaluator 340 evaluates the contents of the reminder r(x) at point a 1 .
  • 1 is correlated to the calculated syndrome coefficient S j .
  • calculator 210-j outputs the results of the calculated S j . It should be noted that syndrome calculators 210-0 through 210-t-l execute the method described above concurrently.
  • Fig. 5 shows a non-limiting example of RCL 320 used in this invention.
  • RCL 320 receives 'p' input bits from interface unit 550, as well as 'm' bits of a temporary reminder r ⁇ (x) from register 330.
  • RCL 320 contains the resultant reminder r(x) which is then passed to evaluator 340.
  • RCL 320 includes two computation logic units (CLUs) 510 and 520, two adders 530 and 540, and an interface unit 550.
  • interface unit 550 is common to calculators 210-0 through 210-t-l in syndrome circuit 200, as shown in Fig. 6A.
  • CLUs 510 and 520 include combinational logic of XOR gates.
  • the logic of CLU 510 is derived from the coefficients of the reciprocal polynomial of M j (x) (hereinafter "M " l j (x)”), while the logic of CLU 520 is derived form the coefficients of the polynomial M j (x).
  • Adders 530 and 540 include each an array of 'm' XOR gates.
  • the remainder r(x) is calculated in two stages: first, calculating the quantity r . (x), and second adding the quantity bo(x) to r ⁇ (x), by means of adder 540.
  • Interface unit 550 is used to differentiate bj(x) and bo(x) of the input word b(x), that is holds only the value of bo(x).
  • RCL 320 calculates the reminder rj(x) of the division of bj(x) by M j (x) in two steps: firstly, estimating the current quotient (hereinafter "qj(x)"), using the current 'p' input bits from interface unit 550 and the previously calculated r ⁇ (x); and secondly, updating the reminder rj(x) by multiplying between q;(x) and Mj(x). The reminder rj(x) is temporarily saved in register 330. This process is repeated until the entire input word is received.
  • Adder 530 receives 'm' bits of the previously calculated r ⁇ (x) and the 'm' most significant bits (MSBs) of the input bits, to perform a bit-by-bit XOR operation between these quantities.
  • the 'm' bits of the previously calculated (x) are obtained from register 330.
  • CLU 510 estimates the quotient qj(x) by unifying the output of adder 530 with the 'p-m' least significant bits (LSBits) of the current 'p' input bits, creating a p-bit vector Wj(x), and multiplying Wj(x) with the coefficients of M j " '(x). Only the 'm' LSBits of the result are fed to CLU 520.
  • the coefficients of the M j ' Jx) are constant and determined using the equation:
  • CLU 520 calculates rj(x) by multiplying between the output of CLU 510 (i.e., q.(x)) and the coefficients of M j (x).
  • the m-LSBits of the result CLU 520 are inserted into register 330.
  • register 330 includes the updated reminder as a result of dividing the current 'p' input bits from interface unit 550 of b](x) by M j (x).
  • the quantity bo(x) is ' added to the content of register 330, by means of adder 540. This operation provides the remainder r(x) which is then sent to evaluator 340. In some cases the size of incoming word b(x) is not an integer multiplication of 'p'.
  • interface unit 550 holds 's+m' bits, where the 'm'
  • MSBits of the 's+m" are the quantity bo(x) and the 's' LSBits belong to the quantity b ⁇ (x). It should be noted that the invention described herein is not limited to use of the polynomial divider circuit shown in Fig. 5, and that any means capable of performing polynomial division are suitable.
  • the invention has now been described with reference to specific embodiments. Other embodiments will be apparent to those of ordinary skill in the art.
  • the invention has been described with respect to a BCH code.
  • the invention can be modified to apply to special cases of error correcting codes having similar characteristics, such as Reed- Solomon codes, which are non-binary subsets of BCH codes.
  • the invention applies to a wide variety of linear cyclic invariant codes whose generator polynomials can be factored.

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  • Physics & Mathematics (AREA)
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  • Engineering & Computer Science (AREA)
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  • Error Detection And Correction (AREA)

Abstract

Cette invention concerne un dispositif et un procédé de calcul en parallèle du syndrome (SO) d'un code de correction d'erreur, en particulier d'un code Bose-Chaudhuri-Hocquengbem. Le dispositif comprend une pluralité de calculateurs de syndrome (200) capables de calculer simultanément une pluralité de coefficients de syndrome (s0,s1). Chaque calculateur de syndrome calcule le coefficient de syndrome au moyen d'une division polynomiale, c'est-à-dire calcule le reste de la division d'un mot d'entrée par le polynôme minimal d'un élément a ^nj(460) dans le domaine Galois GF(2^m). Le reste ainsi obtenu est évalué à a^nj. La mise en oeuvre de calculateurs de syndrome en parallèle convient particulièrement bien pour le décodage de données transmises dans des réseaux à ligne haut débit tels que des réseaux de transport optique.
PCT/IL2002/001054 2002-12-30 2002-12-30 Dispositif et procede de calcul en parallele d'un syndrome de code d'erreur WO2004059487A1 (fr)

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PCT/IL2002/001054 WO2004059487A1 (fr) 2002-12-30 2002-12-30 Dispositif et procede de calcul en parallele d'un syndrome de code d'erreur
AU2002360207A AU2002360207A1 (en) 2002-12-30 2002-12-30 An apparatus and method for parallel calculation of an error code syndrome

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4845713A (en) * 1987-06-08 1989-07-04 Exabyte Corporation Method and apparatus for determining the coefficients of a locator polynomial
US5699368A (en) * 1994-03-25 1997-12-16 Mitsubishi Denki Kabushiki Kaisha Error-correcting encoder, error-correcting decoder, and data transmitting system with error-correcting codes
US5887006A (en) * 1997-06-26 1999-03-23 Integrated Device Technology, Inc. Methods and apparatus for error correction

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4845713A (en) * 1987-06-08 1989-07-04 Exabyte Corporation Method and apparatus for determining the coefficients of a locator polynomial
US5699368A (en) * 1994-03-25 1997-12-16 Mitsubishi Denki Kabushiki Kaisha Error-correcting encoder, error-correcting decoder, and data transmitting system with error-correcting codes
US5887006A (en) * 1997-06-26 1999-03-23 Integrated Device Technology, Inc. Methods and apparatus for error correction

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