WO2004056010A1

WO2004056010A1 - Hardware support for sinr calculation and calculation of scaling factors for demodulated symbols in umts mobile stations

Info

Publication number: WO2004056010A1
Application number: PCT/DE2003/003773
Authority: WO
Inventors: Burkhard Becker; Jürgen NIEDERHOLZ
Original assignee: Infineon Technologies Ag
Priority date: 2002-12-13
Filing date: 2003-11-13
Publication date: 2004-07-01
Also published as: DE10258462A1; AU2003292966A1

Abstract

The invention relates to a circuit arrangement (1) for calculating an SINR value and a scaling factor (Norm1,..., Norm4) for demodulated symbols that are MRC combined at cell level in a radio receiver. Said arrangement comprises a first hardware module (9, 10, 11, 12) for calculating intermediate results (SC,exp(M), NC(M), ND(M), SPilot,exp(M), SData,exp(M), (sigmaM<C>)<2>), a second hardware module (13) for calculating the scaling factor (Norm1,..., Norm4) based on the intermediate results and a processor (4) for calculating the SINR value based on the intermediate results.

Description

description

Hardware support for the SINR calculation and the calculation of standardization factors for demodulated symbols in UMTS mobile stations

The invention relates to a hardware module with which the calculation of SINR values and standardization factors for demodulated symbols in UMTS mobile stations is supported.

In mobile radio systems, signals are transmitted from a base station to a mobile station (downlink) and from a mobile station to a base station (uplink) via so-called physical channels. The physical channels of a mobile radio system are specified by standardization. Each physical channel is characterized by a specific carrier frequency, rules for spreading coding and a specific data structure.

The channels provided in the UMTS (Universal Mobile Telecommunications System) standard are defined in the UMTS specification 3GPP TS 25.211 V4.4.0 (2002-03).

In general, a distinction is made between common physical channels (Common Pilot Channel; CPICH), over which certain data are transmitted for all participants, and dedicated physical channels (Dedicated Physical Channel; DPCH), over which participant-specific data are sent.

Common pilot symbols are transmitted via the CPICH channel, which are known a priori to the receiver and which are used for synchronization and measurement purposes. The data transmission via the DPCH channel includes both subscriber-specific user data symbols and dedicated pilot signals. bole. The dedicated pilot symbols serve just as the common pilot symbols for synchronization and measurement purposes.

During the transmission between the base and mobile station, the radio signals are reflected, scattered or diffracted at various obstacles in the propagation path, with the result that several radio signal versions occur at the receiver that are shifted in time from one another.

After reception, the signals are demodulated by a rake receiver. Because of the multipath transmission, the corresponding time delays of the multipath components must be determined for each physical channel to be demodulated and assigned to individual fingers of the rake receiver. The rake fingers, the temporally adjustable Spreizcode- correlators are adjusted to the determined multi-path delay of the received signal and driven with the respective spreading code of the physical channel to be demodulated ^■.

The symbols supplied by the rake fingers are weighted with the respective channel coefficients that were determined from the transmitted common pilot symbols. The symbols that were transmitted within a cell via different propagation paths are then combined with one another. This is called a cell-specific MRC (Maximum Ratio Combining) combination.

In order to be able to combine symbols that have been MRC-combined within a cell over several cells, it is necessary to standardize the symbols beforehand using a cell-specific standardization factor. The normalization factor is composed of a scaling factor and the cell-specific noise variance.

The scaling factor serves to take into account the cell-specific transmission energy based on the data channel at the MRC. conditions and thus transmit power differences of different base stations in the MRC via paths of different base stations. The scaling factor has two factors. The first factor is given by the ratio of the received amplitude of the dedicated pilot symbols to the received amplitude of the common pilot symbols and serves to normalize the MRC-combined symbols to the energy of the dedicated pilot symbols. The second factor is given by the ratio of the transmission energy of the user data symbols transmitted via the DPCH channel to the transmission energy of the dedicated pilot symbols and serves to standardize the energy of the user data symbols.

Furthermore, the ratio of useful power to interference power (signal to interference and

Noise ratio; SINR) in the receiver is of particular importance since, as is often the case, for example in CDMA (Code Division Multiple Access) mobile radio systems, the power control is carried out on the basis of the SINR value. To calculate the SINR value, the expected signal power and the cell-specific noise variance must be calculated.

The basis for calculating the normalization factor and the SINR value are the ^" common pilot symbols transmitted via the CPICH channel and the dedicated pilot symbols and user data symbols transmitted via the DPCH channel. Both the calculation of the normalization factor and the calculation of the SINR The value is carried out cell-specifically so that differences in the transmission energy based on the data channel and the noise variance can be taken into account cell-specifically during the soft handover.

Furthermore, the operating mode of the base station must be taken into account in the calculations mentioned above. For example, the base station can operate in the UMTS standard in normal mode, in STTD (Space Time Transmit Diversity) mode and in CLTD (Closed Loop Mode Transmit Diversity) mode become. In normal mode, the radio signal is emitted by only one antenna of the base station, while in STTD mode two antennas are provided for the radiation of the radio signal. In the CLTD mode, the radio signals are also transmitted by two antennas, but in the CLTD mode the phase relationship and, if appropriate, the amplitudes of the signals transmitted by the two antennas are also variable. This makes it possible to set constructive interference on the receiver side of the transmission channels emanating from the two antennas.

In view of the above conditions, it is understandable that the greatest possible flexibility must be taken into account when calculating the standardization factors and the SINR values.

So far, the standardization factors and the SINR values have been calculated in the firmware using a digital signal processor. The required data, such as common and dedicated pilot symbols, useful data symbols (and channel coefficients), transmitted from the hardware to the digital signal processor. The disadvantage of this procedure is that a digital signal processor entrusted with such tasks requires high computing power, i.e. is expensive, and also has a high power consumption for mobile radio applications.

In order to be able to use digital signal processors with low computing power, certain, recurring computing processes are outsourced to hardware. This also as

Concept called "hardware tuning" enables a significant relief of the digital signal processor. The outsourced, task-specific hardware is often referred to in the literature as "peripheral dedicated hardware", "hardware support" or "(dedicated) datapath". In the following the term "hardware module" is used. The object of the invention is to provide a circuit arrangement which is designed to reduce the computing load of a digital signal processor integrated in the vision arrangement in the cell-specific calculation of the SINR value and in the calculation of the normalization factor for cell-specific MRC-combined symbols. Furthermore, a circuit is to be specified which enables an efficient combination of symbols from different cells. Another object of the invention is to provide a further circuit arrangement by means of which the normalization factor for cell-specific MRC-combined symbols can be calculated. A corresponding procedure should also be given.

The problem underlying the invention is solved by the features of independent claims 1, 17, 18 and 19. Advantageous further developments and refinements of the invention are specified in the subclaims.

The circuit arrangement according to the invention is used to calculate a SINR value and a normalization factor for demodulated symbols and MRC-combined at cell level in a radio receiver. The calculations are carried out at cell level. The circuit arrangement according to the invention comprises a first hardware module, a second hardware module and a processor. Intermediate results are calculated by means of the first hardware module, which are used by the second hardware module to calculate the normalization factor and by the processor to calculate the SINR value.

The processor is relieved of these calculations by calculating the intermediate results in the first hardware module and calculating the normalization factor in the second hardware module. The processor only has to carry out the actual SINR calculation on the basis of the intermediate results. In addition, there is no processing loop About the rake finger hardware, the processor and the MRC hardware.

The normalization factor is preferably calculated from a scaling factor, by means of which the cell-specific transmission energy is taken into account on the basis of the data channel, and from a cell-specific noise variance.

Furthermore, common pilot symbols, dedicated pilot symbols and user data symbols received by the radio receiver are input as input values into the circuit arrangement according to the invention.

According to a preferred embodiment of the invention, the circuit arrangement has a first channel estimator for calculating channel coefficients based on the common pilot symbols and a second channel estimator for calculating channel coefficients based on the dedicated pilot symbols.

A particularly preferred embodiment of the invention provides that the first hardware module contains a first hardware data path and a second hardware data path. Furthermore, the first hardware data path and / or the second hardware data path have at least one selectively addressable and / or selectively evaluable and / or selectively activatable or deactivatable hardware section.

The above-described embodiment of the invention creates a programmability of the first hardware module, which makes it possible, depending on requirements, to select and / or activate only those sections which are designed for the calculation of the intermediate results relevant at that point in time. By deactivating the remaining hardware sections, the power consumption of the circuit arrangement according to the invention can be reduced. At least one complex multiplier, one complex subtractor, one complex square and one accumulator are advantageously arranged in series in the first hardware data path. At least one of the named components of the first hardware data path can in particular be selectively addressed and / or selectively activated or deactivated.

An advantageous embodiment of the second hardware data path provides that it has at least one complex square and at least one accumulator connected downstream of the at least one complex square.

If a plurality of complex squarers and accumulators are arranged in the second hardware data path, an adder can preferably be connected downstream of the accumulators.

Furthermore, a further advantageous embodiment of the first hardware module is characterized in that the second hardware data path has five stages arranged one behind the other.

The first stage contains at least one complex multiplier and at least one downstream accumulator. The second stage involves a complex adder. The third stage has a complex multiplier and an accumulator connected downstream of the complex multiplier. The fourth stage contains at least one complex square and at least one accumulator connected downstream of the at least one complex square. The fifth stage includes an adder. At least one of the five stages and at least one component of the five stages is in particular designed to be selectively addressable and / or to be activated or deactivated selectively. According to a further advantageous embodiment of the invention, the first hardware module has at least one scaling unit for scaling intermediate results.

The second hardware module preferably comprises a division unit, an eraser and in particular an intermediate store.

The division unit can advantageously be characterized by a shift-and-add stage with a ROM table. The shift-and-add level enables an inexpensive and approximate calculation of divisions.

A further preferred embodiment of the invention provides that the calculation equation for the SINR value and / or the calculation equation for the normalization factor is selected as a function of the number of dedicated pilot symbols available and / or of a predetermined accuracy of the calculation.

An advantageous embodiment of the first hardware module is characterized in that intermediate results can be calculated for different operating modes. The flexibility requirements for the calculations of the SINR value and the standardization factor are thus already taken into account by the design of the first hardware module.

For example, the operating modes can include a normal mode without antenna diversity and at least one multi-antenna diversity mode.

The operating modes can be the normal mode, the STTD mode and the CLTD mode when operating the circuit arrangement according to the UMTS standard.

Another aspect of the invention relates to a circuit used to combine demodulated symbols in a radio receiver is designed. This circuit contains a first hardware combination unit, a circuit arrangement according to the invention, a hardware standardization unit and a second hardware combination unit.

Demodulated symbols at the cell level are MRC-combined using the first hardware combination unit. The hardware normalization unit normalizes the symbols combined at the MRC cell level by means of the normalization factor calculated by the circuit arrangement. The second hardware combination unit can then combine the symbols of different cells combined and standardized at the cell level MRC.

The circuit according to the invention described above has the advantage that the calculation of the normalization factor, the normalization of the cell-specific MRC-combined symbols and the cross-cell combination of the symbols are carried out in the hardware. As a result, no hardware-firmware-hardware loops occur.

Another aspect of the invention relates to a circuit arrangement for calculating a normalization factor Norm for demodulated symbols and MRC-combined symbols at cell level in a radio receiver. The calculation is carried out at cell level. The calculation can optionally be based on the equation

or the equation

Np (M)

Norm = p _nff • - - -

^Poff N _C (M) (J. In the equations given above, S _{C / exp} (M) denote a calculated expected signal power, P _off a normalization factor, (σ _M ^c ) ² a cell-specific noise variance, which consists of common pilot symbols is derived, and (σ _W ^T) ² is a cell-specific noise variance, which is derived from the dedicated pilot symbols. the terms N _c (M), and N _D (M) are based on common or dedicated pilot symbols and the points arising from channel parameters calculated. the term S_ _Data, _exp (M) is calculated based on the received useful-data. the selection of the equation for calculating the normalization factor standard can beispielswei- se made on the basis of the available transmitted dedicated pilot symbols and / or the required calculation accuracy. This has the advantage that the cheapest calculation equation can be selected based on the respective circumstances.

The invention is explained in more detail below by way of example with reference to the drawings. In these show:

1 shows a schematic circuit diagram of an exemplary embodiment of the circuit arrangement according to the invention;

2 shows schematic circuit diagrams of hardware architectures as exemplary embodiments for data paths 9 and 10; and 3 shows a schematic circuit diagram of a hardware architecture as an exemplary embodiment for the calculation unit 13.

1 shows a circuit arrangement 1 as an exemplary embodiment of the invention. The circuit arrangement 1 is integrated in a mobile station which receives radio signals transmitted by a base station. The data transmission between the base station and the mobile station is based on the UMTS standard.

In the present exemplary embodiment of the invention, the base station can be operated in normal mode, in STTD mode or in CLTD mode. The circuit arrangement 1 is designed for the processing of symbols which have been transmitted by the base station in one of the three operating modes. In the following description of the mode of operation of the circuit arrangement 1, the mode of operation of the circuit arrangement 1 in normal mode is always dealt with first. The operation of the circuit arrangement 1 in the STTD and CLTD modes is then described.

The calculations described below with regard to circuit arrangement 1 relate to one cell, i.e. on the symbols emitted by a base station.

The circuit arrangement 1 comprises a unit 2 for calculating channel coefficients, a unit 3, by means of which

Standardization factors and intermediate results for the calculation of SINR values are calculated, as well as a digital signal processor 4.

The unit 2 comprises channel estimators 5 and 6 as well as buffers 7 and 8. The channel estimator 5 is used to calculate channel coefficients h ^ (i) for the considered transmission paths m (m = 1,

2, ..., M) of the CPICH channel within the cell under consideration. The channel coefficients h _m (i) are calculated on the basis of received common pilot symbols y _m ± of the CPICH channel.

The index i (i = 1, 2, ..., 10) indicates the position of the common pilot symbol y _mi within the time slot.

The channel coefficients h _m (i) are calculated by means of known hardware circuit arrangements. The channel coefficients h ^ (i) calculated by the channel estimator 5 are in the

Buffer 7 stored. This enables downstream units to access the calculated channel coefficients h ^ (i).

In STTD and CLTD mode, it must be taken into account that the signals from the base station are transmitted by means of two antennas. Consequently, channel coefficients h _{j / m} (i) (j = 1, 2) for the CPICH channel must be calculated in these cases.

The channel estimator 6 is used to calculate channel coefficients h ° for the transmission paths m (m = 1,

2, ..., M) of the DPCH channel within the cell under consideration. These calculations are based on received pilot symbols

^{of the} DPCH channel. The index k (k = 1, 2, ..., K) indicates the position of the dedicated pilot symbol ^ ^0t within the time slot. In order to calculate the channel coefficients °, the channel estimator 6 also has the known pilot symbols p as they were transmitted by the base station.

In the present case, the channel coefficients ^ for the normal mode are calculated in the hardware of the channel estimator 6 using the following equations. Pilot ¹

1_ Pk x _: pilot ^r m, k + Pk ^x m, kh ^ = (1) K = l

Pk + Pk

The index r or i denotes the real or imaginary part of the relevant channel coefficients or pilot symbols.

When operating the base station in STTD or CLTD mode, the different transmission paths of the two transmit antennas must be taken into account. The following applies to the channel coefficients h ° _{m of} the transmission paths starting from the transmitting antenna 1:

The following applies to the channel coefficients h _{2 / Itl of} the transmission _{paths starting} from the transmitting antenna 2:

Pilot ¹ D ¹

1 ^κ P ₂ , k ^x m, k P ₂ , kx pilot ¹ m, kh 2, m [6)

^K k = l

P ₂ , k + P ₂ , k

The channel coefficients h _r and h _{j / m} (j = 1, 2) calculated in the channel estimator 6 are stored in the buffer memory 8.

The unit 3 comprises data paths 9 and 10, scaling units 11 and 12, a calculation unit 13 and buffers 14 and 15.

The data path 9 is provided with the common pilot symbols y _m ^, the channel coefficients h ^ (i) and h? (i) the CPICH channel and the channel coefficients h ° and h? of the DPCH channel

An expected signal power is in the data path 9

S _{C; exp} (M) and standardization components N _C (M) and N _D (M) are calculated. The following applies to normal mode:

S _C , exp ⁽ M ⁾ = ∑ ∑ K ⁽ i ^{) •} h ° (7) τrt = lx = l

N _C (M) = ∑ ∑ £ (i) (8) m = lι = l

N _D (M) = £ | h ^ (9) m = l

In equation (7), the channel coefficient hc _m * (i) marked with an asterisk denotes the complex conjugate of the channel coefficient h (i). Correspondingly, complex conjugate variables are identified by an asterisk in the following. In equations (7) and (8), the parameter L indicates the number of channel coefficients h (i) that are required for the respective

Sum formation can be used. A prerequisite for determining the parameter L is that the common pilot symbols y _mj _ belonging to the channel coefficients h (i) forming the sum are all within a DPCH time slot. Another requirement in STTD or CLTD mode is that as many common pilot symbols A as -A are used. L = 8 (maximum number L = 10) preferably applies, so that 4 common pilot symbols A and 4 common pilot symbols -A are used in STTD or CLTD mode.

In STTD mode, the expected signal power S _{C / exp} (M) and the normalization components N _C (M) and N _D (M) are calculated according to the following equations.

S _{C /} exp (M) = ∑ ∑ h: 1, m (i) • h ¹ ° l, m + h? 2, _m m ⁽ D h "2, ι (10) m = li = l

N _c CM) = ∑ ∑ h £ _B CL) + ^h 2, m & (11) m = li = l

2 \

N _D (M) = ∑ Nti 1, + h 2, m (12) m = l)

In CLTD mode, antenna weights W _x and W ₂ must be taken into account. The antenna signals W _x and W ₂ are applied to the dedicated signals that are to be emitted by the two antennas. On the other hand, the common pilot symbols are not subjected to the antenna weights W _x and W ₂ . The two diversity components are evaluated by multiplying the dedicated signals to be transmitted by the antenna weights Wi and W ₂ . The

The choice of antenna weights W _x and W ₂ has the aim of maximizing the energy received by the mobile station per time slot, taking into account the weight quantization specified in the UMTS standard. The antenna weights W _x and W ₂ must be estimated based on the channel coefficients based on the common pilot symbols in the mobile station. The

Estimation is preferably carried out in the digital signal processor 4. For the expected signal power S _{C; exp} (M) and for the

Standardization components N _C (M) and N _D (M) result in the following equations in CLTD mode.

S _C , exp (M) W _χ + h £ _m (i) w, h (13)

2λ N _C (M) = £ y tti) • W _x + h ₂ , _m () ^• W ₂ (14) m = lx = l

With equations (13) and (15) it should be noted that h £ "m == hh? Ll ,, _m mm + + hti ° 2 2 ,, mm

After their calculation, the expected signal power S _{c ^ exp} (M) and the normalization components N _C (M) and N _D (M) are scaled in the scaling unit 11, from which a scaled expected signal power S _{C (} (M) and scaled Standardization components N _C (M) and N _D (M) result according to the following equations.

ScexpM M ¹¹ C, exp (M) (16)

i Ni _r C (M) = N _C (M) (17)

L • M

N _D (M) = - • N _D (M) (18) M

The scaled expected signal power S _c C, _e _x x _D ( ^» M) and the scaled standardization components N _C (M) and N _D (M) are in the Buffer 14 is temporarily stored and forwarded to the calculation unit 13.

The data path 10 is provided with the common pilot symbols y _mi , the dedicated pilot symbols x ^ ¹ _k ^ot , useful data symbols x ^ ³ transmitted over the DPCH channel and the channel coefficients h ^ (i) or h _{j / tn} (i) des CPICH channel fed.

In the data path 10, summation values S _{pilot ^ exp} (M) and S _{Data / exp} (M) are calculated, which result from a summation of the dedicated

Pilot symbols ^ _k ° ^fc or the user data symbols x ^ over one

Time slot and emerge over all considered transmission paths within the considered cell. The sum square of the summands is formed before the summation.

M

pilot

^S pilot, exp ( ^M ) = ∑ ∑ ^l τn, k (19) m = lk = l

M Koatal + ^K Data2

Data

S _D ata- exp (M) = ∑ ∑ ^x m, k (20) m = lk = l

In equation (20) K _Datal and _Data2 K denotes the number of payload data symbols x ^ _k ^a i ⁿ the first and second Nutzdatensymbol portion of the DPCH timeslot.

Scaled summations are obtained in the scaling unit 12 from the summation values S _{pilot / exp} (M) and S _{data (exp} (M)

S _{pilot (eχp} (M) and S _{Dat3 (} (M) calculated according to the following equations.

Spiiot, exp ( ^M ) = ^ - ^ ^• Spii _ot , exp (M) (21)

§Data, exp ( ^M ) = ZT-I T ^ ^'S Data, exp ( ^M) (22) ^m ' ^ Datal ⁺ ^ Data2 ^ Furthermore, an integration component ω ^ is calculated in the data path 10 for the later calculation of the noise variance (σ ^ j. In normal mode, the following applies to the integration component ω _M :

In the STTD and CLTD modes, the integration component ω _{M is} calculated using the following equation:

ω »∑ ∑ Ym ,! - h £ _m ⁽ i ⁾ Pι, i - h ₂ , _m (i) P2 (24) ra = li = l

The cell-specific noise variance (σ _M J for the data channel according to the following equation can be calculated from the integration component ω ^, with SF _C and SF _D for the

Spreading factor in the CPICH or DPCH channel.

te - • ω _M (25)

(L - 1) • M SE ^M

The noise variance (σ _M is derived from the integration component α- _M and scaled in the scaling unit 12.

The scaled summation values S _pilot (M) and S _Dat ^ (M) as well as the noise variance are forwarded by the scaling unit 12 both to the calculation unit 13 and to the buffer store 15.

The SINR values are calculated in the firmware by means of the digital signal processor 4. For this purpose, the scaled expected signal power S _c (M) and the scaled standardization components N _C (M) and N _D (M) are obtained from the buffer memory 14 via a common data buffer 16 transferred to the digital signal processor 4. Furthermore, the scaled sum- S _{pilot /} (M) and S _{Data (eχp} (M) as well as the noise variance

(σ ^ j transmitted from the buffer 15 to the digital signal processor 4 via the common data buffer 16.

Four different equations are available in the digital signal processor for calculating a SINR value. When selecting the respective equation, the number of available dedicated pilot symbols x ^ ⁰ within the considered time slot of the DPCH channel must be taken into account. If there are many dedicated pilot symbols x ^ _k ^{ot available} within the time slot, a SINR value SINR- _{L is} calculated using the channel coefficients h ^ (i) or h? (i) and h ° or hl? according to the following

Equation calculated:

If only a few dedicated pilot symbols x ^ _k ^{ot are available} within the considered time slot of the DPCH channel, a SINR value SINR _{2 is} calculated on the basis of the user data symbols ^x _mk ^a :

SINR ₂ = (27)

Equations (26) and (27) represent the preferred calculation equations for the SINR values under the respective conditions.

If a low accuracy is sufficient when calculating the SINR value, the computational effort can be reduced by calculating a SINR value according to one of the two following equations. SINR ₃ = N _D (M) • η r- (28)

The noise variance

in equation (29) can be calculated in the firmware as follows:

) ² = ^ ^■ 4 = S _pilot , _exp (M) - N _D (M) (30)

The integration component υ ^ is defined by the following equation:

M K,

,, 2 _ V _v ^pilo ι-, DD, DD - ^, _. , ^υ M - 2-ι 2- _t ^X m, k ⁿ l, ra ^' Pl, k ~ ⁿ ₂ , m ^' P ₂ , k ^ - ^{i ±} > m = lk = l

Standardization factors for symbols that have been combined in a cell-specific MRC manner are calculated in the calculation unit 13.

Various equations are available for calculating the normalization factors. As with the calculation of the SINR values, the number of available dedicated pilot symbols ^ _k ^ot within the considered time slot of the DPCH channel must be taken into account. If many dedicated pilot symbols ^ ⁰ * are available within the time slot, a normalization factor Norm _{x is} calculated using the channel coefficients h ^ (i) or h _jjltl (i) and h _m or h _{j / Itl} according to the following equation :

_Standard, _off = p • (32)

After the MRC combination, the symbols are at the energy level of the common pilot symbols y _m i due to the weighting with the channel coefficients h (i) and h _jm (i). By including the expected signal power S _{C (6} , _xp (M) in the normalization factor Norm _x , the MRC-combined symbols are normalized to the energy of the dedicated pilot symbols x ^ _k ^0t . For normalization to the energy of the user data symbols ^x _rr - ^a i the factor ^st p _off is provided in equation (32) the factor p _off is calculated on the basis of the offset pilot ₀ ff _S ET WEL rather the difference between the energy level of the dedicated pilot symbols ^ ⁰¹ and the energy level of the useful-data ^ _k ^a indicates.:

Poff = 10 ² ° (33)

If only a few dedicated pilot symbols ^ _k ^{ot are available} within the time slot of the DPCH channel under consideration, a normalization factor norm _{2 is} calculated on the basis of the useful data symbols ° ^a _k ^& :

The inclusion of the summation value S _{Data exp} (M) in the normalization factor Norm ₂ brings about a normalization of the MRC-combined symbols to the energy of the useful data symbols

Data ^x m, k ^•

Equations (32) and (34) represent the preferred calculation equations for the normalization factors Norm _x and Norm ₂ under the respective conditions.

If a low level of accuracy is sufficient when calculating the standardization factor, the computation effort can be reduced. be decorated and the normalization factor can be calculated according to one of the two following equations.

Norm ₃ = p _off • (35)

| N _n (M) 1,,

Norm ₄ = p _off ^• ^^ - ^• γ- ^ ä ⁽³⁶⁾

N _r (M)

A standardization unit 18 is fed with the standardization factor Norm- _L , Norm ₂ , Norm ₃ or Norm ₄ calculated by the calculation unit 13. The standardization unit 18 also receives symbols from a calculation unit 17 which have been MRC-combined within a cell. The MRC-combined symbols are multiplied in the standardization unit 18 by the standardization factor Norm- _L , Norn- ₂ , Norm ₃ or Norm ₄ .

After normalization in the standardization unit 18, the cell-specific MRC-combined and normalized symbols are combined in a calculation unit 19 downstream of the standardization unit 18 over several cells. The symbols combined in this way are forwarded by the calculation unit 19 to the digital signal processor 4 for further processing.

2 shows schematic circuit diagrams of hardware architectures as exemplary embodiments for the data paths 9 and 10.

The data path 10 has inputs INI, IN2, IN3 and IN4, outputs OUT1, OUT2 and OUT3 and control inputs CONTROL1 and CONTROL2. As components, the data path comprises 10 units INV / SH / ADD1 and INV / SH / ADD2, a complex subtractor CSUB1, a multiplexer MUX1, a complex squarer CSQR1, an accumulator ACCU1 and a demultiplexer DEMUX1. The input of the unit INV / SH / ADD1 or INV / SH / ADD2 is the input IN3 or IN4. The control input of the INV / SH / ADD1 or INV / SH / ADD2 unit is the CONTROL1 or CONTROL2 control input. The complex subtractor CSUB1 is connected on the input side to the input IN2 and the outputs of the units INV / SH / ADD1 and INV / SH / ADD2. The output of the complex multiplier CSUB1 is the output OUT1. The multiplexer MUX1 is connected on the input side to the INI input and to the output of the complex subtractor CSUB1. The complex squarer CSQRl, the accumulator ACCUl and the demultiplexer DEMUX1 are connected in series behind the multiplexer MUXl. The outputs of the demultiplexer DEMUX1 are the outputs OUT2 and OUT3.

The data path 10 comprises a pipeline stage. This means that input values from data path 10 are always processed within one clock cycle.

The summation _value S _Pilotexp (M) in accordance with equation (19), the summation value S _{Data (exp} (M) in accordance with equation (20) and the integration component ω ^ in accordance with equation (23) or (24) are calculated in the data path 10 The contribution that a rake finger, ie a transmission path m, contributes to one of the above-mentioned variables when a new user data symbol, dedicated pilot symbol or a common pilot symbol is present is calculated in one clock cycle.

To calculate the summation _value S _pilotexp (M) or ^S _Data , _exp (Nθ), the dedicated pilot symbols x ^ ⁰ or the useful data symbols x ° ^{aa are} entered in the input INI. In the complex squarer CSQRl, the dedicated pilot symbol is used x ^ _k ^{0t or} the user data ^symbol ^ each form the square of the amount. The complex squarer CSQRl performs the operation (a + jb) (a- jb) on a complex input value a + jb. The square of the amount are summed up in the accumulator ACCUl. The integration component ω ^ is calculated in the data path 10 by the common pilot symbols y _m i in the input IN2, the channel coefficients h (i) or h _lm (i) in the input IN3 and the channel coefficients h _{2 (} in the input IN4 _in (i) The control input CONTROL1 is fed with the known pilot symbols pf or pζ ± The control input CONTROL2 is fed with the known pilot symbols p _2ι ±.

The units INV / SH / ADD1 and INV / SH / ADD2 multiply the channel coefficients h C _m (i), hP _m (i) and h ₂ P _m (i) by the known pilot symbols p ±, p ^ and p _{2 / i} through. Since the well-known pilot symbols

, p _x P _j _ and p ₂ p _ only the values 1 + j and -

1-j, no real multiplications have to be carried out in the units INV / SH / ADD1 and INV / SH / ADD2. Rather, it is sufficient to perform sign inversions and additions. Furthermore, the units INV / SH / ADD1 and INV / SH / ADD2 can also carry out shift operations.

The complex subtractor CSUBl and the complex square

CSQRI perform the subtractions and the formation of the squares according to equations (23) and (24). The ACCUl accumulator sums up the squares of amounts.

For the processing of the tasks of the data path 10 described above, the multiplexer MUX1 must be controlled in such a way that the required values are passed through.

Data path 9 has inputs IN5 to IN14 and outputs OUT4 to OUT10. As components, the data path 9 contains complex multipliers CMULT1, CMULT2 and CMULT3, complex squarers CSQR2 and CSQR3, multiplexers MUX4 and MUX5, complex accumulators ACCUC2, ACCUC3 and ACCUC4, accumulators ACCU5 and ACCU6, a complex adder CADD1 and a real adder ADD1. The complex multiplier CMULT1 and the complex accumulator ACCUC2 are arranged one after the other in the order given. The inputs of this series connection represent the inputs IN5 and IN6. The output of the series connection is the output OUT4.

The complex multiplier CMULT2 and the complex accumulator ACCUC3 are connected in series in a corresponding manner. The inputs of this series connection are the inputs IN7 and IN8. Its output is the OUT5 output.

The outputs of the complex accumulators ACCUC2 and ACCUC3 are connected to the inputs of the complex adder CADD1. The output of the complex adder CADD1 is the output OUT6.

The inputs of the complex multiplier CMULT3 are the inputs IN9 and IN10. The input IN10 is connected to the output of the complex adder CADDl. The complex ACCUC4 accumulator is connected behind the complex multiplier CMULT3. The output of the complex ACCUC4 accumulator is the output OUT7.

The multiplexer MUX4, the complex squarer CSQR2 and the accumulator ACCU5 are connected in series in the order given. On the input side, the multiplexer MUX4 is connected to the input IN13, to the outputs of the complex accumulators ACCUC2 and ACCUC4 and to the output of the complex adder CADDl. The input of the complex squarer CSQR2 is the input IN11. The output of the ACCU5 accumulator is the output OUT8.

The multiplexer MUX5, the complex squarer CSQR3 and the accumulator ACCU6 are connected in series in the order given. On the input side is the multiplexer MUX5 with the input IN14, with the outputs of the complex battery ACCUC3 and ACCUC4 and connected to the output of the complex adder CADDl. The input of the complex squarer CSQR2 is the input IN12. The output of the ACCU6 accumulator is the output OUT10.

The real adder ADD1 has connections on the input side to the outputs of the accumulators ACCU5 and ACCU6. The output of the real adder ADD1 is the output OUT9.

The data path 9 comprises a total of three pipeline stages. The complex multipliers CMULT1 and CMULT2 are at the center of the first pipeline stage. The second pipeline stage contains the complex multiplier CMULT3, and the third pipeline stage is characterized by the complex squarers CSQR2 and CSQR3. The processing time of an input value is one clock cycle per pipeline stage.

The expected signal power S _{C / Θxp} (M) according to equation (7), (10) or (13), the normalization component N _C (M) according to equation (8), (11) or (14 ) and the normalization component N _D (M) calculated according to equation (9), (12) or (15). In this case, the contribution that a transmission path m contributes to one of the abovementioned variables when a new dedicated pilot symbol or common pilot symbol is present is calculated in one clock cycle.

In normal mode, the expected signal power S _{C (exp} (M) is calculated in accordance with equation (7) by feeding the conjugate complex channel coefficients hc _m * (i) into the input IN5 and the channel coefficients h ° into the input IN6 The complex multiplier CMULT1 carries out the required multiplications. In the further processing path, the complex accumulator ACCUC2 is bypassed and the amount squares are formed in the complex square CSQR2, which are summed up in the accumulator ACCU5. In STTD mode, the input IN5 with the conjugate complex channel coefficients hc _{lr Ta} * (i), the input IN6 with the channel coefficients h ° _m , for the calculation of the expected signal power S _{C / Sxp} (M) according to equation (10) Input IN7 with the conjugate complex channel coefficients hc _{2; m} * (i) and the

Input IN8 fed with the channel coefficients _{2? M.} These input values then pass through the complex multiplier CMULT1 or CMULT2. The complex accumulators ACCUC2 and ACCUC3 are bypassed and sums are formed in the complex adder CADD1. The complex square CSQR2 forms the square of the amounts from these sums. The resulting squares are summed up in the ACCU5 accumulator.

In CLTD mode, the expected signal power S _{C (βxp} (M) is calculated according to equation (13) by using the conjugate complex channel coefficients hc _xm * (i) in the IN5 input and the antenna weights W _x in the IN6 input. the conjugate complex channel coefficients hc _{2 m} * (i) are fed into the input IN7 and the antenna weights W _{2 are} fed into the input IN8.

Furthermore, the channel coefficients h ° are entered in the input IN9. The respective products are formed in the complex multipliers CMULT1 and CMULT2. The complex adder CADD1, the complex multiplier CMULT3 and the complex squarer CSQR3 are then run through, bypassing the complex accumulators ACCUC2, ACCUC3 and ACCUC4. The resulting values are summed up in the ACCU6 accumulator.

The normalization component N _C (M) is in the normal mode according to

Equation (8) is calculated by entering the channel coefficients h ^ (i) into input IN13. The channel coefficients h ^ (i) then pass through the complex squarer CSQR2 and the accumulator ACCU5. The result is output at output OUT8. The calculation of the normalization component N _D (M) in the normal

Mode according to equation (9) is carried out in the normal mode like the calculation of the normalization component N _C (M) described above. Instead of the channel coefficients h _m (i), the channel coefficients h ° are entered in the input IN13.

For the calculations of the normalization components N _C (M) and N _D (M) in the STTD mode according to equations (11) and (12), the channel coefficients h _m (i) and h ° _m are entered into the input IN13 and into the input IN14 entered the channel coefficients h ₂ P _(tn (i) or hel _r . These input values pass through the complex squarer CSQR2 or CSQR3 and the accumulator ACCU5 or ACCU6. An addition step then takes place in the real adder ADD1 Output OUT9 output.

When calculating the normalization component N _C (M) in CLTD mode according to equation (14), the input values for the

Inputs IN5 to IN8 use the same input values as in the calculation of the expected signal power S _{C / exp} (M) described in CLTD mode. These input values pass through the complex multiplier CMULT1 or CMULT2, the complex square CSQR2 or CSQR3 and the accumulator ACCU5 or ACCU6. After an addition step has been carried out in the real adder ADD1, the result is output at the output OUT9.

The calculation of the normalization component N _D (M) in the CLTD mode according to equation (15) is carried out in the same way as the calculation of the normalization component N _D (M) described in the normal mode.

In the case of the data paths 9 and 10 shown in FIG. 2, it should be noted that for the calculation of the individual intermediate results, from which the SINR value and / or the standard Mation factor are calculated, not all components of data paths 9 and 10 are always required. The components of the data paths 9 and 10 that are not required in each case can be deactivated, for example, during this time. Furthermore, provision can also be made to deactivate components that are not required by feeding corresponding input values, such as zeros, into the respective inputs.

3 shows a schematic circuit diagram of a hardware architecture as an exemplary embodiment of the calculation unit 13.

The calculation unit 13 comprises multiplexers MUX6 and MUX7, a division unit 20, an eraser 21 and a buffer 22.

The scaling units 11 and 12 of the circuit arrangement 1 are connected on the output side to the inputs of the multiplexers MUX6 and MUX7. There is also a connection from the scaling units 11 and 12 to the buffer store 22.

The multiplexer MUX6 feeds the division unit 20 and the eraser 21. The multiplexer MUX7 feeds the division unit 20. The division unit 20, the eraser 21 and the buffer store 22 are connected in series in the order given. A connection from the buffer store 22 to the input of the division unit 20 is also provided.

The standardization unit 18 of the circuit arrangement 1 is connected downstream of the buffer store 22.

To calculate the normalization factors Norm _x to Norm ₄ , the calculation unit 13 receives the scaled expected signal power S _c (M) and the scaled normalization components N _C (M) and N _D (M) from the scaling unit 11 and the scaled gated summation value S _{Dat xp} (M) and the noise variance

(σ ^ j from the scaling unit 12. These values can either be forwarded directly to the division unit 20 via the multiplexer MUX7 or initially stored in the intermediate store 22 and transferred to the division unit 20 at a later point in time.

Furthermore, the calculation unit 13 is supplied with control signals by the scaling units 11 and 12 via the multiplexer MUX6. The control signals are used to inform the calculation unit 13, for example, of the values in the scaling units 11 and 12 for further processing in the

Calculation unit 13 are available and which of the four different standardization factors Norm- _L , Norm ₂ , Norm ₃ and Norm _{4 is to} be calculated.

The normalization factors are calculated in the calculation unit 13 in accordance with equation (32), (34), (35) or (36). The quotient or root formations required for this are carried out in the division unit 20 or in the root extractor 21.

In the present exemplary embodiment, it is provided that the division unit 20 has a shift-and-add stage with a ROM table. This design known to the person skilled in the art enables an approximate calculation of the divisions.

In the present case, the roots in the root extractor 21 are also calculated using a ROM table.

Claims

claims

1. Circuit arrangement (1) for calculating a SINR value and a normalization factor (Normi, ..., Norm ₄ ) for demodulated and at the cell level MRC-combined symbols in a radio receiver, the calculations being carried out at the cell level with

- A first hardware module (9, 10, 11, 12) for calculating intermediate results (S _c - _exp (M), N _c (M), N _D (M), S _P ι- _lo t _.e x _p (M), S _Data , _e xp (M), (σ „ ^C ) ² ),

a second hardware module (13) for calculating the normalization factor (Normi, ..., Norm) on the basis of the intermediate results (S _c , _e __ _p (M), N _C (M), N _D (M), S _{Pilot / e} χ _p (M), S _Da - t _a , exp (M), (σ _M ^c ) ² ), and - a processor (4), which is based on the intermediate results (S _c , exp (M ), N _C (M), N _D (M), Spiiot.θxp (M). S _Data , exp (M),

(c5Η ^c ) ² ) performs the calculation of the SINR value.

2. Circuit arrangement (1) according to claim 1, d a d u r c h g e k e n n z e i c h n e t,

- that the normalization factor (Normi, • • ■ _standard. ₄₎ from a scaling factor for the integration of cell-specific transmit power on the basis of the data channel and of a cell-specific noise variance ((σ _M ^c) ²⁾ is calculated.

3. Circuit arrangement (1) according to claim 1 or 2, d a d u r c h g e k e n n z e i c h n e t,

- That the circuit arrangement (1) with the radio receiver received from the radio pilot symbols (y _{m #} i), dedicated pilot symbols (x ^ _k ^ot ) and useful data symbols (^ _k ³ ) is fed.

4. Circuit arrangement (1) according to claim 3, g e k e n n z e i c h n e t d u r c h - a first channel estimator (5) for calculating channel

PP efficient (h _m (i), h _{j (tn} (i)) based on the common pilot symbols (y _m i), and a second channel estimator (6) for calculating channel coefficients (h ° ^D , hh °? _m ^' ) using the dedicated pilot signal

5. Circuit arrangement (1) according to one or more of the preceding claims, d a d u r c h g e k e n n z e i c h n e t,

- That the first hardware module (9, 10, 11, 12) has a first hardware data path (10) and a second hardware data path (9), the first hardware data path (10) and / or the second hardware - Data path (9) contain at least one selectively addressable and / or selectively evaluable and / or selectively activatable or deactivatable hardware section.

6. Circuit arrangement (1) according to claim 5, d a d u r c h g e k e n n z e i c h n e t,

- That in the first hardware data path (10) at least one complex multiplier (INV / SH / ADDl, INV / SH / ADD2), a complex subtractor (CSUBl), a complex square (CSQRl) and an accumulator (ACCUl) are arranged one behind the other , in particular at least one component of the first hardware data path (10) being selectively addressable and / or selectively activating or deactivating.

7. Circuit arrangement (1) according to claim 5 or 6, d a d u r c h g e k e n n z e i c h n e t,

- That the second hardware data path (9) has at least one complex square (CSQR2, CSQR3) and at least one accumulator (ACCU5, ACCU6) connected downstream of the at least one complex square (CSQR2, CSQR3).

8. Circuit arrangement (1) according to claim 7, characterized in that - in the case of a plurality of complex squarers (CSQR2, CSQR3) and accumulators (ACCU5, ACCU6), the accumulators (ACCU5, ACCU6) are followed by an adder (ADD1).

9. Circuit arrangement (1) according to one or more of claims 5 to 8, d a d u r c h g e k e n n z e i c h n e t - that the second hardware data path (9) has:

a first stage with at least one complex multiplier (CMULT1, CMULT2) and at least one accumulator (ACCUC2, ACCUC3) connected downstream of the at least one complex multiplier (CMULT1, CMULT2), a second stage with a complex adder (CADD1),

- a third stage with a complex multiplier

(CMULT3) and an accumulator (ACCUC4) connected downstream of the complex multiplier (CMULT3),

a fourth stage with at least one complex square (CSQR2, CSQR3) and at least one accumulator (ACCU5, ACCU6) connected downstream of the at least one complex square (CSQR2, CSQR3), and

- a fifth stage with an adder (ADD1), and wherein

- In particular, at least one stage and at least one component of the stages are selectively addressable and / or can be selectively activated or deactivated.

10. Circuit arrangement (1) according to one or more of the preceding claims, d a d r r c h g e k e n n z e i c h n e t,

- That the first hardware module (9, 10, 11, 12) at least one scaling unit (11, 12) for scaling intermediate results (S _c , _exp (M), N _C (M), N _D (M), Spiio _t , _e χp (M), S _Da - _ta , _exp (M), ω _M ² ).

11. Circuit arrangement (1) according to one or more of the preceding claims, d a d u r c h g e k e n n z e i c h n e t,

- That the second hardware module (13) has a division unit (20), an eraser (21) and in particular an intermediate memory (22).

12. Circuit arrangement (1) according to claim 11, d a d u r c h g e k e n n z e i c h n e t,

- That the division unit (20) contains a shift-and-add stage with a ROM table.

13. Circuit arrangement (1) according to one or more of claims 3 to 12, d a d u r c h g e k e n n z e i c h n e t,

- That the calculation equation for the SINR value and / or the calculation equation for the scaling factor

(Normi, ..., Norm ₄ ) depending on the number of dedicated pilot symbols available (x ^ _k ^ot ) and / or on a given accuracy of the calculation.

14. Circuit arrangement (1) according to one or more of the preceding claims, d a d u r c h g e k e n n z e i c h n e t,

- That the first hardware module (9, 10, 11, 12) is designed, intermediate results (S _{C / e} χp (M), N _c (M), N _D (M), S _P i_ i _o t, exp (), S _Data.e χp (M), (σ _M ^c ) ² ) for different operating modes.

15. Circuit arrangement (1) according to claim 14, d a d u r c h g e k e n n z e i c h n e t,

- That the operating modes include a normal mode without antenna diversity and at least one multi-antenna diversity mode.

16. Circuit arrangement (1) according to claim 14 or 15, d a d u r c h g e k e n n z e i c h n e t,

- That the operating mode when operating according to the UMTS standard include the normal mode, the STTD mode and the CLTD mode.

17. Circuit for combining demodulated symbols in a radio receiver, with a first hardware combination unit (17) for the MRC combination of demodulated symbols at cell level,

- A circuit arrangement (1) according to one or more of the preceding claims, - A hardware standardization unit (18) for normalizing the symbols combined at the cell level by means of the normalization factor calculated by the circuit arrangement (Normi, • • • Norm ₄ ), and

- A second hardware combination unit (19) for combining MRC-combined and standardized symbols of different cells.

18. Circuit arrangement (1) for calculating a normalization factor norm for demodulated and at the cell level MRC- combined symbols in a radio receiver, the calculation being carried out at the cell level and the calculation optionally using the equation

or the equation

where S _c , _e - _p (M) is a calculated expected signal power, N _c (M) is calculated using common pilot symbols, N _D (M) is calculated using dedicated pilot symbols, S _Data , _exp (M) is calculated on the basis of received useful data _symbols , p _{Qff is} a normalization _factor , (σ _M ^c ) ^{2 is} a cell-specific noise variance that is derived from common pilot symbols, and (σ _M ^D ) ^{2 is} a cell-specific noise variance that is derived from dedicated pilot symbols.

19. Method for calculating a standardization factor for demodulated symbols and MRC-combined symbols at a cell level in a radio receiver, the calculation being carried out at the cell level and the calculation optionally using the equation

or the equation

N _n (M) norm = p _nff ■ I— -

^Foff - \ | N _C (M)

or the equation

takes place, where S, _e Mp (M) is a calculated expected signal power, N _C (M) is calculated using common pilot symbols. net, N _D (M) is calculated using dedicated pilot symbols, S _Data , _exp (M) is calculated using received user data _symbols , p _{0ff is} a normalization _factor , (σ _M ) ^{2 is} a cell-specific noise variance that is calculated from common pilot symbols , and (σ _M ^D ) ^{2 is} a cell-specific noise variance that is calculated from dedicated pilot symbols.