WO2004049582A1

WO2004049582A1 - Receiver for processing a received signal

Info

Publication number: WO2004049582A1
Application number: PCT/IB2003/005004
Authority: WO
Inventors: Dominique Brunel; Laurent Noel
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2002-11-27
Filing date: 2003-11-05
Publication date: 2004-06-10
Also published as: AU2003278448A1

Abstract

The present invention relates to a receiver (REC) for receiving a signal (SEQ), said signal (SEQ) having a bandwidth. The invention is characterized in that the receiver comprises: -spreading means (SPR) for spreading the bandwidth of said signal (SEQ) with spreading sequence (PN1), -first rejection means (HPF1) for rejecting DC offset on said spread signal (SEQ), and -despreading means (DSPR) for despreading said spread signal (SEQ) with a despreading sequence (PN2).

Description

Receiver for processing a received signal

Field of the invention

The present invention relates to a receiver for processing a received signal according to the preamble of claim 1. The invention further relates to an associated method for processing a received signal according to the preamble of claim 6. Such a receiver may be used in particular in any terminals using standards like

GSM.

Background of the invention

A terminal comprises a receiver which can have many kinds of architectures, described in the prior art, for managing a received signal.

A first architecture, known as super heterodyne architecture, uses an intermediate frequency IF (190MHz for example) which enables to easily filter some adjacent carrier frequencies that are undesirable. It is necessary to down-convert the intermediate frequency IF to baseband (0Hz) for further processing. A drawback of this architecture is that in order to do so, it is necessary to have a lot of components of which two local oscillators and some acoustic filters, which cannot be integrated in a circuit. This leads to some size, cost and power consumption problems.

A second architecture, known as zero IF architecture or direct conversion receiver DCR and disclosed in the document of B. Lindquist et al.: "A new approach to eliminate the dc offset in a TDMA direct conversion receiver", in Proc. IEEE Vehicular Technology Conf, May 1993, pp. 754-757, is a possible solution to alleviate the problems of the super heterodyne architecture, as it uses no intermediate frequency IF. This solution needs only one local oscillator and all its components can be integrated in a circuit. However, there are two major limitations to these DCRs, which make applications to narrowband systems like GSM systems difficult to realize. The first limitation is the existence of DC offsets mainly due to self-mixing of the local oscillator and the RF antenna because of some leakage problems, which are inherent in RF IC designs. The second limitation is that the mixer, which is used to make the down conversion, produces second-order intermodulation, which introduces not only undesirable spectral components in the RX bandwidth, but also a DC component, which degrades the receiver sensitivity. A third architecture, known as Near Zero IF architecture uses an intermediate frequency IF of for e.g. 1MHz, where DC offsets, adjacent carriers and image frequencies are partially removed through the use of Polyphase Bandpass filters. During the demodulation of the signal, the intermediate frequency IF is converted to the baseband and the adjacent carrier frequencies are filtered via a complex low pass filter. But, as there is a need to down-convert the intermediate frequency IF to the baseband, a digital local oscillator is needed which leads to power consumption and to a more complicated design for the receiver.

Summary of the invention Accordingly, it is an object of the invention to provide a receiver and a method for processing a received signal, which overcome the disadvantages of the prior art.

To this end, according to a first object of the invention, there is provided a receiver as claimed in claim 1.

In addition, according to a second object of the invention, there is provided a method as claimed in claim 6.

As we will see in detail further on, such a receiver, in particular, permits to easily suppress the DC offset of the received signal with no use of complex DC compensation loops via a spreading of the received signal and without much distortion of the received signal.

Brief description of the drawings

Additional objects, features and advantages of the invention will become apparent upon reading the following detailed description and with reference to the accompanying drawings in which: - Fig.1 illustrates an architecture of the receiver according to the invention,

- Fig.2 illustrates a sketch of a GSM-like signal received by the receiver of Fig.1 and one adjacent carrier,

- Fig.3 illustrates the spectrum of the spread spectrum local oscillator centered at a frequency F0 of the receiver of Fig.1, - Fig.4 illustrates the spectrum of a spreading sequence after further rejection means of the receiver of Fig.1 when configured to provide a Root Raised Cosine impulse response with a roll-off factor of 0.22,

- Fig.5 illustrates a baseband spectrum of an unfiltered 3.84Mchip/s PN spreading sequence used by some spreading means of the receiver of Fig.1 in the frequency domain,

- Fig.6 illustrates an initial received signal and the spectrum of the signal output by the spreading means of the receiver of Fig.1 after down conversion,

- Fig.7 illustrates the signal output by some first rejection of DC offset means of the receiver of Fig.1 in the frequency domain, and

- Fig.8 illustrates the received signal output by some despreading means of the receiver of Fig.1, after analog integration in the frequency domain.

Corresponding reference numerals will be used throughout the description for corresponding elements.

Detailed description of the invention

In the following description, well-known functions or constructions to the person skilled in the art are not described in detail since they would obscure the invention in unnecessary detail. The present invention relates to a receiver REC for processing a received signal SEQ, comprising a local oscillator LO, said signal SEQ having a bandwidth.

Said receiver REC is used in particular in GSM communication systems and more particularly in a mobile phone. Such a receiver is illustrated in Fig.l.

The receiver REC comprises: a radio frequency RF chip with:

- a spreading section with spreading means SPR for spreading the bandwidth of the received signal SEQ with a spreading sequence PNl,

- first rejection means HPFl for DC offset rejection on said spread signal, and adjacent channel removing means or channel filters LPF 1 ,

- a controlled gain amplifier AGC for amplifying the gain of the received signal SEQ, and

- a despreading section with despreading means DSPR for despreading the spread signal SEQ with a despreading sequence PN2, and a modem with: - an analog to digital converter ADC. Furthermore, said receiver REC comprises synchronizing means SYNC for synchronizing a spread signal SEQ with the despreading sequence PN2.

When receiving a signal SEQ from a base station through the antenna ANT of the User Equipment, i.e. mobile phone, said signal is received at a certain radio carrier frequency, and with a 3dB bandwidth of 270kHz for the GSM standard, for example. The signal SEQ is first processed in the mobile phone via the receiver. More particularly in the receiver there is a need to translate this radio frequency to the baseband frequency of 0Hz in order to be able to demodulate the signal, so that it can be treated by some other components of the mobile phone further on, such as the loudspeakers.

A non-limitative example of a received signal SEQ in the GSM standard is illustrated in Fig.2 in the frequency domain. In the following description, the GSM signal SEQ will be taken as an example.

Said signal SEQ is centered on the GSM carrier center frequency of F0. Often, there are some adjacent carrier frequencies, which can degrade the reception of the desired GSM carrier frequency. The center frequency FI of such an adjacent carrier frequency is also illustrated in the diagram of Fig.2. The difference ΔF between the 2 centers F0 and FI is within the GSM frequency band (900MHz band for example).

The signal SEQ is processed in the mobile phone as follows. At the input of the receiver REC, just after the antenna ANT, there is a low- noise amplifier LNA, which allows a decrease of the noise of the received signal SEQ within the receiver REC

Note that the received signal SEQ is then split into 2 components I and Q, well known to the person skilled in the art, via two quadrature mixers Ml and M2, and that all following steps are made on the 2 components in parallel. But for the sake of simplification, the term signal SEQ will be used instead of I and Q components.

In a first step 1), spreading of the carrier frequency spectrum of said received signal SEQ with a spreading sequence PNl is achieved by the spreading means SPR. This spreading consists in expanding the bandwidth of the GSM carrier frequency by multiplying the data bits of the signal SEQ by a spread spectrum LO. The spread spectrum local oscillator LO, illustrated in Fig.3, is generated by spreading a continuous-wave local oscillator LO via an analog multiplier MO with the spreading sequence PNl. In Fig.3 the spectrum of the LO is shown at multiplier MO output, when further rejection means LPF3 described hereinafter are configured as an all-pass filter. In other words, the spreading sequence PNl injected into the multiplier MO is a square waveform. Hence, at mixers Ml & M2, simultaneous spreading of the GSM signal and downconversion to baseband are performed. Note that said sequence generator PN_SEQ_GEN generates the spreading sequence PNl at 3.84Mchip/sec via a clock PNCLK. But, for the sake of a later demodulation process, said sequence generator PN_SEQ_GEN oversamples its output signal to 4, which has the effect of having a frequency of 15.36MHz.

Note that the spreading sequence PNl can be a Gold or Kasami code family well-known to the person skilled in the art or any other type, such as Walsh codes. It can be noted that as the total GSM operation frequency is 900MHz, when there is a spreading of the received signal SEQ as described above, there is also a spreading of the far adjacent carrier frequencies. In this case, the energy of such adjacent signals is important and can hamper the despreading process described in the description later on. Therefore, it is necessary to get rid of these far adjacent signals. To this end, in a preferred embodiment, the radio frequency RF chip comprises further rejection means LPF3 comprising a low pass filter, which is set at the output of the sequence generator PN_SEQ_GEN. This filter LPF3 permits to suppress the adjacent carrier frequencies of the received signal SEQ, and especially those, which are far from the main desired carrier frequency F0. The received signal SEQ then exhibits a root raised cosine RRC spectral occupancy of 3dB bandwidth equal to 2.3MHz as shown in Fig.4.

Note that there is a crystal of 26Mhz, which is used as a clock reference for the sigma delta synthesizer RF_SIGMA_DELTA, said synthesizer being used to phase- lock a voltage controller NCO producing the cosine wave local oscillator LO.

Note that the spectrum of the PNl sequence is infinite and has a cut-off frequency of 3.84MHz as illustrated in Fig.5. At the output of the quadrature mixers Ml and M2 the spread signal SEQ occupies the bandwidth of the spreading sequence PNl of 3.84Mchip/s in the frequency domain, as can be seen in the Fig.6. In a doted line, one can see an example of the spectrum of the initial received signal SEQ. The signal SEQ now exhibits a spectral occupancy of a typical square wave signal clocked at 3.84MHz, i.e. sin(x)/x amplitude envelope, with zero crossing at N*3.84MHz, N being an integer. Thus, the main carrier frequency F0 has been down-converted to baseband, i.e. centered around 0Hz. However, there are still some DC offsets.

In a second step 2), rejection of the DC offset that remains on said spread carrier frequency spectrum is achieved via a simple DC compensation loop which behaves like a second-order high pass filter of programmable high pass cut-off frequency. These high pass filters HPFl (one for each component I and Q of a signal SEQ) are cascaded with channel filters LPFl, which in this application are used solely to remove any traces or far adjacent carrier frequency components which would be present despite the use of the sharp low pass filter LPF3. The channel filters LPFl have a 3dB cut-off frequency of 2.2MHz. They can be 5^th order Legendre low-pass filters, for example.

Note that the DC offset has two main origins. The first one is the self-mixing between the local oscillator LO and self-mixing of RF carrier frequency as described in the prior art resulting from either LO or RF leakage at the front-end: DC is generated through the mixing of LO with itself, and the RF signal with itself. This is due to the limited amount of isolation between the LO and RF port inherent in an RF IC.

The second one is due to second-order intermodulation performance of the receiver, which generates undesirable spectral components at baseband and a strong DC component. This is due in particular to the mixers of the receiver, which are not linear and which introduce a 2^nd order input intersection point known as IIP2 phenomenon.

This phenomenon induces a DC fluctuation. When the DC offset varies, after the gain amplifiers AGC of the receiver, said DC offset will be amplified. It then implies a clipping of the received signal by the ADC converter, which is a great inconvenience as the initialy received signal SEQ is not recovered correctly. The new spectrum of the signal SEQ after DC offset rejection is illustrated in Fig.7. As can be seen, the DC offset has been filtered. The low cut-off frequency Fi is now 20kHz, whereas the high cut-off frequency Fs is of 2.25MHz. Note that both the low cut-off frequency Fi and the high cut-off frequency Fs are adjustable by programmation.

This rejection has the advantage to be easy to implement. No complex component is needed.

Note that the spreading means SPR has the advantage to allow a good reconstirution of the received signal after DC offset rejection contrary to a usual DC offset loop compensation. Indeed, if one applies a DC offset loop compensation (a simple filter with a resistance and a capacitor) on the GSM signal which has a low bandwidth of 135kHz, a distort signal is sent that is remote from the received signal. This is due to the cut-off frequency of 20kHz of the DC offset loop compensation, which is too high for the GSM bandwidth. Indeed, if one applies a cut-off frequency of 20kHz to a signal having a bandwidth of 13 OkHz, it implies a destruction of said signal, whereas if one applies a cut-off frequency of 20kHz to a signal of bandwidth of 2200kHz, the impact is negligible.

Just after the channel filters LPFl, there is a control of the power of the signal SEQ. Said control permits to keep the power of the signal SEQ constant the power of said signal SEQ is, which is necessary for the further analog to digital converter ADC. Hence, when the power of the signal decreases (for example when the mobile phone is far from the base station) the power is increased again and vice and versa via the automatic gain control AGC.

Note that in a preferred non-limitative embodiment there are two cascades of rejection means HPFl and low-pass filter LPFl with an associated gain control amplifier AGC, for each component I and Q of the spread signal SEQ. It gives a better filtering of the DC offset.

In a third step 3), once the DC offset has been rejected via HPFl means, there is a despreading of the spread signal SEQ in order to recover the initial received signal SEQ. Despreading is achieved by the despreading means DSPR with a despreading sequence PN2. The spreading sequence generator PN_SEQ_GEN generates the despreading sequence PN2.

The despreading means DSPR comprise: - a low-pass filter LPF2,

- a correlator with an integration and dump means I&D.

The correlator permits a measure of similarity between the spread signal SEQ and the despreading sequence PN2. This measure is performed by multiplying the two signals and summing (integration) the results over a defined time window, here over a bit period. The summing is done after a data decision on the multiplication results leading to a value of for example -1, +1.

Note that in analog technique, the integration means can be for example a Legendre low-pass filter with a cut-off frequency of 190KHz.

It can be noted that there is a time propagation of the spread signal SEQ when it is transmitted from the spreading section to the despreading section, said time propagation usually varying from one RF chip to another RF chip, depending on the components used between those two parts, especially depending on the low-pass filters. Therefore, in order to improve the correlation process and to take this time propagation or delay into account, in a preferred embodiment, a synchronization is performed between the despreading sequence PN2 and the spread signal SEQ via synchronization means SYNC.

The synchronization means SYNC comprise a digital delay line DELAY producing a sliding clock S_CLK at 15.36MHz, and a threshold value TH.

The despreading sequence PN2 is fed through the digital delay line DELAY clocked at 4*the chip rate via the clock S_CLK, which results in a % chip delay resolution. The despreading sequence PN2 can then be shifted in ^lΛ chip steps. Note that the despreading sequence PN2 is split and applied to one analog multiplier for each I&Q component of the signal SEQ, as shown in Fig.1.

The shifting, i.e. the despreading sequence PN2 phase is incremented by VA chip, is applied until the despreading sequence PN2 is synchronized or time aligned or in phase with the spread signal SEQ, i.e. an optimum correlation peak is obtained. The maximum number of shifts is equal to the length LGH of the despreading sequence PN2.

When such a synchronization is reached, the sliding clock S_CLK is stopped. No other tracking loop for synchronization is needed.

In detailed manner, at each ^lA chip shift, a dump and integration process is performed via the integration and dump means I&D, which are in a non-limitative embodiment an analog low pass filter, to reconstruct the GSM received signal SEQ in baseband. During the dump process, one looks at the result of the multiplication between each chip of the despreading sequence PN2 and the corresponding chip of the spread sequence SEQ.

Then, integration is performed on the data decision results by the integration and dump means I&D. If this integration is greater than the threshold value TH, for example 4, both signal SEQ and despreading sequence PN2 are described as synchronized and an optimum peak correlation PEAK is obtained.

If no optimum correlation peak is obtained, the sequence PN2 is shifted from YΛ chip and the dump and integration process described above is performed again and so on until an optimum peak is obtained.

Note that just after the delay line DELAY, the despreading sequence PN2 is then fed through the low-pass filter LPF2, as shown in Fig.l, said low-pass filter LPF2 being in a non-limitative embodiment a 5* order Legendre low-pass filter. By doing so, the despreading sequence PN2 suffers exactly the same amount of amplitude&phase distortion as the spread signal SEQ, which is necessary to have a good matching of the spread signal and the despreading sequence. By doing so, since both modulated chips and despreading sequence look alike in both time and frequency domain, the correlation product is optimum and ensures an optimum SNR.

Note that in a non-limitative embodiment, the despreading means DSPR comprise a gain amplifier AGCl at the output of the filter LPF2 in order to adjust the amplitude of the despreading sequence PN2 with the power of the signal received from the mixers Ml and M2. To this end, on each branch of the component I and Q of a received signal SEQ, there is an automatic control loop (not represented) just after the amplifiers AGC, to detect the power of the received signal SEQ. It can be noted that the synchronization described above has the advantage of having a well known time propagation or delay of the spread signal SEQ and is unlikely to vary in time since the signal path consists of electrical transmission lines through a cascade of AGC amplifiers and low-pass filters, the spreading section and despreading section being implemented in a same chip. Therefore, the architecture of the receiver according to the invention as described above, is obviously advantageous compared to a solution where the spreading section would be in the base station and the despreading section in the mobile phone. Thus once time-aligned, no additional timing adjustments are required and no tracking loop is needed, as told before, to maintain the alignment of the despreading sequence PN2 contrary to some other wireless transceivers known as DSSS systems, where such a tracking loop is necessary due to the nature of the ether through which the carrier of the received signal SEQ is transmitted and received: multipath fading, shadowing and other propagation effects contribute to not only constantly rotating the phase of the carrier but also to variable propagation delays.

As no tracking loop is needed in the receiver according to the invention, this considerably simplifies the despreading section and results in two possible despreading implementations. The first one is an analog despreading within the RF chip as stated above and the second one is a despreading in the digital domain.

In the embodiment of the digital despreading, the whole process described above for the analog embodiment, can also be entirely performed by a baseband digital signal chip comprised in the modem and is also called baseband chip. The I and Q components then require an adequate analog to digital converter ADC to sample the 2.2MHz wide (3dB bandwidth) analog signal SEQ. Sampling is performed with a 4xchip rate clock.

Note that further rejection is achieved via the integration means I with a Legendre filter for rejecting adjacent carrier frequencies that could remain in the spectrum of the despread signal SEQ and which are closed to the carrier frequency F0.

Finally, the result of the despreading is that the bandwidth of the received signal SEQ has been compressed from 3.84Mchip/sec to 135kHz and the desired carrier frequency F0 has been down-converted to the baseband 0Hz. After the integration and dump I&D, the initial received signal SEQ is recovered as shown in Fig.8.

The following step) is an analog to digital conversion via the converter ADC in order to permit a demodulation, by a baseband chip following the RF chip, of the signal SEQ obtained. The demodulation permits the listening of a message by the user of the mobile on the headphone for example.

Note that the architecture of the RF chip as stated in the foregoing has the advantage of being completely transparent to the following baseband chip. Hence, standard baseband chips can be used with this RF architecture, with no modifications.

Hence, the receiver according to the invention has the advantage of resolving the problems of DC offset loop compensation on narrowband signals by using techniques used for wideband signals leading to a simple solution with low power consumption. It is to be understood that the present invention is not limited to the aforementioned embodiments and variations and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims. In this respect, the following closing remarks are made.

It is to be understood that the present invention can also be applied to other receivers where DC offset rejection is needed.

It is to be understood that the present invention is not limited to the aforementioned GSM application. It can be used within any other standard application such as Bluetooth, ZIGBEE. It is to be understood that the method according to the present invention is not limited to the aforementioned implementation.

There are numerous ways of implementing functions of the method according to the invention by means of items of hardware or software, or both, provided that a single item of hardware or software can carry out several functions. It does not exclude that an assembly of items of hardware or software or both carry out a function, thus forming a single function without modifying the method for processing a signal in accordance with the invention. Said hardware or software items can be implemented in several manners, such as by means of wired electronic circuits or by means of an integrated circuit that is suitably programmed, respectively.

Any reference sign in the following claims should not be construed as limiting the claim. It will be obvious that the use of the verb "to comprise" and its conjugations do not exclude the presence of any other steps or elements besides those defined in any claim. The article "a" or "an" preceding an element or step does not exclude the presence of a plurality of such elements or steps.

Claims

1. A receiver for processing a received signal (SEQ), said signal (SEQ) having a bandwidth, characterized in that it comprises:

- spreading means (SPR) for spreading the bandwidth of said signal (SEQ) with a spreading sequence (PNl), - first rejection means (HPFl) for rejecting DC offset on said spread signal

(SEQ), and

- despreading means (DSPR) for despreading said spread signal (SEQ) with a despreading sequence (PN2).

2. A receiver for processing a received signal (SEQ) as claimed in claim 1, characterized in that it further comprises synchronization means (SYNC) for synchronizing said spread signal (SEQ) with a despreading sequence (PN2).

3. A receiver for processing a received signal (SEQ) as claimed in claim 2, characterized in that it the synchronization means (SYNC) comprise a delay line

(DELAY), a sliding clock (S_CLK) and a threshold (TH).

4. A receiver for processing a received signal (SEQ) as claimed in claim 1, characterized in that the first rejection means (HPFl) are high-pass filters.

5. A receiver for processing a received signal (SEQ) as claimed in claim 1, characterized in that it further comprises further rejection means (LPF3) for suppression of the carrier adjacent frequencies of the received signal (SEQ).

6. A method for processing a received signal (SEQ), said signal (SEQ) having a carrier frequency spectrum, characterized in that it comprises the steps of:

- spreading the bandwidth of said signal (SEQ) with a spreading sequence (PNl),

- rejecting DC offset on said spread signal (SEQ), and - despreading said spread signal (SEQ) with a despreading sequence (PN2).

7. A method for processing a received signal (SEQ) as claimed in claim 6, characterized in that it further comprises the step of synchronizing said spread signal (SEQ) with a despreading sequence (PN2).

8. A method for processing a received signal (SEQ) as claimed in claim 6, characterized in that it further comprises the step of suppressing the carrier- adjacent frequencies of the received signal (SEQ).