WO2004047184A2 - Structure semi-conductrice convenant pour la realisation d'une cellule solaire - Google Patents

Structure semi-conductrice convenant pour la realisation d'une cellule solaire Download PDF

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WO2004047184A2
WO2004047184A2 PCT/US2002/014996 US0214996W WO2004047184A2 WO 2004047184 A2 WO2004047184 A2 WO 2004047184A2 US 0214996 W US0214996 W US 0214996W WO 2004047184 A2 WO2004047184 A2 WO 2004047184A2
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layer
monocrystalline
semiconductor
accommodating buffer
substrate
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PCT/US2002/014996
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WO2004047184A3 (fr
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Barbara Foley Barenburg
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Motorola, Inc.
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Publication of WO2004047184A3 publication Critical patent/WO2004047184A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0693—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells the devices including, apart from doping material or other impurities, only AIIIBV compounds, e.g. GaAs or InP solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/544—Solar cells from Group III-V materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This invention relates generally to semiconductor structures and devices and to a method for their fabrication, and more specifically to solar cell devices including semiconductor structures and to methods of forming the structures and devices.
  • Solar cells generally include a p-n junction formed of adjacent layers or regions of a semiconductor structure.
  • a solar cell may include a p-n junction formed of oppositely doped regions of a semiconductor substrate such as silicon or adjacent layers of oppositely doped semiconductor layers such as GaAs and AlGaAs.
  • An efficiency of a solar cell is typically about 10-20% for a single p-n junction exposed to direct sunlight.
  • the efficiency of a solar cell generally depends on the wavelength(s) of incident light and the band gap of the semiconductor material: photons having less energy than the bandgap energy of the semiconductor material will not be converted to current, whereas incident photons having an energy equal to or greater than the bandgap of the material will be absorbed by the material and the photon energy will be converted to electricity.
  • the efficiency of a solar cell can be increased by creating additional p-n junctions designed to convert light of varying wavelengths or energy into current.
  • a structure may be formed including multiple, adjacent p-n junctions, in which the top most p-n junction absorbs the high energy photons and the underlying p-n junctions are designed to convert progressively lower energy photons into electricity.
  • adding additional p-n junctions may increase the efficiency of the solar cell, light of various wavelength may not be efficiently absorbed by any of the semiconductor layers.
  • the efficiency of solar cells is also generally a function of defect density of the semiconductor material comprising the cell. The efficiency of the cell generally decreases as the number of defects in the semiconductor material increases.
  • semiconductor structures including multiple layers of oppositely-doped, low defect density material are desirable to form high-efficiency solar cells.
  • dyes designed to convert incident light to light of wavelengths more readily absorbed by the solar cell have been added to a surface of a solar cell.
  • such dyes often conglomerate on the surface of the solar cell, reducing any desired effect of the dyes.
  • improved solar cell structures including fluorescent dye and methods for forming the structures are desired.
  • a solar cell device could advantageously be fabricated using that film.
  • thin films of high quality monocrystalline material could be realized beginning with a bulk wafer such as a silicon wafer, an integrated device structure could be achieved that took advantage of the best properties of both the silicon and the high quality monocrystalline material layers.
  • FIGS. 1, 2, 3, and 4 illustrate schematically, in cross section, device structures in accordance with various embodiments of the invention
  • FIG. 5 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer
  • FIG. 6 illustrates a high resolution Transmission Electron Micrograph of a structure including a monocrystalline accommodating buffer layer
  • FIG. 7 illustrates an x-ray diffraction spectrum of a structure including a monocrystalline accommodating buffer layer
  • FIG. 8 illustrates a high resolution Transmission Electron Micrograph of a structure including an amorphous oxide layer
  • FIG. 9 illustrates an x-ray diffraction spectrum of a structure including an amorphous oxide layer
  • FIGS. 10A-10D illustrate schematically, in cross-section, the formation of a device structure in accordance with another embodiment of the invention.
  • FIGS. 11 A-l ID illustrate a probable molecular bonding structure of the device structures illustrated in FIGS. 10A-10D
  • FIG. 12 illustrates a device structure including a solar cell in accordance with the present invention
  • FIG. 13 illustrates a device structure in accordance with yet another embodiment of the invention.
  • FIG. 14 illustrates schematically, in cross section, a device structure in accordance with another embodiment of the invention.
  • FIG. 15 illustrates a device structure including another embodiment of a solar cell in accordance with the present invention.
  • FIG. 16 illustrates a device structure in accordance with yet another embodiment of the invention.
  • FIG. 17 is a flow chart of a process for fabricating a solar cell structure in accordance with the processes described.
  • FIG. 1 illustrates schematically, in cross section, a portion of a semiconductor structure 100, suitable for forming a solar cell, in accordance with an embodiment of the invention.
  • Semiconductor structure 100 includes a monocrystalline substrate 102, an accommodating buffer layer 104 comprising a monocrystalline material, a monocrystalline p-type semiconductor layer 106, a monocrystalline n-type semiconductor layer 108, and a dye layer 110, which converts light energy of one level to an energy of a second level that is more readily converted to electricity by solar cells formed using structure 100.
  • the term "monocrystalline" shall have the meaning commonly used within the semiconductor industry.
  • the term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.
  • structure 100 also includes an amorphous intermediate layer 112 positioned between substrate 102 and accommodating buffer layer 104.
  • Structure 100 may also include a template layer 114 between the accommodating buffer layer and layer 106.
  • the template layer helps to initiate the growth of the monocrystalline material layer on the accommodating buffer layer.
  • the amorphous intermediate layer helps to relieve the strain in the accommodating buffer layer and by doing so, aids in the growth of a high crystalline quality accommodating buffer layer.
  • Substrate 102 is a monocrystalline semiconductor or compound semiconductor wafer, preferably of large diameter.
  • the wafer can be of, for example, a material from Group IV of the periodic table.
  • Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like.
  • substrate 102 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry.
  • Accommodating buffer layer 104 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate.
  • amorphous intermediate layer 112 is grown on substrate 102 at the interface between substrate 102 and the growing accommodating buffer layer by the oxidation of substrate 102 during the growth of layer 104.
  • the amorphous intermediate layer serves to relieve strain that might otherwise occur in the monocrystalline accommodating buffer layer as a result of differences in the lattice constants of the substrate and the buffer layer.
  • lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by the amorphous intermediate layer, the strain may cause defects in the crystalline structure of the accommodating buffer layer. Defects in the crystalline structure of the accommodating buffer layer, in turn, would make it difficult to achieve a high quality crystalline structure in monocrystalline material layers 106 and 108.
  • Accommodating buffer layer 104 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying substrate and with the overlying material layer.
  • the material could be an oxide or nitride having a lattice structure closely matched to the substrate and to the subsequently applied monocrystalline material layer.
  • Materials that are suitable for the accommodating buffer layer include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for the accommodating buffer layer.
  • metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates
  • the intrinsic insulator oxides and nitrides may be suitably doped to form conducting accommodating buffer layers as desired.
  • the accommodating buffer materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitrides may include three or more different metallic elements.
  • Amorphous interface layer 112 is preferably an oxide formed by the oxidation of the surface of substrate 102, and more preferably is composed of a silicon oxide.
  • the thickness of layer 112 is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate 102 and accommodating buffer layer 104. Typically, layer 112 has a thickness in the range of approximately 0.5-5 nm.
  • the material for monocrystalline material layers 106 and 108 can be selected, as desired, for a particular structure or application.
  • the monocrystalline material of layers 106 and 108 may comprise compound semiconductor material which can be selected, as needed for a particular semiconductor structure, from any of the Group ⁇ iA and VA elements (HT-V semiconductor compounds), mixed UI-V compounds, Group II(A or B) and VIA elements (II-VI semiconductor compounds), and mixed II-VI compounds.
  • Examples include gallium arsenide (GaAs), gallium indium arsenide (GalnAs), gallium aluminum arsenide (GaAlAs), indium phosphide (InP), gallium indium phosphide (GalnP), aluminum indium phosphide (AllnP), indium gallium arsenic phosphide (InGaAsP), and the like.
  • Layers 106 and 108 may be separately grown layers of semiconductors material, with a suitable dopant added to one or both of the layers to form the p-type and n-type materials, or layers 106 and 108 may be formed of a single semiconductor layer, which is suitably doped to form layers 106 and 108.
  • template 114 Appropriate materials for template 114 are discussed below. Suitable template materials chemically bond to the surface of the accommodating buffer layer 104 at selected sites and provide sites for the nucleation of the epitaxial growth of monocrystalline material layer 106. When used, template layer 114 has a thickness ranging from about 1 to about 10 monolayers. As discussed in greater detail below, template layer 114 may also include a surfactant to further relieve any strain that might result from any lattice mismatch between layer 114 and subsequently grown layer 106.
  • Layer 110 includes dye material that absorbs light energy of certain wavelength(s) and converts the energy into light of second wavelength(s).
  • layer 110 may be used to increase an efficiency of a solar cell by absorbing energy of light, which is not otherwise efficiently absorbed by the solar cell, and converting the energy into light that is more efficiently absorbed by the cell.
  • the dye includes one or more fluorophores, which convert incident light by means of fluorescence. Other means for converting the energy include resonance energy transfer and electron transfer.
  • fluorophores include B, R- Phycoerythrin, erythrosin, and fluorein manufactured by Molecular Probes of Eugene Oregon.
  • biomolecules such as carbohydrates, amino acids, DNA, and/or proteins are employed to reduce conglomeration of the dye (e.g., fluorophore) material.
  • the biomolecule is attached to the surface of the semiconductor material using spin coating methods, and the fluorophore is selected to attach to a portion of the biomaterial.
  • the fluorescent material may be attached to the biomolecule and the combination of the biomolecule and the fluorescent material may be applied to a surface using, for example, spin coating technology.
  • FIG. 2 schematically illustrates, in cross section, a portion of a semiconductor structure 200 in accordance with another exemplary embodiment of the invention.
  • Structure 200 is similar to structure 100, except that structure 200 includes an amorphous layer 202, rather than accommodating buffer layer 104 and amorphous interface layer 112.
  • amorphous layer 202 may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above. Monocrystalline layer 106 is then formed (by epitaxial growth) overlying the monocrystalline accommodating buffer layer. The accommodating buffer layer is then exposed to an anneal process to convert the monocrystalline accommodating buffer layer to an amorphous layer. Amorphous layer 202 formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate. Thus, layer 202 may comprise one or two amorphous layers.
  • amorphous layer 202 between substrate 102 and monocrystalline layer 106 relieves stresses between layers 102 and 106 and provides a true compliant substrate for subsequent processing—e.g., monocrystalline material layer 108 formation.
  • the anneal process may be performed after the formation of layer 108.
  • a thin layer of monocrystalline material e.g., material comprising layer 106 may be epitaxially grown over the accommodating buffer layer, and this thin film may serve as an anneal cap during layer 202 formation and as a seed layer for additional material growth for layer 106 formation.
  • FIG. 3 illustrates a semiconductor structure 300 in accordance with yet another embodiment of the invention.
  • Structure 300 is similar to structure 200, except that structure 300 includes additional monocrystalline material layers which form additional p-n junctions. The formation of additional p-n junctions of materials of different bandgap energies allows absorption of light over a greater range of wavelengths. Thus, structure 300 may operate more efficiently when exposed to a light source of multiple wavelengths, such as the sun, compared to structures 100 and 200.
  • Structure 300 includes a substrate 102, a buffer layer 202, a template layer 114, and a dye layer 110, as described above.
  • structure 300 includes a p+ GaAs layer 302, an n- GalnP layer 304, a p- GaAs layer 306, an n- GaAs layer 308, an n- GalnP layer 310, an n++ GaAs layer 312, a p++ GaAs layer 314, a p- GalnP layer 316, a p- GalnP layer 318, an n- GalnP layer 320, an n- AllnP layer 322, and an n++ GaAs layer 324.
  • a structure including layers 302-324 (exclusive of layers 102, 202, 114, and 110) is described in greater detail in "29.5% Efficient GalnP/GaAs Tandem Solar Cell", Bertness et al., Appl. Phys. Lett., 85 (8), 22 Aug. 1994, the content of which is hereby incorporated by reference.
  • FIG. 4 illustrates a structure 400 in accordance with a further embodiment of the invention.
  • Structure 400 is similar to structure 200, except that structure 400 includes an additional p-n junction 402 formed using substrate 102 and includes an additional back-side conductive material layer 404.
  • Additional p-n junction 402 is configured to convert photons to electricity.
  • p-n structure 402 is formed of material different from material used to form layers 106 and 108.
  • junction 402 can convert photons (e.g., lower energy photons) that pass through layers 106 and 108.
  • the thickness of layers 106 and 108 is less than the thickness of layers 406 and 408.
  • Structure 400 preferably includes a conductive accommodating buffer layer 202.
  • a conductive accommodating buffer layer 202 As noted above, some of the materials suitable to form accommodating buffer layer 202 are conductive. Otherwise insulating buffer layer material may also be used to form layer 202, if suitably doped (e.g., dopant levels at 10 to 10 atoms per cubic centimeter). Conducting accommodating buffer layer facilitates the transfer of electrons through the various layers of structure 400 between layer 108 and layer 404.
  • Conductive material layer 404 may comprise any conductive material.
  • layer 404 includes a metal such as gold, tin, or a combination of chromium and gold.
  • any suitable number of p-n junctions may be formed above layer 202 in accordance with the present invention.
  • layers 302-324, illustrated in FIG. 3 may be formed above layer 202 and p-n junction 402.
  • monocrystalline substrate 102 is a silicon substrate oriented in the (100) direction.
  • the silicon substrate can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 75-300 mm.
  • accommodating buffer layer 104 is a monocrystalline layer of Sr z Ba 1-z TiO 3 where z ranges from 0 to 1 and the amorphous intermediate layer is a layer of silicon oxide (SiO x ) formed at the interface between the silicon substrate and the accommodating buffer layer. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formed layers 106 and 108.
  • the accommodating buffer layer can have a thickness of about 2 to about 100 nanometers (nm) and preferably has a thickness of about 5 nm. In general, it is desired to have an accommodating buffer layer thick enough to isolate the monocrystalline material layer 26 from the substrate to obtain the desired electrical and optical properties. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed.
  • the amorphous intermediate layer of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1 to 2 nm.
  • monocrystalline material layer 106 is a compound semiconductor layer of gallium arsenide having a thickness of about 1 nm to about 100 micrometers ( ⁇ m) and preferably a thickness of about 0.5 ⁇ m to 10 ⁇ m and layer 108 is a layer of GalnP having a thickness of about 1 nm to about 100 ⁇ m and preferably a thickness of about 0.1 ⁇ m to 4 ⁇ m.
  • a template layer is formed by capping the oxide layer.
  • the template layer is preferably 1-10 monolayers of Ti-As, Sr-O-As, Sr-Ga-O, or Sr-Al-O.
  • 1 -2 monolayers of Ti-As or Sr-Ga-O have been illustrated to successfully grow GaAs layers.
  • GalnP layer 108 may be grown overlying GaAs layer 106 without an additional template.
  • Layer 110 is formed over layer 108 by attaching biomolecules such as DNA, having fluorescent material attached thereto, to a surface of layer 108.
  • monocrystalline substrate 102 is a silicon substrate as described above.
  • the accommodating buffer layer is a monocrystalline oxide of strontium or barium zirconate or hafnate in a cubic or orthorhombic phase with an amorphous intermediate layer of silicon oxide formed at the interface between the silicon substrate and the accommodating buffer layer.
  • the accommodating buffer layer can have a thickness of about 2-100 nm and preferably has a thickness of at least 5 nm to ensure adequate crystalline and surface quality and is formed of a monocrystalline SrZrO 3 , BaZrO 3 , SrHfO 3 , BaSnO 3 or BaHfO 3 .
  • a monocrystalline oxide layer of BaZrO 3 can grow at a temperature of about 700 °C.
  • the lattice structure of the resulting crystalline oxide exhibits a 45 degree rotation with respect to the substrate silicon lattice structure.
  • an accommodating buffer layer formed of these zirconate or hafnate materials is suitable for the growth of a monocrystalline material layer which comprises compound semiconductor materials in the indium phosphide (InP) system.
  • the compound semiconductor layers 106 and 108 can be, for example, p-doped and n-doped indium phosphide (InP), indium gallium arsenide (InGaAs), aluminum indium arsenide, (AlInAs), or aluminum gallium indium arsenic phosphide (AlGalnAsP) layers, having a thickness of about 1.0 nm to 10 ⁇ m.
  • a suitable template for this structure is 1 - 10 monolayers of zirconium-arsenic (Zr-As), zirconium-phosphorus (Zr-P), hafnium- arsenic (Hf-As), hafnium-phosphorus (Hf-P), strontium-oxygen-arsenic (Sr-O-As), strontium-oxygen-phosphorus (Sr-O-P), barium-oxygen-arsenic (Ba-O-As), indium- strontium-oxygen (In-Sr-O), or barium-oxygen-phosphorus (Ba-O-P), and preferably 1- 2 monolayers of one of these materials.
  • the surface is terminated with 1-2 monolayers of zirconium followed by deposition of 1-2 monolayers of arsenic to form a Zr-As template.
  • a monocrystalline layer of the compound semiconductor material from the indium phosphide system is then grown on the template layer.
  • the resulting lattice structure of the compound semiconductor material exhibits a 45 degree rotation with respect to the accommodating buffer layer lattice structure and a lattice mismatch to (100) InP of less than 2.5%, and preferably less than about 1.0%.
  • Amorphous layer 202 is an amorphous oxide layer which is suitably formed of a combination of amorphous intermediate layer materials (e.g., layer 112 materials as described above) and accommodating buffer layer materials (e.g., layer 104 materials as described above).
  • amorphous layer 202 may include a combination of SiO x and Sr z Ba 1-z TiO (where z ranges from 0 to l),which combine or mix, at least partially, during an anneal process to form amorphous oxide layer 202.
  • amorphous layer 202 may vary from application to application and may depend on such factors as desired insulating properties of layer 202, type of monocrystalline material comprising layers 106 and 108, and the like. In accordance with one exemplary aspect of the present embodiment, layer 202 thickness is about 2 nm to about 100 nm, preferably about 2-10 nm, and more preferably about 5-6 nm. Example 4
  • Substrate material 102, template layer 114, and layer 110 may be the same as those described above in connection with example 1.
  • structure 300 is similar to structure 200, except that structure 300 includes additional p-n junctions, configured to increase an efficiency of a solar cell manufactured using structure 300.
  • layer 302 is formed of p+ GaAs epitaxially grown overlying template 114 as described above.
  • Layer 302 is formed of p+ GaAs, which is about 150 to about 250 nm and preferably about 200 nm thick;
  • layer 304 is a layer of n- GalnP, which is preferably about 50 to about 80 and preferably about 70 nm thick;
  • layer 306 is a p- GaAs layer, which is about 3000 to about 4000 nm and preferably about 3500 nm thick;
  • layer 308 is an n- GaAs layer, which is about 80 to about 120 nm and preferably about 100 nm thick;
  • layer 310 is an n- GalnP layer, which is about 80 to about 120 nm and preferably about 100 nm thick;
  • layer 312 is an n++ GaAs layer, which is about 8 to about 12 and preferably about 11 nm thick;
  • layer 314 us a p++ GaAs layer, which is about 8 to about 12 and preferably about 11 nm thick;
  • layer 316 is a p-
  • structure 400 is similar to structure 200, except structure 400 includes a p-n junction 402 formed within substrate 102 and structure 400 includes a layer 404 of conductive material.
  • junction 402 is formed by epitaxially growing about 250 nm to about 100 ⁇ m thick n- type layer 406 overlying a p+ silicon substrate 408.
  • conductive layer 404 is a metal layer and is about 0.1 nm to about 100 nm thick.
  • substrate 102 is a monocrystalline substrate such as a monocrystalline silicon, germanium, or gallium arsenide substrate.
  • the crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation.
  • accommodating buffer layer 104 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation.
  • the lattice constants of the accommodating buffer layer and the monocrystalline substrate must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved.
  • the terms "substantially equal” and “substantially matched” mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer.
  • FIG. 4 illustrates graphically the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal.
  • Curve 502 illustrates the boundary of high crystalline quality material. The area to the right of curve 502 represents layers that have a large number of defects. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved.
  • substrate 102 is a (100) or (111) oriented monocrystalline silicon wafer and accommodating buffer layer 104 is a layer of strontium barium titanate.
  • Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material by 45° with respect to the crystal orientation of the silicon substrate wafer.
  • the inclusion in the structure of amorphous interface layer 112, a silicon oxide layer in this example, if it is of sufficient thickness, serves to reduce strain in the titanate monocrystalline layer that might result from any mismatch in the lattice constants of the host silicon wafer and the grown titanate layer.
  • a high quality, thick, monocrystalline titanate layer is achievable.
  • layer 106 (or layer 302) is a layer of epitaxially grown monocrystalline material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation.
  • the lattice constant of layer 106 differs from the lattice constant of substrate 102.
  • the accommodating buffer layer must be of high crystalline quality.
  • substantial matching between the crystal lattice constant of the host crystal, in this case, the monocrystalline accommodating buffer layer, and the grown crystal is desired.
  • this substantial matching of lattice constants is achieved as a result of rotation of the crystal orientation of the grown crystal with respect to the orientation of the host crystal.
  • the grown crystal is gallium arsenide, aluminum gallium arsenide, zinc selenide, or zinc sulfur selenide and the accommodating buffer layer is monocrystalline Sr x Ba ⁇ -x TiO 3
  • substantial matching of crystal lattice constants of the two materials is achieved, wherein the crystal orientation of the grown layer is rotated by 45° with respect to the orientation of the host monocrystalline oxide.
  • the host material is a strontium or barium zirconate or a strontium or barium hafnate or barium tin oxide and the compound semiconductor layer is indium phosphide or gallium indium arsenide or aluminum indium arsenide
  • substantial matching of crystal lattice constants can be achieved by rotating the orientation of the grown crystal layer by 45° with respect to the host oxide crystal.
  • a crystalline semiconductor buffer layer between the host oxide and the grown monocrystalline material layer can be used to reduce strain in the grown monocrystalline material layer that might result from small differences in lattice constants. Better crystalline quality in the grown monocrystalline material layer can thereby be achieved.
  • layers formed above layer 106 are formed by epitaxially growing material that is closely lattice matched to the underlying layer to allow high quality epitaxial growth of the film.
  • the following example illustrates a process, in accordance with one embodiment of the invention, for fabricating a semiconductor structure such as the structures depicted in FIGS. 1 - 4.
  • the process starts by providing a monocrystalline semiconductor substrate comprising silicon or germanium.
  • the semiconductor substrate is a silicon wafer having a (100) orientation.
  • the substrate is preferably oriented on axis or, at most, about 4° off axis.
  • At least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures.
  • the term "bare" in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material.
  • bare silicon is highly reactive and readily forms a native oxide.
  • the term "bare" is intended to encompass such a native oxide.
  • a thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process in accordance with the invention.
  • the native oxide layer In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline substrate, the native oxide layer must first be removed to expose the crystalline structure of the underlying substrate. The following process is preferably carried out by molecular beam epitaxy (MBE), although other epitaxial processes may also be used in accordance with the present invention.
  • MBE molecular beam epitaxy
  • the native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkaline earth metals or combinations of alkaline earth metals in an MBE apparatus.
  • the substrate is then heated to a temperature of about 750 °C to cause the strontium to react with the native silicon oxide layer.
  • the strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface.
  • the resultant surface which exhibits an ordered 2x1 structure, includes strontium, oxygen, and silicon.
  • the ordered 2x1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide.
  • the template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer.
  • the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkaline earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750 °C. At this temperature a solid state reaction takes place between the strontium oxide and the native silicon oxide causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer.
  • an alkaline earth metal oxide such as strontium oxide, strontium barium oxide, or barium oxide
  • the substrate is cooled to a temperature in the range of about 200-800 °C and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy.
  • the MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources.
  • the ratio of strontium and titanium is approximately 1:1.
  • the partial pressure of oxygen is initially set at a minimum value to grow stoichiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value.
  • the overpressure of oxygen causes the growth of an amorphous silicon oxide layer at the interface between the underlying substrate and the growing strontium titanate layer.
  • the growth of the silicon oxide layer results from the diffusion of oxygen through the growing strontium titanate layer to the interface where the oxygen reacts with silicon at the surface of the underlying substrate.
  • the strontium titanate grows as an ordered (100) monocrystal with the (100) crystalline orientation rotated by 45° with respect to the underlying substrate. Strain that otherwise might exist in the strontium titanate layer because of the small mismatch in lattice constant between the silicon substrate and the growing crystal is relieved in the amorphous silicon oxide i ntermedi ate 1 ayer .
  • the monocrystalline strontium titanate is capped by a template layer that is conducive to the subsequent growth of an epitaxial layer of a desired monocrystalline material.
  • the MBE growth of the strontium titanate monocrystalline layer can be capped by terminating the growth with 1-2 monolayers of titanium, 1 -2 monolayers of titanium-oxygen or with 1 -2 monolayers of strontium- oxygen.
  • arsenic is deposited to form a Ti-As bond, a Ti-O-As bond or a Sr-O-As.
  • gallium arsenide monocrystalline layer is subsequently introduced to the reaction with the arsenic and gallium arsenide forms.
  • gallium can be deposited on the capping layer to form a Sr-O-Ga bond, and arsenic is subsequently introduced with the gallium to form the GaAs.
  • subsequent semiconductor layers can be epitaxially formed using an MBE process in a similar manner.
  • layer 110 is formed by attaching biomolecules such as DNA and fluorescent material to a surface of a semiconductor layer.
  • biomolecules and fluorescent material may be suitably attached using spin-coat technology.
  • the fluorescent material is attached to the biomolecule, and the combination of the biomolecule and the fluorescent material are attached during a single spin-on coat process.
  • FIG. 6 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with one embodiment of the present invention.
  • Single crystal SrTiO accommodating buffer layer 104 was grown epitaxially on silicon substrate 102. During this growth process, amorphous interfacial layer 112 is formed which relieves strain due to lattice mismatch.
  • GaAs compound semiconductor layer 106 was then grown epitaxially using template layer 114.
  • FIG. 7 illustrates an x-ray diffraction spectrum taken on a structure including GaAs monocrystalline layer 06 comprising GaAs grown on silicon substrate 102 using accommodating buffer layer 104.
  • the peaks in the spectrum indicate that both the accommodating buffer layer 104 and GaAs compound semiconductor layer 106 are single crystal and (100) orientated.
  • Structure 200 may be formed by growing an accommodating buffer layer, forming an amorphous oxide layer over substrate 102, and growing semiconductor layer 106 over the accommodating buffer layer, as described above.
  • the accommodating buffer layer and the amorphous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amorphous, thereby forming an amorphous layer such that the combination of the amorphous oxide layer and the now amorphous accommodating buffer layer form a single amorphous oxide layer 202.
  • Layer 108 is then subsequently grown over layer 106.
  • the anneal process may be carried out subsequent to growth of layer 108.
  • layer 202 is formed by exposing substrate 102, the accommodating buffer layer, the amorphous oxide layer, and monocrystalline layer 106 to a rapid thermal anneal process with a peak temperature of about 700 °C to about 1000 °C and a process time of about 5 seconds to about 10 minutes.
  • a rapid thermal anneal process with a peak temperature of about 700 °C to about 1000 °C and a process time of about 5 seconds to about 10 minutes.
  • suitable anneal processes may be employed to convert the accommodating buffer layer to an amorphous layer in accordance with the present invention.
  • laser annealing, electron beam annealing, or "conventional" thermal annealing processes may be used to form layer 202.
  • an overpressure of one or more constituents of layer 106 may be required to prevent degradation of layer 106 during the anneal process.
  • the anneal environment preferably includes an overpressure of arsenic to mitigate degradation of layer 106.
  • FIG. 8 is a high resolution TEM of semiconductor material manufactured in accordance with the embodiment of the invention illustrated in FIG. 2.
  • a single crystal SrTiO 3 accommodating buffer layer was grown epitaxially on silicon substrate 102.
  • an amorphous interfacial layer forms as described above.
  • layer 106 comprising a compound semiconductor layer of GaAs is formed above the accommodating buffer layer and the accommodating buffer layer is exposed to an anneal process to form amorphous oxide layer 202.
  • FIG. 9 illustrates an x-ray diffraction spectrum taken on a structure including monocrystalline layer 106 comprising a GaAs compound semiconductor layer and amorphous oxide layer 202 formed on silicon substrate 102.
  • the peaks in the spectmm indicate that GaAs compound semiconductor layer 106 is single crystal and (100) orientated and the lack of peaks around 40 to 50 degrees indicates that layer 202 is amorphous.
  • the process described above illustrates a process for forming a semiconductor structure including a silicon substrate, an overlying oxide layer, and a monocrystalline material layer comprising a gallium arsenide compound semiconductor layer by the process of molecular beam epitaxy.
  • the process can also be carried out by the process of chemical vapor deposition (CVD), metal organic chemical vapor deposition
  • MOCVD migration enhanced epitaxy
  • MEE migration enhanced epitaxy
  • ALE atomic layer epitaxy
  • PVD physical vapor deposition
  • CSSD chemical solution deposition
  • PLD pulsed laser deposition
  • alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown.
  • monocrystalline material layers comprising other HI-V and II-VI monocrystalline compound semiconductors can be deposited overlying the monocrystalline oxide accommodating buffer layer.
  • monocrystalline material layer and monocrystalline oxide accommodating buffer layer uses an appropriate template for initiating the growth of the monocrystalline material layer.
  • the accommodating buffer layer is an alkaline earth metal zirconate
  • the oxide can be capped by a thin layer of zirconium.
  • the deposition of zirconium can be followed by the deposition of arsenic or phosphorus to react with the zirconium as a precursor to depositing indium gallium arsenide, indium aluminum arsenide, or indium phosphide respectively.
  • the oxide layer can be capped by a thin layer of hafnium.
  • the deposition of hafnium is followed by the deposition of arsenic or phosphorous to react with the hafnium as a precursor to the growth of an indium gallium arsenide, indium aluminum arsenide, or indium phosphide layer, respectively.
  • strontium titanate can be capped with a layer of strontium or strontium and oxygen
  • barium titanate can be capped with a layer of barium or barium and oxygen.
  • Each of these depositions can be followed by the deposition of arsenic or phosphorus to react with the capping material to form a template for the deposition of a monocrystalline material layer comprising compound semiconductors such as indium gallium arsenide, indium aluminum arsenide, or indium phosphide.
  • FIGS. 10A-10D The formation of a device structure in accordance with another embodiment of the invention is illustrated schematically in cross-section in FIGS. 10A-10D.
  • this embodiment of the invention involves the process of forming a compliant substrate utilizing the epitaxial growth of a single crystal of accommodating buffer layer 104 previously described with reference to FIG. 1 and amorphous layer 202, previously described with reference to FIG. 2, and the formation of a template layer 114.
  • the embodiment illustrated in FIGS. 10A-10D utilizes a template that includes a surfactant to facilitate layer-by- layer monocrystalline material growth.
  • an amorphous intermediate layer 112 is grown on substrate 102 at the interface between substrate 102 and a growing accommodating buffer layer 104, which is preferably a monocrystalline oxide layer, by the oxidation of substrate 102 during the growth of layer 104, as described above.
  • Layer 104 is grown with a strontium terminated surface represented in FIG. 10A by hatched line 1002 which is followed by the addition of a template layer 1004 which includes a surfactant layer 1006 and capping layer 1008 as illustrated in FIGS. 10B and 1 OC.
  • Surfactant layer 1006 may comprise, but is not limited to, elements such as Al, In and Ga, but will be dependent upon the composition of layer 104 and the overlying layer of monocrystalline material for optimal results.
  • aluminum is used for surfactant layer 1006 and functions to modify the surface and surface energy of layer 104.
  • surfactant layer 1006 is epitaxially grown, to a thickness of one quarter to two monolayers, over layer 104 as illustrated in FIG. 10B by way of molecular beam epitaxy, although other epitaxial processes may also be performed including CVD, MOCVD, MEE, ALE, PVD, CSD, PLD, or the like.
  • Surfactant layer 1006 is then exposed to a Group V element such as arsenic, for example, to form capping layer 1008 as illustrated in FIG. IOC.
  • Surfactant layer 1006 may be exposed to a number of materials to create capping layer 1008 such as elements which include, but are not limited to, As, P, Sb and N.
  • Surfactant layer 1006 and capping layer 1008 combine to form template layer 1004.
  • Monocrystalline material layer 106 which in this example is a compound semiconductor such as GaAs, is then deposited via MBE, CVD, MOCVD, MEE, ALE, PVD, CSD, PLD, and the like, to form the final structure illustrated in FIG. 10D.
  • FIGS. 11 A-l ID illustrate possible molecular bond structures for a specific example of a compound semiconductor structure formed in accordance with the embodiment of the invention illustrated in FIGS. 10A-10D. More specifically, FIGS. 11A-1 ID illustrate the growth of GaAs (layer 106) on the strontium terminated surface of a strontium titanate monocrystalline oxide (layer 104) using a surfactant containing template (layer 1004).
  • FIG. 1 1 A illustrates the molecular bond structure of a strontium terminated surface of a strontium titanate monocrystalline oxide layer.
  • An aluminum surfactant layer is deposited on top of the strontium terminated surface and bonds with that surface as illustrated in FIG. 1 IB, which reacts to form a capping layer comprising a monolayer of Al 2 Sr having the molecular bond structure illustrated in FIG. 1 IB which forms a diamond-like structure with an sp 3 hybrid terminated surface that is compliant with compound semiconductors such as GaAs.
  • the structure is then exposed to As to form a layer of AlAs as shown in FIG. 1 IC.
  • GaAs is then deposited to complete the molecular bond structure illustrated in FIG. 1 ID which has been obtained by 2D growth.
  • FIG. 12 illustrates schematically, in cross section, a device structure 1200 in accordance with a further embodiment of the invention.
  • Device structure 1200 includes a monocrystalline semiconductor substrate 1202, preferably a monocrystalline silicon, germanium, or gallium arsenide wafer.
  • Monocrystalline semiconductor substrate 1202 includes two regions, 1204 and 1206.
  • An electrical semiconductor component generally indicated by the dashed line 1208 is formed, at least partially, in region 1204.
  • Electrical component 1208 can be a resistor, a capacitor, an active semiconductor component such as a diode or a transistor or an integrated circuit such as a CMOS integrated circuit.
  • electrical semiconductor component 1208 can be a CMOS integrated circuit configured to perform digital signal processing or another function for which silicon integrated circuits are well suited.
  • device 1208 includes circuits for inverters to convert direct current to alternating current or charge controllers.
  • the electrical semiconductor component in region 1204 can be formed by conventional semiconductor processing as is well known and widely practiced in the semiconductor industry.
  • a layer of insulating material 1210 such as a layer of silicon oxide or the like may overlie electrical semiconductor component 1208.
  • Insulating material 1210 and any other layers that may have been formed or deposited during the processing of semiconductor component 1208 in region 1204 are removed from the surface of region 1206 to provide a bare silicon surface in that region.
  • bare silicon surfaces are highly reactive and a native silicon oxide layer can quickly form on the bare surface.
  • a layer of barium or barium and oxygen is deposited onto the native oxide layer on the surface of region 1206 and is reacted with the oxidized surface to form a first template layer (not shown).
  • the layer reacted with the oxidized surface is comprised of strontium or strontium and oxygen.
  • a monocrystalline oxide layer is formed overlying the template layer by a process of molecular beam epitaxy.
  • Reactants including barium, titanium and oxygen are deposited onto the template layer to form the monocrystalline oxide layer in the preferred embodiment, while in other embodiments, the reactants include strontium, titanium, and oxygen.
  • the partial pressure of oxygen is initially set near the minimum necessary to fully react with the barium and titanium (or strontium and titanium) to form the monocrystalline oxide layer as a barium titanate (or strontium titanate) layer.
  • the partial pressure of oxygen is increased to form an amorphous layer between the growing crystalline layer and the substrate.
  • the step of depositing the monocrystalline oxide layer is terminated by forming a layer 1212, which includes 1-10 monolayers of titanium, barium, strontium, barium and oxygen, titanium and oxygen, or strontium and oxygen, and may additionally include a surfactant (e.g., 1 - 2 monolayers of Al) and/or a cap layer as discussed above in connection with FIGS. 10A- 10D and 11A - 1 1D.
  • a surfactant e.g., 1 - 2 monolayers of Al
  • an n-type semiconductor material layer 1216 (e.g., n-type GaAs) is epitaxially grown overlying layer 1212 and the monocrystalline oxide layer is exposed to an anneal process such that the titanate layer forms an amorphous oxide layer 1214.
  • a monocrystalline n-type layer 1218 (e.g., n-type GaAs) and a fluorescent dye layer 1220 are then formed overlying layer 1216 using a method described above with reference to FIGS 1-3.
  • Electrical contacts 1222 and 1224 (e.g., ohmic contacts) are then formed, such that contact may be made to layer 1218.
  • dye layer 1220 may be formed after contacts 1222 and 1224 are formed.
  • Structure 1200 may also include a p-n junction formed in substrate 1202 within region 1206.
  • junction 1226 is formed by forming an n-type layer 1228 (e.g., using ion implant, diffusion, or epitaxial growth techniques) overlying substrate 1202.
  • a back- side contact 1230 is formed using the method described above in connection with FIG. 4.
  • illustrative structure 1200 has been described as a structure formed on a silicon substrate 1202 and having a barium (or strontium) titanate layer, similar devices can be fabricated using other monocrystalline substrates, accommodating buffer layers and other monocrystalline material layers as described elsewhere in this disclosure.
  • a device structure in accordance with the present invention may include a solar cell including additional p-n junction layers, p-n junctions formed within the substrate, and a back side contact to increase the efficiency of the solar cell.
  • FIG. 13 illustrats a three-terminal solar cell structure 1300 in accordance with yet another embodiment of the invention.
  • Solar cell structure 1300 includes a p- silicon substrate 1302, an accommodating buffer layer 1304, a template layer 1306, a P+ AlGaAs layer 1308, a P AlGaAs layer 1310, an n+ AlGaAs layer 1312, an anti- reflective (AR) coating layer 1314, a dye layer 1316, a top emitter contact 1318, base contacts 320, and bottom emitter contacts 1322.
  • a more detailed description of a device including layers similar to layers 1302 and 1306-1314, is provided in "Three- Terminal Tandem Solar Cells with a Back-Contact Type Bottom Cell", Nagashima et al., 28th Photovoltaic Specialist Conference, September 2000 Proceedings, the content of which is hereby incorporated herein by reference.
  • the three-terminal solar cell structure 1300 in accordance with the preferred embodiment of the present invention includes an emitter contact 1318 at a top of the structure as well as an emitter contact 1322 and a base contact 1320 at the bottom of the structure. With this configuration, electrons generated at the top of the solar cell structure 1300 (from light absorption) flow toward the contact 1318, and electrons generated at the bottom of the cell flow toward emitter contact 1322.
  • Layers 1302-1312, layer 1316 and contact 1318 may be formed using the method describe above in connections with structures 100, 200, 300, 400, and 1200.
  • Base regions 1324 and emitter regions 1326 may be formed by suitably doping a portion of substrate (e.g., a p- silicon wafer). An insulating layer 1328 may then be formed underlying regions 1324 and 1326, and contacts 1320 and 1322 may be formed using, for example, deposition and etch techniques. ,
  • FIG. 4 illustrates a semiconductor structure 1400 in accordance with a further embodiment of the invention.
  • Semiconductor structure 1400 is similar to semiconductor structure 400 and is formed as described above with reference to FIG. 4, except that layer 110 which included the dye material that absorbs light energy of certain wavelengths and converts the energy into light of second wave length is not employed. Accordingly, a top layer, other than the dye layer is used such as monocrystalline material layer 108 or other desired top layer, such as an anti-reflective coating (not shown).
  • the additional p-n junction 402 is formed using substrate 102 and includes an additional back-side conductive material layer 404. Additional p-n junction 402 is configured to convert photons to electricity.
  • p-n structure 402 is formed of material different from material used to form layers 106 and 108.
  • junction 402 can convert photons (e.g., lower energy photons) that pass through layers 106 and 108.
  • the thickness of layers 106 and 108 is less than the thickness of layers 406 and 408.
  • FIG 15 illustrates schematically, and in cross section, a device structure 1500 in accordance with a further embodiment of the invention.
  • Device structure 1500 is similar to structure 1200 and is formed as described above, except that the dye layer 1220 is not formed. Accordingly, a top layer, other than the dye layer is used such as a monocrystalline n-type layer 1218 or other desired top layer, such as an anti-reflective coating (not shown).
  • an electrical semiconductor component generally indicated by the dashed line 1208 is formed, at least partially, in region 1204. Electrical component 1208 can be a resistor, a capacitor, an active semiconductor component such as a diode or a transistor or an integrated circuit such as a CMOS integrated circuit.
  • electrical semiconductor component 1208 can be a CMOS integrated circuit configured to perform digital signal processing or another function for which silicon integrated circuits are well suited.
  • device 1208 includes circuits for inverters to convert direct current to alternating current or charge controllers.
  • FIG. 16 illustrates a three terminal solar cell structure 1600 in accordance with yet another embodiment of the invention.
  • Structure 1600 is similar in structure to structure 1300 and is formed as described above, except that the dye layer 1360 is not used. Accordingly, a top layer, other than the dye layer is used such as an AR coating layer 1314 or other desired top layer.
  • FIG. 17 is a flow chart of a process for fabricating a solar cell structure in accordance with the processes described in more detail above. Some of the more significant steps are summarized in this flow chart description.
  • a monocrystalline substrate is provided, meaning that it is prepared for use in equipment that can perform a next step of the process.
  • the substrate is preferably silicon.
  • a monocrystalline accommodating buffer layer is epitaxially grown at step 1705, overlying the monocrystalline substrate.
  • a first monocrystalline semiconductor material is epitaxially grown over the monocrystalline accommodating buffer layer.
  • a second monocrystalline semiconductor layer is epitaxially grown adjacent the first monocrystalline semiconductor layer at step 1715, wherein a combination of the first monocrystalline semiconductor layer and the second monocrystalline semiconductor layer form a p-n junction.
  • the present invention includes structures and methods for fabricating material layers which form semiconductor structures, devices and integrated circuits including other layers such as metal layers. More specifically, the invention includes structures and methods for forming a compliant substrate which is used in the fabrication of semiconductor structures, devices and integrated circuits and the material layers suitable for fabricating those structures, devices, and integrated circuits.
  • a monocrystalline silicon wafer can be used in forming a monocrystalline germanium layer over the wafer.
  • the wafer is essentially a "handle" wafer used during the fabrication of semiconductor electrical components within a monocrystalline layer overlying the wafer. Therefore, electrical components can be formed within semiconductor materials over a wafer of at least approximately 200 millimeters in diameter and possibly at least approximately 300 millimeters.
  • a relatively inexpensive "handle" wafer overcomes the fragile nature of compound semiconductor or other monocrystalline material wafers by placing them over a relatively more durable and easy to fabricate base material.
  • an integrated circuit can be formed such that all electrical components, and particularly all active electronic devices, can be formed within or using the monocrystalline material layer even though the substrate itself may include a monocrystalline semiconductor material. Fabrication costs for solar cell devices and other devices employing non-silicon monocrystalline materials should decrease because larger substrates can be processed more economically and more readily compared to the relatively smaller and more fragile substrates (e.g., conventional compound semiconductor wafers).

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Abstract

L'invention concerne des structures pour cellules solaires (100) comprenant des couches épitaxiales de grande qualité faite de matériaux semi-conducteurs monocristallins recouvrant des substrats monocristallins (102) tels que des grandes tranches de silicium que l'on obtient en formant un substrat élastique pour la croissance de couches monocristallines. Une façon parmi d'autres de former un substrat élastique consiste d'abord à créer une couche tapon réceptrice (104) sur une tranche de silicium. La couche tampon réceptrice (104) est une couche de matériau monocristallin séparée de la tranche de silicium par une couche d'interface amorphe (112) d'oxyde de silicium. Ladite couche (112) dissipe les contrainte et permet de tirer un oxyde monocristallin de haute qualité recevant la couche tampon. Les structures de cellule solaire comprennent également une seconde couche semi-conductrice monocristalline disposée contre la première couche semi-conductrice monocristalline, la première et de la seconde couches semi-conductrices monocristallines combinées formant une liaison p-n (402).
PCT/US2002/014996 2001-07-25 2002-05-14 Structure semi-conductrice convenant pour la realisation d'une cellule solaire WO2004047184A2 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL2000248C2 (nl) * 2006-09-25 2008-03-26 Ecn Energieonderzoek Ct Nederl Werkwijze voor het vervaardigen van kristallijn-silicium zonnecellen met een verbeterde oppervlaktepassivering.

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Publication number Priority date Publication date Assignee Title
EP1109230A2 (fr) * 1999-12-02 2001-06-20 The Boeing Company Cellule photovoltaique multijonctions avec un Si ou Si-Ge substrat

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EP1109230A2 (fr) * 1999-12-02 2001-06-20 The Boeing Company Cellule photovoltaique multijonctions avec un Si ou Si-Ge substrat

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL2000248C2 (nl) * 2006-09-25 2008-03-26 Ecn Energieonderzoek Ct Nederl Werkwijze voor het vervaardigen van kristallijn-silicium zonnecellen met een verbeterde oppervlaktepassivering.
WO2008039067A2 (fr) * 2006-09-25 2008-04-03 Ecn Energieonderzoek Centrum Nederland Procédés de fabrication de photopiles solaires au silicium cristallin à passivation superficielle améliorée
WO2008039067A3 (fr) * 2006-09-25 2008-06-19 Ecn Energieonderzoek Ct Nederl Procédés de fabrication de photopiles solaires au silicium cristallin à passivation superficielle améliorée
KR101389546B1 (ko) * 2006-09-25 2014-04-28 이씨엔 에네르지온데르조크 센트륌 네덜란드 표면 패시베이션이 향상된 결정성 실리콘 태양 전지의 제조 방법
US8709853B2 (en) 2006-09-25 2014-04-29 Ecn Energieonderzoek Centrum Nederland Method of manufacturing crystalline silicon solar cells with improved surface passivation

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