WO2004046954A1

WO2004046954A1 - Processor module and information processor

Info

Publication number: WO2004046954A1
Application number: PCT/JP2002/012188
Authority: WO
Inventors: Tomoki Yonehana; Katsunori Takeshita
Original assignee: Fujitsu Limited
Priority date: 2002-11-21
Filing date: 2002-11-21
Publication date: 2004-06-03
Also published as: JPWO2004046954A1

Abstract

A processor module comprises a plurality of processors, and a common unit which is commonly connected to the processors and externally connectable. Each of the processors has a control circuit and a resource. The control circuit in each processor controls the control circuit(s) of one or more processors, and in addition to the resource in the processor, uses at least a part of the resources in the one or more processors.

Description

TECHNICAL FIELD Processor module and blue information processing device

The present invention relates to a processor module and an information processing device, and more particularly to a processor module and an information processing device having a plurality of processors such as a CPU. In general, an information processing device having a plurality of CPUs is called a multiple processor system (hereinafter, also referred to as a multi processor (MP) system). With the scalability, reliability, and diversity of functions required for information processing, multi-processor systems have

A CMP (Chip Multi Processor) structure that replaces the SMP (Symietric Multi Processor) structure has begun to be adopted.

The demand for high performance multiprocessors is expected to increase in the future. Therefore, the present invention relates to a further improvement in applicability in a multiprocessor system having a CMP structure.

Background art

FIG. 1 is a basic conceptual diagram of a multiprocessor system adopting the SMP structure, and FIG. 2 is a basic conceptual diagram of a multiprocessor system adopting the CMP structure. In FIG. 2, substantially the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. As shown in Fig. 1, in the commonly adopted SMP structure, a plurality of CPUs 1-1 to 1-N are directly connected to the main memory 3, the input / output device (1/0) 4, etc. 2 to use the capacity of each CPU 1-1 to 1-N equally. For this reason, in the SMP structure, as the number N of the CPUs 1-1_1-N increases, the competitiveness in the path 2 increases, and the performance improvement of the multiprocessor system is limited. As a result, in the SMP structure, an increase in the number N of CPUs 1-1_1 to 11-N is a factor that deteriorates the scalability of the multiprocessor system.

On the other hand, in the CMP structure, as shown in FIG. 2, a plurality of processor modules 11-1 to 11-M having the same configuration are connected to a path 2 that is connected to the main memory 3 or 1/04. Semiconductor substrate of each processor module 1 1 _ 1 to 11-M On the top, a plurality of CPUs 12-1 to 12-N and a common unit 13 are mounted. In one processor module 11, all the CPUs 12-1 to 12 -N in the processor module 11 share the common unit 13. Therefore, the common unit 13 guarantees coherency, and each of them is directly connected to the path 2 connecting with the main memory 3 and 1/04. Communication between CPUs 12-1 to 12-N mounted on the same board, that is, CPU 12-in one processor module ^ 11::! Since communication between 1 2 and N is performed only through the common unit 13, contention on the bus 2 can be reduced. As a result, in the case of the CMP structure, it is possible to reduce the problems that occur when the number of CPUs increases, unlike the SMP structure.

However, in the case of the CMP structure, the performance of individual CPUs is lower than that of the SMP structure that implements one CPU using the same level of technology. For this reason, a CMP structure is used to improve the processing speed when processing is performed by one high-performance CPU rather than many CPUs, such as scientific and technological calculations that require high-speed arithmetic processing. The resulting multiprocessor system has lower performance than the multiprocessor system that uses the SMP structure, and narrows the applicability of the multiprocessor system that uses the CMP structure.

Examples of the use of information processing include, for example, emphasizing the parallel processing characteristics of a multiprocessor system rather than increasing the speed of a single CPU such as a database, so that processing can be performed quickly and smoothly. There are uses. On the other hand, for example, in scientific computing, there are applications where high-speed processing can be realized by increasing the functionality of individual CPUs rather than parallel processing of many CPUs. These are in a trade-off relationship and it is difficult to satisfy both requirements simultaneously.

Prior art documents include the following.

Japanese Patent Application Laid-Open No. 63-2994931

Unexamined Japanese Patent Publication No.

Japanese Patent Application Laid-Open No. H10—2547775 Disclosure of the Invention

The present invention solves the above-mentioned problems, and provides a new and novel processor module and information. It is a general purpose to provide an information processing device.

A more specific object of the present invention is to provide an information processing apparatus employing a CMP structure, in which one processor uses the computational resources of another processor in a single processor module to operate at a higher speed than a single processor. The purpose of this is to satisfy simultaneously the demand for multi-parallel processing that performs complex processing and the demand for high-speed processing by a single processor.

Another object of the present invention is to provide a plurality of processors and a common unit commonly connected to a number of processors and connectable to the outside. Each processor has a control circuit and a resource. Control circuitry in one or more other processors to utilize at least some of the resources in the one or more other processors in addition to the resources in that processor. Another object of the present invention is to provide a processor module which is a feature. According to the processor module according to the present invention, in an information processing apparatus employing a CMP structure, one processor uses one processor in a single processor module and is faster than a single processor. And the need for high-speed processing by a single processor at the same time.

Still another object of the present invention is an information processing apparatus in which a plurality of processor modules are connected via a bus, wherein each processor module is connected to a plurality of processors and is commonly connected to the plurality of processors. A common unit connected to the path, each processor has a control circuit and resources in one processor module, and a control circuit in each processor controls a control circuit of one or more other processors Another object of the present invention is to provide an information processor 3 characterized by utilizing at least a part of the resources in the one or more other processors in addition to the resources in the processor. ¾ ^ to do. According to the information processing apparatus according to the present invention, in an information processing apparatus employing a CMP structure, one processor uses one processor and uses the computational resources of another processor as compared with a single processor. The demand for multi-parallel processing for high-speed processing and the demand for high-speed processing by a single processor can be satisfied simultaneously.

Further objects and features of the present invention will become apparent from the description given below with reference to the drawings. BRIEF DESCRIPTION OF THE FIGURES

Figure 1 is a basic conceptual diagram of a multiprocessor system that employs the SMP structure. FIG. 2 is a basic conceptual diagram of a multiprocessor system employing a CMP structure. FIG. 3 is a diagram for explaining the principle of operation of the present invention, in which the resource of the CPU of the information processing device is a storage unit such as a cache memory.

FIG. 4 is a diagram for explaining the operation principle of the present invention in the case where the resource of the CPU of the information processing apparatus is an arithmetic unit such as an arithmetic unit.

FIG. 5 is a block diagram showing a main part of the first embodiment of the information processing device 3 according to the present invention.

FIG. 6 is a block diagram showing a main part of a second embodiment of the information processing apparatus according to the present invention.

FIG. 7 is a front view for explaining a cache switching operation in the first and second embodiments.

FIG. 8 is a flowchart for explaining the cache switching operation in the first and second embodiments.

FIG. 9 is a block diagram showing a main part of a third embodiment of the information processing apparatus according to the present invention.

FIG. 10 is a block diagram showing a main part of a fourth embodiment of the information processing apparatus according to the present invention.

FIG. 11 is a flowchart for explaining the operation unit switching operation in the third and fourth embodiments.

FIG. 12 is a flowchart for explaining the operation: switching operation in the third and fourth embodiments. BEST MODE FOR CARRYING OUT THE INVENTION

First, the operation principle of the information processing apparatus according to the present invention will be described with reference to FIGS. The information processing apparatus according to the present invention employs a CMP structure, and separates resources (resources) individually owned by each CPU in one processor module, and a part of resources of another CPU. It has a configuration that can be used as. FIG. 3 shows a case where the resource of the CPU for the information processing device is a storage unit such as a cache memory, and FIG. 4 shows that the resource of the CPU of the information processing device is a calculation unit such as a calculator. Needless to say, the resources are not limited to the storage unit and the operation unit, but may be any resources that can be shared between CPUs. In FIGS. 3 and 4, substantially the same parts as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. In the present invention, the basic configuration of each processor module is the same as that shown in FIG. 2, but the configuration of each CPU is different from that shown in FIG.

Fig. 3 (a) shows a state where each CPU uses its own resources, and Fig. 3 (b) shows a state where one CPU uses at least a part of the resources of the other CPU. Is shown. For convenience of description, the processor module 11 includes two CPUs 12-1 and 12-2 and the common unit 13, and the power S and the number of CPUs are not limited to two. Each of the CPUs 12-1 and 12-2 includes a control circuit 21 and a cache memory 22.

The control circuit 21 is provided to control a cache memory 22 which is a resource of the CPU 12 to which the control circuit 21 belongs, and operates when the CPU 12 provides the cache memory 22 to another CPU 12. In the state of FIG. 3A, the two CPUs 12-1 and 12-2 use the respective cache memories 22 and exchange data with the common unit 13 as the two CPUs 12-1 and 12-2. I do.

On the other hand, in the state of FIG. 3B, the cache memory 22 of the CPU 12-2 is changed to the CPU 12_1, and the cache memory 22 of the CPU 12-2 can be used by the CPU 12-1. The control circuit 22 in the CPU 12-1 operates the control circuit 22 in the CPU 12-2 which controls the cache memory 22 of the CPU 12-2, and stores the cache memory 22 of the CPU 12_2 in the cache memory inside the CPU 12-1. Used as a single cache memory together with memory 22. At the same time, the control circuit 21 of the CPU 12-2 manages the exchange of data between the CPU 12-1 and the outside, and the CPU 12-1 stops the exchange of data with the outside. As a result, data processing is shared between the CPUs 12-1 and 12-2, and the speed of the CPUs 12-1 and 12-2 can be increased.

Fig. 4 (a) shows that each CPU uses its own resources, and Fig. 4 (b) shows that one CPU uses at least a part of the resources of the other CPU. Indicates a state in which The processor module 11 is composed of two CPUs 12-1 and 12-2 and a common unit 13 (not shown) for convenience of description, but the number of CPUs is limited to two. Not something. The CPUs 12-1 and 12-2 comprise a control circuit 21 (not shown) and an arithmetic unit 23, respectively.

The control circuit 21 is provided to control a computing unit 23 which is a resource of the CPU 12 to which the control circuit 21 belongs, and the CPU 12 transmits the computing unit 23 to another CPU 12. Operates when provided. In the state of FIG. 4 (a), two CPUs 12-1 and 12-2 use the respective computing units 23, and are shared as two CPUs 12-1 and 12_2. Exchange data with 13

That is, each of the CPUs 12-1 and 12-2 has a mechanism for issuing other instructions in addition to a mechanism for issuing instructions to the arithmetic unit 23 included in each CPU. The mechanism for issuing other instructions includes the function S for issuing instructions to the arithmetic unit 23 of the other CPU, but when each CPU 12-1 and 12-2 is operating individually, Function S stopped. FIG. 4 (a) shows the information processing unit 3 in this state.

Therefore, when a large load is applied to the CPU 12-1, or when the resources (cache) are insufficient, the CPU 12-1 is requested to provide the cache memory 22 as a resource to the other CPUs 12-2. The CPU 12-2 responding to the request purges the cache memory 22 (sweep data to the main memory 3), and passes the control to the CPU 12-1. When the load on CPU 1 2-1 is reduced and CPU 1 2-2 no longer needs cache memory 2 2, CPU 1 2-1 purges cache memory 2 2 of CPU 1 2-2 Control is returned to CPU 12-2.

On the other hand, in the state shown in FIG. 4 (b), the arithmetic unit 23 of the CPU 1 2 _ 1 is assigned to the CPU 12-2 by ^ (the CPU 12-2 is the arithmetic unit of the CPU 12-2. The control circuit 22 in the CPU 12-2 operates the control circuit 22 in the CPU 12-1 that controls the arithmetic unit 23 of the CPU 12-1. The arithmetic unit 23 of 1 2-1 is used as a single arithmetic unit together with the arithmetic unit 23 inside the CPU 12-2. At the same time, the control circuit 21 of the CPU 12-1 It manages the exchange of data between the CPU 12-2 and the outside, and the CPU 12-1 stops the exchange of data between the outside, thereby sharing the data processing between the CPUs 12-1 and 12-2. And the CPU 12-1 can be sped up. W

7

That is, when the information processing unit 3 is in the state shown in FIG. 4 (b), the CPU 12-1 stops its function as a CPU, and the internal operation unit 23 is connected to the CPU 12-2-2. . At this time, the CPU 12-2 operates as a CPU equivalent to a CPU having twice the normal operation unit by using the function of issuing instructions to the operation unit 23 of the CPU 12-1.

Therefore, when a heavy load is applied to the CPU 12-2 or when the resources (arithmetic units) are insufficient, the other CPU 12-1 requests the ^^ of the arithmetic unit 23 which is a resource. . The CPU 12-1 responding to the request purges the cache memory 22 (sweep data to the main memory 2), and passes the control to the CPU 12-2. When the load on CPU 1 2—2 decreases and it is no longer necessary to provide arithmetic unit 23 from CPU 1 2—1, CPU 1 2—2 purges cache memory 2 2 of CPU 1—2—1. Control is returned to CPU 1 2 1 1.

As described above, the ability of one CPU to use only its own resources, or the use of its own resources and at least part of the resources of other CPUs, depends on the individual processor module while the information processing device is operating. It is possible to switch dynamically for each P. This allows multiple CPUs to integrate their respective computational resources and operate as if they were a single high-speed CPU.

Next, embodiments of the processor module according to the present invention and the information processing apparatus according to the present invention will be described with reference to FIG.

FIG. 5 is a block diagram showing a main part of the first embodiment of the information processing apparatus according to the present invention. In the first embodiment of the information processing, the first embodiment of the processor module according to the present invention is used. 5, the same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

In this embodiment, two CPUs 12-1 and 12-2 are provided on the board of one processor module 1. Each CPU 12-1, 12-2 has a control circuit 21, a cache memory 22, a purge circuit 25, a multiplexer 26, an instruction issuing unit 110, and the like. In FIG. 5, for convenience of explanation, the CPU 12-1 shows only the circuit parts necessary when the CPU 12-2 uses the cache (Ll $) 22. When 2 uses the CPU 22-1 cache 22, the necessary circuit parts exist in mirror symmetry. FIG. 6 is a block diagram showing a main part of a second embodiment of the information processing apparatus according to the present invention. In the second embodiment of the information processing apparatus, the second embodiment of the processor module according to the present invention is used. In FIG. 6, the same portions as those in FIGS. 3 and 5 are denoted by the same reference numerals, and description thereof will be omitted.

In the present embodiment, three CPUs 12-1, 12-2, and 12-3 are provided on the board of one processor module 1. Each of the CPUs 12-1, 12-2, and 12-3 has a control circuit 21, a cache memory 22, a purge circuit 25, a multiplexer 26, an instruction issuing unit 110, and the like. In FIG. 5, for convenience of explanation, CPU 1 2—1 power S CPU 1 2—2, 1 2—3 Only power required to use the cache (Ll $) 2 2 The CPU 12–2 uses the CPU 12–1 and 12–3 to use the cache 22. The necessary circuit parts and the CPU 12–3 include the CPU 12–1 and 12–2. The circuit part necessary to use the cache 22 exists in mirror symmetry. FIG. 7 is a flowchart illustrating a cache switching operation in the first and second embodiments. In the description of FIG. 7, "the other CPUJ" indicates the CPU 12-1 in the first embodiment, and indicates the CPUs 12-2 and 12-3 in the second embodiment.

When the load on CPU 12-1 increases or the resource (cache) becomes insufficient, the instruction issuing unit 110 of CPU 12-1 receives the instruction to provide the resource (cache) between CPUs. (Cache) A notification that a request has occurred is sent to the control circuit 21 of the CPU 12-1, and the processing in FIG. 7 is started. In step S1, it is determined whether or not a resource (cache) provision request has occurred. If the determination result is YES, the control circuit 21 of the CPU 12-1 is sent to the control circuit 21 of another CPU. Issues a request REQ1 for providing resources. In step S2, the contents of the cache memory 22 of the other CPU are stored in the main memory 2 to save the information from the control circuit 21 of the other CPU to the purge circuit 25 of the other CPU. Issue request REQ2. Thus, the purge circuit 25 of the other CPU purges the contents of the cache memory 22 of the other CPU.

In step S3, it is determined whether or not the purging by the purging circuit 25 of another CPU has been completed. If the decision result in the step S3 is YES, a completion notice ACK1 indicating that the purging is completed is returned from the purge circuit 25 of the other CPU to the control circuit 21 of the other CPU. In step S4, the other CPU control circuit 21 responds to the completion notification ACK1. Then, a signal MuxEnable for enabling the multiplexer 26 of another CPU is supplied to the multiplexer 26. In step S5, in response to the control circuit 21 completion notification ACK1 of the other CPU, a completion notification ACK2 is returned to the control circuit 21 of the CPU 12-1 so that the CPU 12-1 Access to the cache memory 22 of another CPU is enabled, and the process ends.

The CPU 12-2 (12-3) that has provided the resources to the CPU 12-1 can operate under the control of the CPU 12-1 using the resources not provided.

When the load on CPU 12-1 is reduced or the CPU 12-1 no longer needs to borrow resources (cache), control the cache memory 22 of other CPUs by the following procedure. CPU return.

FIG. 8 is a flowchart illustrating a cache switching operation in the first and second embodiments. In the description of FIG. 8, “Other CPUJ denotes ^ in the first embodiment; ^ denotes CPU 12-1, and in the second embodiment, denotes CPU 12-2 1 2-3.

CPU 12-1 reduces load and resource (cache) shortage is resolved. CPU 12-1 instruction issue unit 110 power S Receives resources (cache) cancel instruction between CPUs. Then, the control circuit 21 of the CPU 121 notifies that the resource (cache) request has been canceled, and the processing in FIG. 8 starts. In step S 11, it is determined whether or not a resource (cache) provision cancellation request has occurred. If the determination result is YES, the control circuit 21 of the CPU 12-1 switches to the control circuit 21 of another CPU. Request REQ1 to return control of cache memory 22 of another CPU. In step S12, a request REQ2 for purging the contents of the cache memory 22 of the other CPU to the main memory 2 for storing information from the control circuit 21 of the other CPU to the purging circuit 25 of the other CPU Put out. As a result, the purge circuit 25 of the other CPU purges the contents of the cache memory 22 of the other CPU.

In step S13, it is determined whether or not the purging by the purging circuit 25 of another CPU has been completed. If the decision result in the step S13 is YES, a completion notice ACK1 indicating that the purging circuit 25 of the other CPU is completed is returned from the purging circuit 25 of the other CPU. In step S 14, in response to ACK 1, the control circuit 21 of the other CPU, the signal Muxdisable that disables the multiplexer 26 of the other CPU in response to ACK 1 Is supplied to the multiplexer 26. In step S5, the CPU 12-1 returns a completion notification ACK2 to the control circuit 21 of the CPU 12-1 in response to the completion notification ACK1 of the control circuit 21 of the other CPU. Access to 22 is disabled, and the process ends.

FIG. 9 is a block diagram showing a main part of a third embodiment of the information processing apparatus according to the present invention. In the third embodiment of the information processing apparatus, the third embodiment of the processor module according to the present invention is used. In FIG. 9, the same portions as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.

In this embodiment, two CPUs 12-1 and 12-2 are provided on the board of one processor module / module 1. Each of the CPUs 12-1 and 12-2 has a control circuit 21, a computing unit 23, multiplexers 27 and 28, and the like. In FIG. 9, for convenience of explanation, the CPU 12-1 shows only a circuit portion necessary when the arithmetic unit 23 of the CPU 12-2 is used. The circuit part necessary when using the arithmetic unit 23 is mirror-symmetric.

FIG. 10 is a block diagram showing a main part of a fourth embodiment of the information processing unit 8 according to the present invention. In the fourth embodiment of the information processing apparatus, the fourth embodiment of the processor module according to the present invention is used. 10, the same parts as those in FIGS. 4 and 9 are denoted by the same reference numerals, and the description thereof will be omitted.

In this embodiment, three CPUs 12-1, 12-2, and 12-3 are provided on the board of one processor module 1. Each CPU 12-1, 12-2, 12-3 has a control circuit 21, a computing unit 23, multiplexers 27, 28, and the like. In FIG. 10, for convenience of explanation, only the circuit parts necessary when the CPU 12-1 uses the arithmetic units 23 of the CPUs 12-2 and 12-3 are shown. Are required when using the computing unit 23 of the CPUs 12-1 and 12-3, and the circuit parts required when the CPU 12-3 uses the computing unit 23 of the CPUs 12-1 and 12-2. Change to Kagami ^.

FIG. 11 is a flowchart for explaining the operation unit switching operation in the third and fourth embodiments. In the description of FIG. 11, "the other CPUJ: ^ in the third embodiment indicates the CPU 12-1, and in the fourth embodiment, indicates the CPUs 12-2, 12-3. When the load on CPU 12-1 increases or the resources (arithmetic units) become insufficient, the instruction issuing unit 110 of CPU 12-1-1 receives resources (arithmetic units) «instructions between CPUs , Resources (arithmetic unit) »The request is notified to the control circuit 21 of the CPU 12-1, and the processing of FIG. 11 is started. In step S21, it is determined whether or not the resource (arithmetic unit) has been obtained. If the determination is YES, the control circuit 21 of the CPU 12-1 executes the other CPU. A request REQ1 for providing resources is issued to the control circuit 21. In step S22, a request REQ2 requesting termination of the arithmetic processing is issued from the control circuit 21 of the other CPU to the arithmetic unit 23 of the other CPU.

In step S23, it is determined whether or not the arithmetic processing by the arithmetic unit 23 of another CPU has been completed. Completion notification ACK1 indicating the end of the arithmetic processing is returned from arithmetic unit 23 of the other CPU, and if the decision result in step S23 is YES, in step S24, the control circuit 21 In response to the completion notification ACK1, the signal MuxEnable for enabling the multiplexers 26 and 27 of the other CPUs is supplied to the multiplexers 26 and 27. In step S25, the CPU 12-1 responds to the control circuit 21 of the other CPU in response to the completion notification ACK1 and returns a completion notification ACK2 to the control circuit 21 of the CPU 12-1. The operation unit 23 of another CPU is enabled, and the process ends. Thereby, the CPU 12-1 issues an instruction to the arithmetic unit 23 of another CPU, and the arithmetic unit 23 of the other CPU can be used for arithmetic processing.

The CPU 12-2 (12-3) whose resources are set to CPU 12-1 can operate under the control of the CPU 12-1 by using resources that have not been »» d.

When the load on the CPU 12-1 is reduced or the need to borrow the S resource (arithmetic unit) becomes unnecessary, the control of the cache memory 22 of the other CPU is performed according to the following procedure. Return to CPU.

FIG. 12 is a flowchart illustrating the cache switching operation in the third and fourth embodiments. In the description of FIG. 12, “other CPU” refers to CPU 12-1 in the third embodiment, and refers to CPU 12-2 and 12-3 in the fourth embodiment. .

As the load on the CPU 12-1 is reduced or the shortage of resources (arithmetic units) is eliminated, the instruction issuing unit 110 of the CPU 12-1 cancels the resources (arithmetic units) provided between the CPUs. Resource (arithmetic unit) «Control of CPU 12-1 The circuit 21 is notified, and the processing of FIG. 12 is started. In step S31, it is determined whether or not a resource (operator) cancellation request has occurred. If the determination is YES, the control circuit 21 of the CPU 12-1 and the control circuit of the other CPU are used. 21. Request REQ1 to return control of the arithmetic unit 23 of another CPU is issued to 21. In step S22, a request REQ2 requesting termination of the arithmetic processing is issued from the control circuit 21 of the other CPU to the arithmetic unit 23 of the other CPU.

In step S33, it is determined whether or not the force has been calculated by the calculator 23 of another CPU. Completion notification ACK1 indicating the end of the arithmetic processing is returned from the arithmetic unit 23 of the other CPU, and if the decision result in the step S33 is YES, the control circuit 21 of the other CPU is returned in the step S34. In response to the power S and the completion notification ACK1, the multiplexers 26,

The signal MuxDisable for disabling 27 is supplied to multiplexers 26 and 27. In step S35, the CPU 12-1 responds to the control circuit 21 of the other CPU in response to the completion notification ACK1 and returns a completion notification ACK2 to the control circuit 21 of the CPU 12-1. The use of the arithmetic unit 23 of another CPU is disabled, and the process ends. As a result, the other CPU issues an instruction to the arithmetic unit 23 of the other CPU and becomes available for arithmetic processing. As described above, according to this effort, it is possible to realize a single processor at the same time as the multiprocessor system 1S employing the CMP structure. This eliminates the need to individually design a multi-processor system for various applications, and a single multi-processor system can meet both requirements, thus reducing costs.

Also, it is only necessary that one CPU can use the resources of one or more CPUs, and a configuration in which one CPU uses the resources of three or more CPUs is acceptable.

Further, the first and third embodiments can be appropriately combined, or the second and fourth embodiments can be combined in a low-k sense. It is only necessary that one CPU can use at least a part of the resources of one or more CPUs.

It should be noted that the present invention is not limited to the above embodiments, and various improvements and modifications can be made within the scope of the present invention.

Claims

The scope of the claims

1. Multiple processors and

A common part that is commonly connected to a number of processors and that can be connected to the outside.

Each processor has a control circuit and resources,

The control circuit in each processor controls the control circuit in one or more other processors to use at least a part of the resources in the one or more other processors in addition to the resources in the processor. A processor module.

2. The processor module according to claim 1, wherein the tiilE resource is at least one of a storage unit and an operation unit.

3. The processor module according to claim 1 or 2, wherein the processor that has provided the resource to another processor operates independently of the other processor using the resource that has not been provided. .

4. The control circuit in each processor is characterized in that the control circuit of the one or more other processors is dynamically controlled according to a load or a shortage of resources of the processor. Item 1. The processor module according to Item 1.

5. An information processing apparatus in which a plurality of processor modules are connected via a path,

Each processor module includes a plurality of processors and a common unit commonly connected to the number of processors and connected to the bus,

In one processor module, each processor has a control circuit and resources, and the control circuit in each processor controls the control circuits of one or more other processors, and in addition to the resources in that processor. Resources in the one or more other processors An information processing device characterized by utilizing at least a part of a source.

6. The information processing device according to claim 5, wherein the sukumi resource is at least one of a storage unit and a calculation unit.

7. In the one processor module, a processor that has provided resources to another processor operates independently of the other processors using the resources. Item 7. The information processing device according to item 5 or 6.

8. In the one processor module, a control circuit in each processor dynamically controls a control circuit of the one or more other processors according to a load or a resource shortage of the processor. The information processing device according to any one of claims 5 to 7, wherein: