WO2004040454A3 - Method and apparatus for performing multi-page write operations in a non-volatile memory system - Google Patents

Method and apparatus for performing multi-page write operations in a non-volatile memory system Download PDF

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Publication number
WO2004040454A3
WO2004040454A3 PCT/US2003/028195 US0328195W WO2004040454A3 WO 2004040454 A3 WO2004040454 A3 WO 2004040454A3 US 0328195 W US0328195 W US 0328195W WO 2004040454 A3 WO2004040454 A3 WO 2004040454A3
Authority
WO
WIPO (PCT)
Prior art keywords
page
volatile memory
page number
memory system
write operations
Prior art date
Application number
PCT/US2003/028195
Other languages
French (fr)
Other versions
WO2004040454A2 (en
Inventor
Robert C Chang
Bahman Qawami
Farshid Sabet-Sharghi
Ping Li
Original Assignee
Sandisk Corp
Robert C Chang
Bahman Qawami
Farshid Sabet-Sharghi
Ping Li
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandisk Corp, Robert C Chang, Bahman Qawami, Farshid Sabet-Sharghi, Ping Li filed Critical Sandisk Corp
Priority to AU2003268564A priority Critical patent/AU2003268564A1/en
Publication of WO2004040454A2 publication Critical patent/WO2004040454A2/en
Publication of WO2004040454A3 publication Critical patent/WO2004040454A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means

Abstract

Methods and apparatus for facilitating multi-page or multi-block operations within a non-volatile memory system. According to one aspect of the present invention, a method for performing a multi-page command includes obtaining a first page number of a first convention that identifies a first page associated with a non-volatile memory, and mapping the first page number to a second page number of a second convention. Like the first page number, the second page number also identifies the first page. Mapping the first page number to the second page number includes identifying a total number of districts associated with the non-volatile memory and a total number of pages associated with each block of a total number of blocks. Finally, the first page is accessed using the second page number and the multi-page command.
PCT/US2003/028195 2002-10-28 2003-09-10 Method and apparatus for performing multi-page write operations in a non-volatile memory system WO2004040454A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003268564A AU2003268564A1 (en) 2002-10-28 2003-09-10 Method and apparatus for performing multi-page write operations in a non-volatile memory system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US28180402A 2002-10-28 2002-10-28
US10/281,804 2002-10-28

Publications (2)

Publication Number Publication Date
WO2004040454A2 WO2004040454A2 (en) 2004-05-13
WO2004040454A3 true WO2004040454A3 (en) 2004-10-28

Family

ID=32228774

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/028195 WO2004040454A2 (en) 2002-10-28 2003-09-10 Method and apparatus for performing multi-page write operations in a non-volatile memory system

Country Status (4)

Country Link
CN (1) CN1703678A (en)
AU (1) AU2003268564A1 (en)
TW (1) TWI272481B (en)
WO (1) WO2004040454A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2880152B1 (en) * 2004-12-24 2007-03-02 Trusted Logic Sa METHOD AND SYSTEM FOR OPTIMIZING THE MANAGEMENT OF RECORD FILES
DE102005001038B3 (en) * 2005-01-07 2006-05-04 Hyperstone Ag Non volatile memory`s e.g. flash memory, block management method for e.g. computer system, involves assigning physical memory block number of real memory block number on table, and addressing real memory blocks with physical block number
JP4547028B2 (en) * 2005-08-03 2010-09-22 サンディスク コーポレイション Nonvolatile memory with block management
WO2008016170A1 (en) * 2006-07-31 2008-02-07 Kabushiki Kaisha Toshiba Nonvolatile memory system, and data read/write method for nonvolatile memory system
US8065468B2 (en) 2008-07-03 2011-11-22 Silicon Motion, Inc. Data storing methods and apparatus thereof
TWI390548B (en) * 2008-07-03 2013-03-21 Silicon Motion Inc Data storing methods and apparatus thereof
WO2010000206A1 (en) * 2008-07-03 2010-01-07 Silicon Motion, Inc. Data storing methods and apparatus thereof
US9329989B2 (en) * 2011-12-30 2016-05-03 SanDisk Technologies, Inc. System and method for pre-interleaving sequential data

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5572466A (en) * 1992-10-06 1996-11-05 Kabushiki Kaisha Toshiba Flash memory chips
WO2002046929A1 (en) * 2000-12-06 2002-06-13 Tdk Corporation Method of controlling flash memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5572466A (en) * 1992-10-06 1996-11-05 Kabushiki Kaisha Toshiba Flash memory chips
WO2002046929A1 (en) * 2000-12-06 2002-06-13 Tdk Corporation Method of controlling flash memory
US20030028704A1 (en) * 2000-12-06 2003-02-06 Naoki Mukaida Memory controller, flash memory system having memory controller and method for controlling flash memory device

Also Published As

Publication number Publication date
TWI272481B (en) 2007-02-01
WO2004040454A2 (en) 2004-05-13
AU2003268564A8 (en) 2004-05-25
TW200424846A (en) 2004-11-16
CN1703678A (en) 2005-11-30
AU2003268564A1 (en) 2004-05-25

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