WO2004019202A3 - Fifo clock domain change - Google Patents

Fifo clock domain change Download PDF

Info

Publication number
WO2004019202A3
WO2004019202A3 PCT/US2003/023906 US0323906W WO2004019202A3 WO 2004019202 A3 WO2004019202 A3 WO 2004019202A3 US 0323906 W US0323906 W US 0323906W WO 2004019202 A3 WO2004019202 A3 WO 2004019202A3
Authority
WO
WIPO (PCT)
Prior art keywords
clock
data
retimed
delay line
rate
Prior art date
Application number
PCT/US2003/023906
Other languages
French (fr)
Other versions
WO2004019202A2 (en
Inventor
Mark Alan Schultz
David Jay Duffield
Dinakaran Chidambaram
Christopher Dale Duncan
Original Assignee
Thomson Licensing Sa
Mark Alan Schultz
David Jay Duffield
Dinakaran Chidambaram
Christopher Dale Duncan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing Sa, Mark Alan Schultz, David Jay Duffield, Dinakaran Chidambaram, Christopher Dale Duncan filed Critical Thomson Licensing Sa
Priority to AU2003257056A priority Critical patent/AU2003257056A1/en
Priority to BR0306137-0A priority patent/BR0306137A/en
Publication of WO2004019202A2 publication Critical patent/WO2004019202A2/en
Publication of WO2004019202A3 publication Critical patent/WO2004019202A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Communication Control (AREA)

Abstract

A data retiming arrangement applies data to be retimed to a delay line. The data is applied concurrently with a data clock applied to a clock multiplexer and to a data counter, and a second clock applied to the clock multiplexer. The counter counts a number of clock cycles equal to the capacity of the delay line, and produces a FULL signal at the incoming data clock rate. The FULL signal is retimed to the reclock rate by a cascade of registers, which produce a retimed FULL Flag. The FULL Flag resets the clock multiplexer to provide the delay line with the retimed clock, and also switches the delay line to read the retimed data at the retime clock rate.
PCT/US2003/023906 2002-08-22 2003-07-31 Fifo clock domain change WO2004019202A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2003257056A AU2003257056A1 (en) 2002-08-22 2003-07-31 Fifo clock domain change
BR0306137-0A BR0306137A (en) 2002-08-22 2003-07-31 Smart Board Fifo Approach Clock Domain Change

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US40520402P 2002-08-22 2002-08-22
US60/405,204 2002-08-22

Publications (2)

Publication Number Publication Date
WO2004019202A2 WO2004019202A2 (en) 2004-03-04
WO2004019202A3 true WO2004019202A3 (en) 2004-05-21

Family

ID=31946824

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/023906 WO2004019202A2 (en) 2002-08-22 2003-07-31 Fifo clock domain change

Country Status (3)

Country Link
AU (1) AU2003257056A1 (en)
BR (1) BR0306137A (en)
WO (1) WO2004019202A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4771426A (en) * 1984-07-20 1988-09-13 Unisys Corporation Isochronous clock reconstruction
US5592658A (en) * 1994-09-29 1997-01-07 Novacom Technologies Ltd. Apparatus and method for computer network clock recovery and jitter attenuation
US6209047B1 (en) * 1995-11-03 2001-03-27 Samsung Electronics Co., Ltd. RAM data transmitting apparatus and method using a FIFO memory with three fullness flags

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4771426A (en) * 1984-07-20 1988-09-13 Unisys Corporation Isochronous clock reconstruction
US5592658A (en) * 1994-09-29 1997-01-07 Novacom Technologies Ltd. Apparatus and method for computer network clock recovery and jitter attenuation
US6209047B1 (en) * 1995-11-03 2001-03-27 Samsung Electronics Co., Ltd. RAM data transmitting apparatus and method using a FIFO memory with three fullness flags

Also Published As

Publication number Publication date
BR0306137A (en) 2004-10-19
WO2004019202A2 (en) 2004-03-04
AU2003257056A8 (en) 2004-03-11
AU2003257056A1 (en) 2004-03-11

Similar Documents

Publication Publication Date Title
EP1589682B1 (en) Demultiplexer circuit
US9753486B2 (en) Clock gating with an asynchronous wrapper cell
TWI382317B (en) Method of compensating for a byte skew of pci express and pci express physical layer receiver for the same
JP6461089B2 (en) Multi-wire open drain link with data symbol transition based clock synchronization
WO2008027066A3 (en) Clock and data recovery
US20020163361A1 (en) Source synchronous I/O without synchronizers using temporal delay queues
US9054941B2 (en) Clock and data recovery using dual manchester encoded data streams
TW200603159A (en) Semiconductor memory device
JP6221328B2 (en) Receiving device, information processing device, and data receiving method
WO2014138640A1 (en) Clock recovery circuit for multiple wire data signals
WO2003019351A3 (en) Fifo memory devices having single data rate (sdr) and dual data rate (ddr) capability
WO2008148044A3 (en) Resonant clock and interconnect architecture for digital devices with multiple clock networks
WO2006017460A3 (en) Data transmission synchronization
US8610476B1 (en) Apparatus and methods for lock detection for semi-digital and fully-digital clock data recovery
TW200511314A (en) Synchronous memory device having advanced data align circuit
GB2358531A (en) Glitch free clock multiplexer circuit
JP2014127845A (en) Method of adjusting differential-signal skew and transmission circuit
TWI437411B (en) Fifo apparatus for the boundary of clock trees and method thereof
Konstantinou et al. The mesochronous dual-clock FIFO buffer
WO2004019202A3 (en) Fifo clock domain change
JP2003304225A (en) Data recovery circuit
WO2013189009A1 (en) Adaptive offset synchronization of data based on ring buffers
EP2466479B1 (en) Interface system, and corresponding integrated circuit and method
US20120155489A1 (en) Communication system, and corresponding integrated circuit and method
US7454543B2 (en) Early high speed serializer-deserializer (HSS)internal receive (Rx) interface for data sampling clock signals on parallel bus

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP