WO2004019202A2 - Fifo clock domain change - Google Patents

Abstract

A data retiming arrangement applies data to be retimed to a delay line. The data is applied concurrently with a data clock applied to a clock multiplexer and to a data counter, and a second clock applied to the clock multiplexer. The counter counts a number of clock cycles equal to the capacity of the delay line, and produces a FULL signal at the incoming data clock rate. The FULL signal is retimed to the reclock rate by a cascade of registers, which produce a retimed FULL Flag. The FULL Flag resets the clock multiplexer to provide the delay line with the retimed clock, and also switches the delay line to read the retimed data at the retime clock rate.

Description

SMART PARD FTFO Cl ΩC.K DOMAIN OHANGF

dross-Reference to Related Applications [0001] This application claims the benefit of the priority date of Provisional

Application No. 60/405,204 filed August 22, 2002 in the name of Schultz et al.

Field of the Invention [0002] This application relates to arrangements for reclocking data from a first clock rate to a second clock rate, lower than the first clock rate, and more particularly to a first-in, first out arrangement written and read at disparate clock rates.

Background of the Invention [0003] Reclocking of data is a common problem in data processing. One possible reason for reclocking of data is to correct the data for differential delays occasioned by passage through paths having different delays. Reclocking may also be required in order to make high-speed data accessible to a low-speed processor. Reclocking of data, while a relatively simple task in principle, can be subject to clocking errors which result in data errors. In the field of electronic transmission of video information, the data errors maybe manifested as "glitches" which degrade the picture.

[0004] In some applications, data transmitted through a data path may be accompanied by error detection (ED) or error correction (EC) codes, and often by both

(EDAC). During those intervals in which the data and its accompanying codes are transmitted over a network and the codes are used for verification andor correction of the data, the clock signal must accompany the data. However, when the data so transmitted and verified is used, the ED, EC, or EDAC portion of the data is surplusage, as it is no longer of any use. Consequently, the codes must be removed from the data. The removal of the codes is often accomplished by simply discontinuing the clock signal during transmission to the processing location of that portion of the data which represents the codes. Thus, the clock signal that accompanies the data to be processed may be discontinuous. Discontinuities in the clock signal may, in turn, adversely affect reclocking of the data signal from one clock rate to another. [0005] Improved reclocking method and apparatus is desired.

Summary of the Tnventirm

[0006] An arrangement according to an aspect of the invention is for receiving data at a first clock rate from a first data source, and for transmitting the data, at a second clock rate different from the first clock rate, to a sink of data operating at the second clock rate. The arrangement comprises a first clock source of the first clock signals, and a second clock source of the second clock signals. The arrangement also comprises at least one delay line including a data input port coupled to the first data source for writing the data therefrom, a data output port coupled to the sink of data for reading retimed data thereto, a clock input port, and a shift enable input port for controlling the writing and reading functions of the delay line. A counter is coupled to at least the source of first clock signals for counting first clock pulses, and for producing a FULL signal when the count of the counter equals the data capacity of the delay line. A cascade of registers clocked by the second clock signal is arranged for receiving the FULL signal, and for retiming the FULL signal to the second clock, to thereby produce a FULL Flag signal. A clock multiplexer includes a first input port coupled to receive the first clock signal, a second input port coupled to receive the second clock signals, and an output port coupled to the clock input port of the delay line, for applying the first clock signal to the clock input port of the delay line, and for, in response to the FULL Flag signal, switching the second clock signal to the clock input port of the delay line, whereby the delay line is clocked at the second clock rate in response to the FULL Flag signal.

[0007] In another avatar of the invention, a method for retiming data comprises the step of applying data at a first clock rate to a delay line controlled by clock signal. During the step of applying data, the delay line is clocked at the first clock rate. Concurrently with the step of applying data, cycles of the first clock are counted. When the count of the first clock signals equals the byte capacity of the delay line, a delay line FULL signal is generated. The delay line FULL signal is retimed to a second clock signal to produce a partially retimed Delay line FULL signal. The partially retimed Delay line FULL signal is retimed to the second clock signal, to produce a Delay line FULL Flag. The second clock signal is switched to the delay line for clocking the delay line at the second clock rate. In a particular version of this avatar, the steps of (a) applying data at the first clock rate, (b) clocking the delay line at the first clock rate, and (c) counting cycles are performed concurrently with a WRITE command to the delay line, and the method further comprises the step of switching the command to the delay line to READ in response to the Delay line FULL Flag. In another particular version of this avatar, the second clock signal is at a lesser rate than the first clock signal. The delay line may be a first-in, first out device.

Brief Description of the Drawing [0008] FIGURE 1 is a simplified block diagram of a first-in, first-out arrangement according to an aspect of the invention; and FIGURES 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, 2i, 2j, and 2k are timing diagrams illustrating various timing relationships in the arrangement of FIGURE 1.

Description of the Invention

[0009] In FIGURE 1, data packets clocked with (by) a high-speed or high-rate clock are applied by way of a data input port 10 and a data path 12 to a data input port 14id of a delay circuit in the form of a first-in, first-out (FIFO) circuit 14. The data packets applied to data input port 10 are represented by packets A, B, C, D, E, . . ., X, and Y timeline 210 of FIGURE 2a. Retimed data at a lower or lesser clock rate is read from data output port 14o of FIFO 14 for application by way of a path 16 to a data sink, which in one embodiment of the invention is a microprocessor (μP) 15. The operation is cyclic or at least recurrent, as the FIFO 14 fills with data and then empties to microprocessor 15. In one embodiment of the invention, FLFO circuit 14 is a simple delay line including a clock input port 14ic and a shift enable input port 14is. The FIFO clock signal is varied, and is illustrated as waveform 222 in FIGURE 2g. In one application of this embodiment, the data packets are each of 188 bytes, and the data capacity of the FIFO is 188 bytes. [0010] A WRITE ENABLE (WR_ENABLE) signal or flag is applied to input port 24 of the arrangement of FIGURE 1 at the same time that a packet of data is applied to data input port 10. The RDJ3NABLE signal originates in the register decoder (not illustrated) of μP 15, and is output from the microprocessor 15 at one of a collection of ports illustrated together as a single port 15io. FIGURE 2d illustrates the WR_ENABLE signal as a waveform 216. The WRITE ENABLE signal is applied from input port 24 to a first input port 26iw of a multiplexer (MPX) 26, and also by way of an inverter 31 \ to a first input port 30il of an AND circuit 30. The timing of the WR_ENABLE signal is illustrated in FIGURE 2d. Multiplexer 26 of FIGURE 1 also receives a READ ENABLE (RDJENABLE) signal at an input port 26ir. Multiplexer 26 is controlled by a FIFO_FULL flag signal applied to its control input port 26ic. The RD_ENABLE and FIFO_FULL Flag are illustrated in FIGURES 2e and 2k. During those times in which the FEFO_FULL flag is at (in) a first state representing a less- than-full condition, the WRITE ENABLE signal is coupled through MUX 26 of FIGURE 1 to SHIFT ENABLE signal input port 14is of FIFO 14, to enable FIFO 14 for writing or clocking in of data. The data which is clocked in or written is at the rate of the clock signal applied to input port 14ic. This clock rate may be either the high speed clock (HSclk) or a relatively low-speed clock (μPclk) derived from the microprocessor (μP) to which the retimed data is applied. Thus, either HSclk or μPclk is applied to clock input port 14ic of FIFO 14, depending upon the state of the FIFO_FULL Flag. The first state of the FIFO_FULL flag, in one version, may be an inactive state represented by a logic low or logic 0 state, which results in coupling of the high-speed clock HSclk to clock input port 14ic of FIFO 14 during the writing operation. The FIFO clock signal is illustrated as a waveform 222 in FIGURE 2g. [0011] The incoming data at data input port 10 of FIGURE 1 is accompanied by concurrent high speed clock signal HSclk applied to a high-speed clock input port 16, and from high-speed clock input port 16 to an input port 18ih clock multiplexer circuit 18 and a high speed clock HSclk input port 20ih of a counter 20. Thus, counter 20 always operates at the speed of high-speed clock signal HSclk during loading or writing. FIGURE 2b illustrates the high speed clock signal 212. A PACKET RESET signal (220 of FIGURE 2f) is applied to a PACKET RESET input port 22 of FIGURE 1 before the end of each packet of data if the packet available for being captured has been determined or deemed to be not a packet of interest. The PACKET_RESET pulse resets the counter before it reaches the full packet count to assure that the counter is ready for the first byte of data from the new incoming packet, and also assures that that the FIFO_FULL signal is not activated, since the counter does not reach a count of 187. If the packet available to be captured is a packet of interest, the PACKET RESET flag is not activated. The PACKET RESET signal resets counter 20 of FIGURE 1 to zero count, preparatory for counting the bytes of the next following packet. Counter 20 of FIGURE 1 is clocked at the same rate as the data incoming to port 10, and it is reset to zero at the beginning of a data packet. The full count of counter 20 equals the number of bit locations in FIFO delay 14, so that, in principle, counter 20 reaches a full count at the same time that FIFO 14 becomes full of data. As mentioned, in one embodiment of the invention, each data packet contains 188 bytes. The count of counter 20 is illustrated as a waveform 224 in FIGURE 2h. [0012] The WRITE_ENABLE signal is always enabled at the beginning of each packet during the storing cycle in order to start storing the data in the currently received packet. While the packet is in the process of being stored, other logic determines if the packet currently in the process of being stored is a desired packet for capture. If the packet currently being stored is not desired, the WRITE-ENABLE flag is disabled, which stops the writing of the flow of data applied to input port 14id of FIFO 14, and is also applied to input port 3 Oil of AND gate 30, but does not affect the gate since the output signal of the counter is not active. As mentioned below, the microprocessor can read desired parts of the 188-bit packet, as for example the microprocessor might read ten bytes of desired information which occur at bytes 134 to 144 of the packet, and having all the information which is required from the packet, produce a PACKET_RESET signal (220 of FIGURE 2f) at or near the 144th byte (as illustrated in FIGURE 2h) to thereby end the packet reading. In other cases, the full packet will be read. In that case, the full count signal is applied from output port 20o of counter 20 to a second input port 30i2 of AND gate 30. A DISABLE_FIFO_FULL signal (226 of FIGURE 2i) can be applied from an output port 15io of microprocessor 15, by way of an inverter 31₂ to _a third input port 30i3 of AND gate 30 of FIGURE 1. The DIS ABLE_FIFO_FULL signal disables AND gate 30 during those times in which the DISABLE_FIFO_FULL is inactive or at a logic low (logic 0) level.

[0013] Thus, during those times, after a PACKET RESET signal is applied to input port 22 of the arrangement of FIGURE 1, in which data is applied to input port 10, accompanied by a high-speed clock signal applied to input port 16 and a WRITE ENABLE signal applied to port 24, and if the FIFO_FULL flag is not raised, FIFO 14 will load with (write) data while counter 20 counts clock pulses corresponding to the number of data bytes so loaded. During the writing operation, the WRITE ENABLE signal (216 of FIGURE 2d) applied to input port 30il of AND gate 30 is active, and the DISABLE_FLFO_FULL signal (226 of FIGURE 2i) applied to port 30i3 is also active, thereby maintaining AND gate 30 in readiness for receiving an active signal from output port 20o of counter 20. At some time, counter 20 will reach a full count, and apply an active signal from its output port 20o to AND gate port 30i2. At this time, all of the input ports of AND gate 30 become logically active, and AND gate 30 produces a FIFO_ FULL signal, clocked at the high speed clock signal HSclk. The FlFO_FULL signal is illustrated as 228 of FIGURE 2j. [0014] Ideally, the FIFO_FULL signal produced by AND gate 30 could be used to set clock multiplexer 18 and read-write multiplexer (MPX) 26. However, direct use of the FIFO_FULL signal produced by AND gate 30 may produce improper operation as a result of timing glitches. The FIFO_FULL signal produced by AND gate 30 at its output port 30o is applied by way of a signal path 33 to an input port of microprocessor 15, and is also retimed to the microprocessor clock by a cascade 32 of shift registers, illustrated as shift registers (REG) or flip-flops (FF) 34 and 36. More particularly, the FIFO_FULL signal from AND gate 30 is applied to the data input port 34id of register 34. Register 34 also receives at its clock input port 34ic the microprocessor (μP) clock signal μPclk (214 of FIGURE 2c), which is derived from a source associated with the microprocessor (not illustrated). Register 34 partially reclocks the FIFO_FULL signal to produce a partially retimed signal designated F, and the partially reclocked FIFO_FULL signal is applied from output port 34o of register 34 to the data input port 36id of a further register 36. Register 36 receives the microprocessor clock signal μPclk at its clock input port 36ic, and produces at its output port 36o the completely retimed FLFO_FULL signal, denominated FIFO_FULL flag, for application over a signal path 38 to the control signal input port 26ic of multiplexer (MUX) 26 and to the control signal input port 18c of clock MPX 18. Multiple registers are used to avoid the possibility of a "shoot-through" glitch which might occur if but a single register were used. Such a shoot- through glitch can occur when the edge of the data signal from one clock domain coincides in time with the edge of a FF clock signal from a different clock domain. The second FF is added to change the data edge and prevent continuation of the glitch. The FIFO_FULL Flag or signal is illustrated as 230 of FIGURE 2k.

[0015] A second input port 18i£ of clock multiplexer (MPX) 18 of FIGURE 1 receives the microprocessor clock μPclk. When the FIFO_FULL Flag is produced at the output port 36o of register 36 and applied to the control input ports of multiplexers 18 and 26 of FIGURE 1 , MUX 26 switches to its READ ENABLE input, so that the READ ENABLE signal (218 of FIGURE 2e) is applied to the SHIFT ENABLE input port 14is of FIFO 14, to disable writing and enable reading. Also, clock multiplexer (MPX) 18 couples to the clock input port 14ic of FIFO 14 from its output port 18o the low-speed or microprocessor clock μPclk applied to its input port 18iZ, so that FIFO 14, during the remaining portion of the cyclical or recurrent operation of the arrangement, which is to say during the READ operation, clocks the data stored in FIFO 14 to output port 14o at the microprocessor clock rate μPclk.

[0016] Microprocessor 15 can terminate the reads from FIFO 14 at any time by sending the DISABLE_FIFO_FULL signal from a port 15io of the microprocessor to input port 30i3 of AND gate 30. This saves microprocessor cycles and therefore saves microprocessor resources. For example, suppose that the microprocessor requires the information from only ten bytes of data contained in the 188-byte packet. Assuming that those ten relevant bytes occur early in the packet, the microprocessor can read the ten bytes, and then issue the DISABLE_FIFO_FULL signal (226 of FIGURE 2i) which, after two further μP clock cycles, will clear the FIFOJFULL Flag interrupt associated with a register of μP 15. The FIFO can then again be enabled to start to capture new data. The μP can either poll the register to determine the status of the FIFO_FULL Flag, or the Flag could be connected to an interrupt request. The system can use both alternatives, with the interrupt software controllable to be either enabled or disabled as an interrupt. The microprocessor uses the FIFO_FULL Flag to determine the status of the counter. This may be important in the context of a smart card which performs an operation important for security, such as running a complex decrypting algorithm to determine the value of the next key.

During such complex operations, the interrupts are disabled until the microprocessor is again ready to receive outside information.

[0017] Thus, an arrangement according to an aspect of the invention is for receiving data (210) at a first clock rate (HSclk) from a first data (210) source (10), and for transmitting the data (210), at a second clock rate (μPclk) different from the first clock rate (HSclk), to a sink of data (210) operating at the second clock rate (μPclk). The arrangement comprises a first clock source (16) of the first clock signals, and a second clock source (17) of the second clock signals. The arrangement also comprises at least one delay line (14) including a data (210) input port (14id) coupled to the first data (210) source (10) for writing the data (210) therefrom, a data (210) output port coupled to the sink of data (210) for reading retimed data (210) thereto, a clock input port (14ic), and a shift enable input port (14is) for controlling the writing and reading functions of the delay line (14). A counter (20, 30) is coupled to at least the source (16) of first clock (HSclk) signals for counting first clock pulses, and for producing a FULL signal (228) when the count of the counter (20, 30) equals the data (210) capacity of the delay line (14). A cascade of registers (32) clocked by the second clock (μPclk) signal is arranged for receiving the FULL signal (228), and for retiming the FULL signal (228) to the second clock (μPclk), to thereby produce a FULL Flag signal (230). A clock multiplexer (18) includes a first input port (18ih) coupled to receive the first clock (HSclk) signal, a second input port (18i£) coupled to receive the second clock (μPclk) signals, and an output port (18o) coupled to the clock input port (14ic) of the delay line (14), for applying the first clock (HSclk) signal to the clock input port (14ic) of the delay line (14), and for, in response to the FULL Flag signal, switching the second clock (μPclk) signal to the clock input port 14ic) of the delay line (14), whereby the delay line (14) is clocked at the second clock rate (μPclk) in response to the FULL Flag signal (230).

[0018] In another avatar of the invention, a method for retiming data (210) comprises the step of applying data (210) at a first clock rate (HSclk) to a delay line (14) controlled by clock signal. During the step of applying data (210), the delay line (14) is clocked at the first clock rate (HSclk). Concurrently with the step of applying data (210), cycles of the first clock are counted. When the count of the first clock (HSclk) signals equals the byte capacity of the delay line (14), a delay line (14) FULL signal (228) is generated. The delay line (14) FULL signal (228) is retimed to a second clock signal (μPclk) to produce a partially retimed Delay line ( 14) FULL signal (F'). The partially retimed Delay line ( 14)

FULL signal (F') is retimed to the second clock signal (μPclk), to produce a Delay line (14) FULL Flag (230). The second clock signal (μPclk) is switched to the delay line (14) for clocking the delay line (14) at the second clock rate (μPclk). In a particular version of this avatar, the steps of (a) applying data (210) at the first clock rate (HSclk), (b) clocking the delay line (14) at the first clock rate (HSclk), and (c) counting cycles are performed concurrently with a WRITE command (216) to the delay line (14), and the method further comprises the step of switching the command to the delay line (14) to READ in response to the Delay line (14) FULL Flag. In another particular version of this avatar, the second clock signal is at a lesser rate than the first clock signal. The delay line may be a first-in, first out (FIFO) device.

Claims

1. An arrangement for receiving data at a first clock rate from a first data source and for transmitting said data, at a second clock rate different from said first clock rate, to a sink of data operating at said second clock rate, said arrangement comprising: a first clock source of said first clock signals; a second clock source of said second clock signals; at least one delay line including a data input port coupled to said first data source for writing said data therefrom, a data output port coupled to said sink of data for reading retimed data thereto, a clock input port, and a shift enable input port for controlling the writing and reading functions of said delay line; counting means coupled to at least said source of first clock signals for counting said first clock pulses, and for producing a FULL signal when the count of said counting means equals the data capacity of said delay line; a cascade of registers clocked by said second clock signal, for receiving said FULL signal, and for retiming said FULL signal to said second clock, to thereby produce a FULL Flag signal; a clock multiplexer including a first input port coupled to receive said first clock signal, a second input port coupled to receive said second clock signals, and an output port coupled to said clock input port of said delay line, for applying said first clock signal to said clock input port of said delay line, and for, in response to said FULL Flag signal, switching said second clock signal to said clock input port of said delay line, whereby said delay line is clocked at said second clock rate in response to said FULL Flag signal.

2. A method for retiming data, comprising the steps of: applying data at a first clock rate to a delay line controlled by a clock signal; during said step of applying data, clocking said delay line at said first clock rate; concurrently with said step of applying data, counting cycles of said first clock; when the count of said first clock equals the byte capacity of said delay line, generating a DELAY LINE FULL signal; retiming said DELAY LINE FULL signal to a second clock signal to produce a partially retimed DELAY LINE FULL signal; retiming said partially retimed DELAY LINE FULL signal to said second clock signal, to produce a DELAY LINE FULL Flag; in response to said DELAY LINE FULL Flag, switching said second clock signal to said delay line for clocking said delay line at said second clock rate.

3. A method according to claim 2, wherein said steps of (a) applying data at said first clock rate, (b) clocking said delay line at said first clock rate, and (c) counting cycles are performed concurrently with a WRITE command to said delay line; and further comprising the steps of: in response to said DELAY LINE FULL Flag, switching the command to said delay line to READ.

4. A method according to claim 2, wherein said second clock signal is at a lesser rate than said first clock signal.

5. A method according to claim 2, wherein said delay line is a first-in, first out (FIFO) device.

6. A method for retiming data, comprising the steps of: applying data at a first clock rate to a delay line controlled by a clock signal; during said step of applying data, clocking said delay line at said first clock rate; concurrently with said step of applying data, counting cycles of said first clock; when the count of said first clock equals the byte capacity of said delay line, generating a DELAY LINE FULL signal; retiming said DELAY LINE FULL signal to a second clock signal to produce a DELAY LINE FULL Flag; in response to said DELAY LINE FULL Flag, switching said second clock signal to said delay line for clocking said delay line at said second clock rate.

7. A method according to claim 6, wherein said first clock rate is higher than said second clock rate.