WO2003107176A3 - Load speculation method - Google Patents

Load speculation method Download PDF

Info

Publication number
WO2003107176A3
WO2003107176A3 PCT/IB2003/002363 IB0302363W WO03107176A3 WO 2003107176 A3 WO2003107176 A3 WO 2003107176A3 IB 0302363 W IB0302363 W IB 0302363W WO 03107176 A3 WO03107176 A3 WO 03107176A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
invalidated
returned
further processing
speculative
Prior art date
Application number
PCT/IB2003/002363
Other languages
French (fr)
Other versions
WO2003107176A2 (en
Inventor
Jan Hoogerbrugge
Original Assignee
Koninkl Philips Electronics Nv
Jan Hoogerbrugge
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Jan Hoogerbrugge filed Critical Koninkl Philips Electronics Nv
Priority to AU2003241090A priority Critical patent/AU2003241090A1/en
Publication of WO2003107176A2 publication Critical patent/WO2003107176A2/en
Publication of WO2003107176A3 publication Critical patent/WO2003107176A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution

Abstract

The invention is based on the idea to perform data speculation on loads where the data has been invalidated by the cache coherence protocol. A cache memory is checked for requested data and it is determined whether said requested data in the cache memory was invalidated by cache coherence protocol. The invalidated data is markedas speculative data and said data marked speculative is returned for further processing. If no invalidated data has been found, requested data is returned for further processing.
PCT/IB2003/002363 2002-06-13 2003-05-27 Load speculation method WO2003107176A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003241090A AU2003241090A1 (en) 2002-06-13 2003-05-27 Load speculation method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02077330 2002-06-13
EP02077330.5 2002-06-13

Publications (2)

Publication Number Publication Date
WO2003107176A2 WO2003107176A2 (en) 2003-12-24
WO2003107176A3 true WO2003107176A3 (en) 2004-03-25

Family

ID=29724489

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/002363 WO2003107176A2 (en) 2002-06-13 2003-05-27 Load speculation method

Country Status (2)

Country Link
AU (1) AU2003241090A1 (en)
WO (1) WO2003107176A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0614146A1 (en) * 1993-01-29 1994-09-07 Motorola, Inc. A data processor with speculative data transfer and method of operation
WO2000034882A1 (en) * 1998-12-10 2000-06-15 Fujitsu Limited Cache device and control method
US20030014602A1 (en) * 2001-07-12 2003-01-16 Nec Corporation Cache memory control method and multi-processor system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0614146A1 (en) * 1993-01-29 1994-09-07 Motorola, Inc. A data processor with speculative data transfer and method of operation
WO2000034882A1 (en) * 1998-12-10 2000-06-15 Fujitsu Limited Cache device and control method
US6526480B1 (en) * 1998-12-10 2003-02-25 Fujitsu Limited Cache apparatus and control method allowing speculative processing of data
US20030014602A1 (en) * 2001-07-12 2003-01-16 Nec Corporation Cache memory control method and multi-processor system

Also Published As

Publication number Publication date
AU2003241090A8 (en) 2003-12-31
AU2003241090A1 (en) 2003-12-31
WO2003107176A2 (en) 2003-12-24

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