WO2003096404A1 - A method of forming base regions and emitter windows in silicon bipolar transistors - Google Patents
A method of forming base regions and emitter windows in silicon bipolar transistors Download PDFInfo
- Publication number
- WO2003096404A1 WO2003096404A1 PCT/SE2003/000698 SE0300698W WO03096404A1 WO 2003096404 A1 WO2003096404 A1 WO 2003096404A1 SE 0300698 W SE0300698 W SE 0300698W WO 03096404 A1 WO03096404 A1 WO 03096404A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- base layer
- forming
- emitter window
- dielectric
- Prior art date
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 19
- 239000010703 silicon Substances 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 25
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 25
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 25
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 10
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 abstract 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract 5
- 239000010410 layer Substances 0.000 description 50
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000011241 protective layer Substances 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- -1 α-Si Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
Definitions
- the invention relates to silicon devices, especially semiconductor manufacturing processes for low- voltage high-frequency BiCMOS or bipolar circuits with SiGe-base, particularly for use in mobile telecommunication circuits.
- CMOS or BiCMOS circuits are used today for high-speed applications in the 1-5 GHz frequency range, replacing circuits previously only possible to realize using III-N based technologies.
- High-performance bipolar integrated circuits are used extensively for critical building blocks in telecommunication circuits, mainly for the analog functions, e.g. for switching currents and voltages, and for the high-frequency radio circuit functions in e.g. mixers, amplifiers, detector etc.
- a common problem in all self-aligned double poly-Si processes is the removal of the (poly-) silicon used for the extrinsic base in the emitter opening without etching down into the monocrystalline silicon.
- a certain degree of overetching down into the substrate is allowed, at least in a process where the base is formed by ion implantation after the etching.
- overetching is not allowed and, thus, this etching becomes very critical.
- the object of the invention is to provide a simple solution for removing the polysilicon used for the extrinsic base in the emitter window. No etching is allowed into the layer that will be used as intrinsic base and that already has been formed, typically an epitaxially grown base layer containg SiGe.
- the method according to the invention of forming a base region and an emitter window for a silicon bipolar transistor on a silicon substrate, comprising forming an intrinsic base layer containing SiGe, on top of the substrate, forming a layer of Si0 2 on the intrinsic base layer, forming an extrinsic base layer containing Si, on top of the Si0 2 layer, forming a layer of a dielectric on top of the extrinsic base layer, patterning the emitter window on top of the dielectric, and etching out the emitter window selectively down to the Si0 2 layer, in that the structure is exposed to HF to remove the Si0 2 layer in the emitter window, and Si is selectively deposited on the exposed intrinsic base layer and exposed side walls of the extrinsic base layer as well as in cavities created in the Si0 2 layer and the dielectric by the exposure to HF to establish contact between the extrinsic base layer and the intrinsic base layer.
- the selective filling process will not suffer from pattern density effect, i.e. loading.
- the method according to the invention will therefore have a much larger process margin.
- Figs. 1 - 4 illustrate successive known steps in connection with the fabrication of a silicon bipolar transistor on a silicon substrate
- Figs. 5 and 6 illustrate two steps according to the invention.
- Fig. 1 Shown in Fig. 1 is a silicon substrate 1, wherein the silicon is preferably monocrystalline.
- a multilayer structure of Si and SiGe layers with added dopants, typically boron, and possibly other materials such as C is formed as an intrinsic base layer 2 on the substrate.
- the top layer of the intrinsic base layer 2 usually consists of a couple of hundred A buffer layer of undoped Si.
- the total thickness of the intrinsic base layer 2 is 1000-1500 A typically.
- this protective layer 3 porous and easily etched by HF in a later step, it can purposely be damaged by exposure to plasma, such as used in a dry-etching system.
- a predetermined region of the protective layer 3 can be protected from exposure to plasma by applying a photoresist layer (not shown) and patterning it.
- the purpose of the photoresist layer is to prevent the predetermined region from being damaged by the plasma. This will be further described in connection with Fig.
- the processing then continues according to the standard flow by deposition of a layer containing Si, on top of the Si0 2 layer.
- This Si layer will serve as extrinsic base layer 4 as shown in Fig. 3.
- the material of the extrinsic base layer 4 can be polysilicon, ⁇ -Si, SiGe, etc.
- An ion implantation (boron) is performed to heavily dope the Si layer to p-type in a manner known per se.
- a layer 5 of a dielectric is then formed on top of the extrinsic base layer 4 in that an oxide (TEOS) layer is deposited as also shown in Fig. 3.
- TEOS oxide
- Typical thicknesses of the silicon and oxide layers are 1000-2000 A each.
- An emitter window is patterned on top of the dielectric in that a photoresist mask 6 defining the emitter window opening and outside edges of a base contact is applied on top of the dielectric 5 as also illustrated in Fig. 3. It is understood that Fig. 3 only shows half a symmetrical emitter-base structure of the transistor.
- the TEOS/silicon stack in Fig. 3 is then etched down to the Si0 2 layer 3 that is used as a stopping layer ("stop-on-oxide").
- stop-on-oxide the selectivity between oxide and silicon and end-point detection is used to carefully stop the etching within the oxide layer.
- the etched down structure is shown in Fig. 4.
- the structure in Fig. 4 is exposed to HF, preferably HF vapor, while the photoresist still remains on top of the dielectric layer 5.
- Si0 2 will also be removed under the extrinsic base layer 4 causing cavities 7 to be formed.
- the extent of the cavities 7 can be controlled by the size of the protected region on the protective layer 3, in that the Si0 2 etch rate will be lower in the protected region.
- Si0 2 will also be removed under the edges of the dielectric 5 causing cavities 8 to be formed as indicated in Fig. 5.
- a layer 9 of Si is selectively deposited on the exposed silicon areas of the structure, i.e. on the exposed intrinsic base layer 2 and exposed side walls of the extrinsic base layer 4 as well as in the cavities 7, 8 created in the Si0 2 layer 3 and the dielectric 5 by the exposure to HF in order to establish contact between the extrinsic base layer 4 and the intrinsic base layer 2.
- the Si layer 9 will fill the cavities 7, 8, forming a good extrinsic base contact path to the substrate 1.
- the resulting structure is shown in Fig. 6.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
In a method of forming a base region and an emitter window for a silicon bipolar transistor on a silicon substrate, comprising forming an intrinsic base layer containing SiGe, on top of the substrate, forming a layer of SiO2 on the intrinsic base layer, forming an extrinsic base layer containing Si, on top of the SiO2 layer, forming a layer of a dielectric on top of the extrinsic base layer, patterning the emitter window on top of the dielectric, and etching out the emitter window selectively down to the SiO2 layer, the structure is exposed to HF to remove the SiO2 layer in the emitter window, and Si is selectively deposited on the exposed intrinsic base layer and exposed side walls of the extrinsic base layer as well as in cavities created in the SiO2 layer and the dielectric by the exposure to HF to establish contact between the extrinsic base layer and the intrinsic base layer.
Description
A METHOD OF FORMING BASE REGIONS AND EMITTER WINDOWS IN SILICON BIPOLAR TRANSISTORS
TECHNICAL FIELD The invention relates to silicon devices, especially semiconductor manufacturing processes for low- voltage high-frequency BiCMOS or bipolar circuits with SiGe-base, particularly for use in mobile telecommunication circuits.
BACKGROUND OF THE INVENTION Advanced silicon bipolar, CMOS or BiCMOS circuits are used today for high-speed applications in the 1-5 GHz frequency range, replacing circuits previously only possible to realize using III-N based technologies.
High-performance bipolar integrated circuits are used extensively for critical building blocks in telecommunication circuits, mainly for the analog functions, e.g. for switching currents and voltages, and for the high-frequency radio circuit functions in e.g. mixers, amplifiers, detector etc.
A common problem in all self-aligned double poly-Si processes is the removal of the (poly-) silicon used for the extrinsic base in the emitter opening without etching down into the monocrystalline silicon. Typically, a certain degree of overetching down into the substrate is allowed, at least in a process where the base is formed by ion implantation after the etching. However, in the manufacture of bipolar transistors having an epitaxially formed base, formed prior to the emitter window etching, such overetching is not allowed and, thus, this etching becomes very critical.
SUMMARY OF THE INVENTION
The object of the invention is to provide a simple solution for removing the polysilicon used for the extrinsic base in the emitter window. No etching is allowed into the layer that will be used as intrinsic base and that already has been formed, typically an epitaxially grown base layer containg SiGe.
This is attained by the method according to the invention of forming a base region and an emitter window for a silicon bipolar transistor on a silicon substrate, comprising forming an intrinsic base layer containing SiGe, on top of the substrate, forming a layer of Si02 on the intrinsic base layer, forming an extrinsic base layer containing Si, on top of the Si02 layer, forming a layer of a dielectric on top of the extrinsic base layer, patterning the emitter window on top of the dielectric, and etching out the emitter window selectively down to the Si02 layer, in that the structure is exposed to HF to remove the Si02 layer in the emitter window, and Si is selectively deposited on the exposed intrinsic base layer and exposed side walls of the extrinsic base layer as well as in cavities created in the Si02 layer and the dielectric by the exposure to HF to establish contact between the extrinsic base layer and the intrinsic base layer.
The selective filling process will not suffer from pattern density effect, i.e. loading. Thus, the method according to the invention will therefore have a much larger process margin.
BRIEF DESCRIPTION OF THE DRAWING
The invention will be described more in detail below with reference to the appended drawing on which Figs. 1 - 4 illustrate successive known steps in connection with the fabrication of a silicon bipolar transistor on a silicon substrate, and Figs. 5 and 6 illustrate two steps according to the invention.
DESCRIPTION OF THE INVENTION
Shown in Fig. 1 is a silicon substrate 1, wherein the silicon is preferably monocrystalline. In a manner known per se, a multilayer structure of Si and SiGe layers with added dopants, typically boron, and possibly other materials such as C is formed as an intrinsic base layer 2 on the substrate. The top layer of the intrinsic base layer 2 usually consists of a couple of hundred A buffer layer of undoped Si. The total thickness of the intrinsic base layer 2 is 1000-1500 A typically.
A protective layer 3 of Si02, typically 100 A, is formed on the intrinsic base layer 2, either by deposition of a TEOS layer, thermal oxidation at low temperature (<= 800 °C) or combinations thereof as shown in Fig. 2.
To make this protective layer 3 porous and easily etched by HF in a later step, it can purposely be damaged by exposure to plasma, such as used in a dry-etching system.
In accordance with the invention, a predetermined region of the protective layer 3 can be protected from exposure to plasma by applying a photoresist layer (not shown) and patterning it. The purpose of the photoresist layer is to prevent the predetermined region from being damaged by the plasma. This will be further described in connection with Fig.
5.
The processing then continues according to the standard flow by deposition of a layer containing Si, on top of the Si02 layer. This Si layer will serve as extrinsic base layer 4 as shown in Fig. 3. The material of the extrinsic base layer 4 can be polysilicon, α-Si, SiGe, etc. An ion implantation (boron) is performed to heavily dope the Si layer to p-type in a manner known per se.
A layer 5 of a dielectric is then formed on top of the extrinsic base layer 4 in that an oxide (TEOS) layer is deposited as also shown in Fig. 3. Typical thicknesses of the silicon and oxide layers are 1000-2000 A each.
An emitter window is patterned on top of the dielectric in that a photoresist mask 6 defining the emitter window opening and outside edges of a base contact is applied on top of the dielectric 5 as also illustrated in Fig. 3. It is understood that Fig. 3 only shows half a symmetrical emitter-base structure of the transistor.
The TEOS/silicon stack in Fig. 3 is then etched down to the Si02 layer 3 that is used as a stopping layer ("stop-on-oxide"). In the etching process, the selectivity between oxide
and silicon and end-point detection is used to carefully stop the etching within the oxide layer. The etched down structure is shown in Fig. 4.
In accordance with the invention, to remove the Si02 layer 3 in the emitter window the structure in Fig. 4 is exposed to HF, preferably HF vapor, while the photoresist still remains on top of the dielectric layer 5.
Si02 will also be removed under the extrinsic base layer 4 causing cavities 7 to be formed. The extent of the cavities 7 can be controlled by the size of the protected region on the protective layer 3, in that the Si02 etch rate will be lower in the protected region.
Si02 will also be removed under the edges of the dielectric 5 causing cavities 8 to be formed as indicated in Fig. 5.
In Fig. 5, the photoresist has been removed using conventional methods.
Then in accordance with the invention, using properties of UHN-CND epitaxial deposition, e.g. the deposition method that can be used to form the intrinsic base layer 2, a layer 9 of Si is selectively deposited on the exposed silicon areas of the structure, i.e. on the exposed intrinsic base layer 2 and exposed side walls of the extrinsic base layer 4 as well as in the cavities 7, 8 created in the Si02 layer 3 and the dielectric 5 by the exposure to HF in order to establish contact between the extrinsic base layer 4 and the intrinsic base layer 2.
Approximately up to 300 A of Si can selectively be deposited using this method. The Si layer 9 will fill the cavities 7, 8, forming a good extrinsic base contact path to the substrate 1. The resulting structure is shown in Fig. 6.
Processing continues according to conventional process flow with spacer and emitter formation etc.
Claims
1. A method of forming a base region and an emitter window for a silicon bipolar transistor on a silicon substrate, comprising - forming an intrinsic base layer containing SiGe, on top of the substrate,
- forming a layer of Si02 on the intrinsic base layer,
- forming an extrinsic base layer containing Si, on top of the Si02 layer,
- forming a layer of a dielectric on top of the extrinsic base layer,
- patterning the emitter window on top of the dielectric, and - etching out the emitter window selectively down to the Si02 layer, characterized by
- exposing the structure to HF to remove the Si02 layer in the emitter window, and
- selectively depositing Si on the exposed intrinsic base layer and exposed side walls of the extrinsic base layer as well as in cavities created in the Si02 layer and the dielectric by the exposure to HF to establish contact between the extrinsic base layer and the intrinsic base layer.
2. The method according to claim 1, characterized by exposing part of the layer of Si02 on the intrinsic base layer to plasma before forming the extrinsic base layer.
3. The method according to claim 1, characterized by exposing the whole layer of Si02 on the intrinsic base layer to plasma before forming the extrinsic base layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AU2003224582A AU2003224582A1 (en) | 2002-05-08 | 2003-05-06 | A method of forming base regions and emitter windows in silicon bipolar transistors |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE0201425A SE522916C2 (en) | 2002-05-08 | 2002-05-08 | Method for forming base regions and emitter windows in bipolar silicon transistors |
| SE0201425-6 | 2002-05-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2003096404A1 true WO2003096404A1 (en) | 2003-11-20 |
Family
ID=20287835
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/SE2003/000698 WO2003096404A1 (en) | 2002-05-08 | 2003-05-06 | A method of forming base regions and emitter windows in silicon bipolar transistors |
Country Status (3)
| Country | Link |
|---|---|
| AU (1) | AU2003224582A1 (en) |
| SE (1) | SE522916C2 (en) |
| WO (1) | WO2003096404A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9159817B2 (en) | 2013-11-19 | 2015-10-13 | International Business Machines Corporation | Heterojunction bipolar transistors with an airgap between the extrinsic base and collector |
| WO2021252069A1 (en) * | 2020-06-11 | 2021-12-16 | Massachusetts Institute Of Technology | Bipolar junction transistor optical modulator |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0483487A1 (en) * | 1990-10-31 | 1992-05-06 | International Business Machines Corporation | Self-aligned epitaxial base transistor and method for fabricating same |
| US5502330A (en) * | 1995-02-23 | 1996-03-26 | Texas Instruments Incorporated | Stacked barrier-diffusion source and etch stop for double polysilicon BJT with patterned base link |
| US5656515A (en) * | 1996-07-18 | 1997-08-12 | Lucent Technologies, Inc. | Method of making high-speed double-heterostructure bipolar transistor devices |
| WO2001039264A1 (en) * | 1999-11-26 | 2001-05-31 | Telefonaktiebolaget Lm Ericsson | Method in the fabrication of a silicon bipolar transistor |
| WO2002043132A1 (en) * | 2000-11-22 | 2002-05-30 | Conexant Systems, Inc. | Method for fabricating a self-aligned emitter in a bipolar transistor |
-
2002
- 2002-05-08 SE SE0201425A patent/SE522916C2/en unknown
-
2003
- 2003-05-06 WO PCT/SE2003/000698 patent/WO2003096404A1/en not_active Application Discontinuation
- 2003-05-06 AU AU2003224582A patent/AU2003224582A1/en not_active Abandoned
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0483487A1 (en) * | 1990-10-31 | 1992-05-06 | International Business Machines Corporation | Self-aligned epitaxial base transistor and method for fabricating same |
| US5502330A (en) * | 1995-02-23 | 1996-03-26 | Texas Instruments Incorporated | Stacked barrier-diffusion source and etch stop for double polysilicon BJT with patterned base link |
| US5656515A (en) * | 1996-07-18 | 1997-08-12 | Lucent Technologies, Inc. | Method of making high-speed double-heterostructure bipolar transistor devices |
| WO2001039264A1 (en) * | 1999-11-26 | 2001-05-31 | Telefonaktiebolaget Lm Ericsson | Method in the fabrication of a silicon bipolar transistor |
| WO2002043132A1 (en) * | 2000-11-22 | 2002-05-30 | Conexant Systems, Inc. | Method for fabricating a self-aligned emitter in a bipolar transistor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9159817B2 (en) | 2013-11-19 | 2015-10-13 | International Business Machines Corporation | Heterojunction bipolar transistors with an airgap between the extrinsic base and collector |
| WO2021252069A1 (en) * | 2020-06-11 | 2021-12-16 | Massachusetts Institute Of Technology | Bipolar junction transistor optical modulator |
| US11624941B2 (en) | 2020-06-11 | 2023-04-11 | Massachusetts Institute Of Technology | Bipolar junction transistor optical modulator |
Also Published As
| Publication number | Publication date |
|---|---|
| SE522916C2 (en) | 2004-03-16 |
| SE0201425L (en) | 2003-11-09 |
| SE0201425D0 (en) | 2002-05-08 |
| AU2003224582A1 (en) | 2003-11-11 |
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